JPH10162108A - Data storage body - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data storage body that eliminates the need for a capacitor for power supply at memory writing time. SOLUTION: The data storage body 100, which receives supply of electric power and a write command to a memory 11 by an electromagnetic inductive coupling system utilizing the mutual induction of a coil 3 or the induced electromagnetic field of an antenna, is provided with a battery 101, which is connected to a power supply line Va reaching at least the memory 11, an opening/closing means 102 which is interposed in the power supply line Va, and an opening/ closing means 103 which controls and closes the opening/closing means 102 after receiving the write command.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage device such as an IC card or a data carrier which communicates with a reader / writer or the like by an electromagnetic induction coupling system and receives power required for operation of a memory or a control circuit. The present invention relates to an improvement when a battery is used in combination to supply power for writing to a memory.

[0002]

2. Description of the Related Art An IC card 20 shown in FIG. 6 as a conventional data storage unit communicates with a reader / writer 1 by an electromagnetic induction coupling method utilizing mutual induction of coils or an induction electromagnetic field of an antenna. These are systems in which the reader / writer 1 accesses the IC card 20 which is close to a communicable place by communication and transmits / receives data, thereby reading / writing data without contact. Such an IC card 20 is formed in a shape suitable for carrying, such as a tag type, in addition to a card type, and the system is applied to management of door entry / exit, an automatic ticket gate, and the like. The IC card 20 receives power necessary for operation of a memory, a control circuit, and the like from the reader / writer 1 coupled as a communication partner by an electromagnetic induction coupling method in order to avoid troublesome battery replacement and the like. A power supply voltage is generated by rectifying and storing an induced current caused by an induction action / induction electromagnetic field.

More specifically, the reader / writer 1 emits energy by transmitting a carrier wave of a predetermined frequency through the coil 2 and modulates the carrier wave, thereby transmitting a read command or a write command (write command). Transmission and the like are performed.
Is provided with a coil 3 for receiving the carrier. Note that a resonance capacitor 4 is connected to the coil 3 in parallel. In the IC card 20, a rectifier 5 having an input terminal connected to both ends of the coil 3 is provided, and a storage / smoothing capacitor 6 is connected between both output terminals. As a result, the induced current of the carrier wave is rectified in full-wave or half-wave, and the power supply voltage V
out is generated.

In the IC card 20, a clock signal generating circuit 7 and a communication section 8 are provided for the rectifier 5, and a power supply voltage Vout from the rectifier 5 is used to reset a reset signal generating circuit 9, a control section 10, EEP as memory
The data is sent to the ROM 11. The clock signal generation circuit 7 shapes the voltage signal generated in the rectifier 5 into a clock signal CLK by performing waveform shaping or the like, and converts the voltage signal into a clock signal CLK.
And so on. The communication unit 8 performs a process such as demodulation on the induced voltage of the coil 3 or the voltage signal generated in the rectifier 5 to generate a reception signal RCV,
When receiving the transmission signal SND from the control unit 10, the control unit 10 performs processing such as modulation and transmits the signal to the reader / writer 1 via the coil 3.

The reset signal generating circuit 9 shown in detail in FIG. 7 includes a comparator and a reference voltage source that operate by receiving the supply voltage Vout, and includes a reference voltage Vref from the reference voltage source and a supply voltage Vout. By comparing the divided voltage value of the resistor with the comparator, the supply power supply voltage Vout
Generates a reset signal RST that becomes significant at less than 2V. The reset signal RST is controlled by the control unit 10 and the EEPROM.
The circuits 10 and 11 operate only when the supply voltage Vout is 2 V or more.

The control unit 10 comprises a microprocessor system or a logic circuit / sequential circuit. The control unit 10 receives a command or data from the reader / writer 1 in response to a received signal RCV, and receives a memory control signal CTL or a data signal DA.
It generates T and sends it to the EEPROM 11 for control, or conversely generates a transmission signal SND based on the data signal DAT from the EEPROM 11 and sends it to the communication unit 8. In the control unit 10, in order to support writing to the memory, a write command detecting unit for detecting a write command from the reader / writer 1 is implemented by program processing or by using a decoder or the like. As a result, a write command detection signal is output as a pulse. Following this pulse, a memory control signal CTL and a data signal D according to a series of write control timings are output.
An AT is generated.

[0007] The EEPROM 11 is a non-volatile memory that can be rewritten bit by bit. In applications where memory capacity is important, a flash memory that can be erased in block units may be used instead. In this type of memory, writing tends to take a long time, and power consumption during writing tends to be large. Therefore, a large-capacity ripple capacitor 12 and a Schottky diode D0 are introduced in order to separately secure power at the time of memory writing.
The ripple capacitor 12 is connected between the line of the power supply voltage Vout to the EEPROM 11 and the ground voltage GND, and the diode D0 is inserted in series with the line of the power supply voltage Vout from the connection point of the ripple capacitor 12 to the rectifier 5 side. Is done. Thus, the memory power supply voltage Vd supplied to the EEPROM 11 is maintained at the peak value of the power supply voltage Vout or a value close to the peak value in preparation for memory writing.

The IC card 20 having such a configuration approaches the reader / writer 1 until communication is possible and receives energy from the reader / writer 1 via the coils 2 and 3. Vout rises to a value operable beyond 2V. Specifically, referring to the waveform example of FIG. 8, the voltage almost reaches 4 V at time t0. Although the memory power supply voltage Vd is also lower by about 0.1 V, the waveforms are almost the same. In this state, when a write command is received from the reader / writer 1 (see t1 in FIG. 8), the control unit 10 controls writing to the EEPROM 11 (see t2 to t5 in FIG. 8). During this time, 10ms
Takes a degree. Also, during this time, a large amount of power is consumed by the EEPROM 11, so if the ripple capacitor 12 is not provided, the supply power supply voltage Vout drops rapidly and becomes inoperable (see two-dot chain lines Vout1, Vd1 in FIG. 8). EEPRO from large capacity ripple capacitor 12
Since power is supplied to M11, the supply power supply voltage Vout and the memory power supply voltage Vd are maintained at 3 V or more even when the writing is completed (see t5 in FIG. 8).
(See t7 in FIG. 8).

In the case of such an IC card 20, since it is often used by being held manually or by a tool, the IC card 20 is activated (movable) when moving in a range where communication with the reader / writer 1 is not possible. State) and a transitional state that transitions to an inactive state (inoperable state). Although a reset signal generation circuit 9 is provided to avoid unstable operation in this transition state, power supply may be suddenly cut off during processing depending on a use mode. In some cases, the circuit 9 alone cannot handle the problem. In particular, it is troublesome when the power supply to the EEPROM 11 is cut off when writing data. When a write operation is performed in the EEPROM 11, the internal storage element portion is initialized once, and then new data is written, which takes about 10 ms as described above. If the power supply voltage of the memory drops during this time or there is a large fluctuation in the power supply, it is possible that the memory remains initialized or even erroneous data is written.

On the other hand, the IC card 20 is provided with the ripple capacitor 12 for replenishing the power consumption at the time of writing in the memory.
4) Even when the power supply from the reader / writer 1 is suddenly cut off, the memory power supply voltage Vd changes almost in the same manner as in the normal state until the writing is completed (see the broken line Vd2 in FIG. 8). The capacitor 6 is connected to the control unit 10 other than the EEPROM 11.
And so on, the supply power supply voltage Vout does not drop rapidly. Thus, by using a large-capacity capacitor, the reliability of writing to the memory is ensured.

The IC card 21 shown in FIG. 9 is provided with an abnormal write voltage detecting circuit 22 which outputs a significant detection signal when the voltage falls below a predetermined abnormal write voltage, instead of providing the ripple capacitor 12. EE while the detection signal is significant
The control unit 2 suspends the write control to the PROM 11
3 has been revised. The abnormal write voltage is a value considerably higher than the reset voltage of 2 V, and is set to a value practically sufficient to complete the write process to the EEPROM 11 with the power from the capacitor 6. In this way, by limiting the writing process only when a reliable result can be expected, the reliability of writing to the memory is ensured.

As described above, in the conventional data storage unit, in order to ensure the reliability of writing to the memory against fluctuations in power reception, measures such as using a large-capacity capacitor or limiting the writing process are taken. Had been given. Further, the data may be carefully checked or corrected by writing the data to the memory and then reading and collating the data by the processing of the control unit. By taking these measures,
Even when an unexpected power supply abnormality occurs due to a mode of use by humans or the like, a fail-safe or fail-soft system can be constructed.

[0013]

However, when a large-capacity ripple capacitor is used for a memory, it depends on the type and storage capacity of the memory, but also in consideration of the variation in the capacity of the capacitor and the magnitude of aging. , And a ripple capacitor of several tens of μF is required. This not only hinders downsizing of the device due to its large shape, but also causes a significant increase in cost. On the other hand, detecting the abnormal write voltage exceeding the reset voltage and limiting the write process only when the power supply is sufficient is unsatisfactory in that the usable range of the device is reduced. Yes.

Therefore, it is an object to devise a circuit that can reduce the capacity of the memory without or without the ripple capacitor without limiting the writing process. The present invention has been made to solve such a problem, and an object of the present invention is to realize a data storage body that does not require a capacitor for supplying power during memory writing.

[0015]

SUMMARY OF THE INVENTION In order to solve such a problem, a data storage device of the present invention (as described in claim 1 at the time of the filing of the application) is provided with a mutual induction effect of coils or induction of an antenna. In a data storage unit that receives power supply and a write command to a memory by an electromagnetic induction coupling method using an electromagnetic field, at least a battery connected to a power supply line to the memory and a battery inserted into the power supply line Opening / closing means, and opening / closing control means for controlling the opening / closing means to a closed state after receiving the write command.

In such a data storage device of the first solution, the power required for the operation of the memory and its control circuit is supplied by the electromagnetic inductive coupling system for both communication and the use of a battery. Thus, when the power required for the operation of the memory is insufficient, the shortage of the power is supplied from the battery via the power supply line. An opening / closing means is interposed in the power supply line, and the opening / closing means is closed by the opening / closing control means after receiving the write command. Becomes conductive. Then, the battery can be supplied with power to the memory.

That is, a battery is used in combination to replenish insufficient power at the time of writing to the memory or the like, and the writing process to the memory is reliably performed. However, power can be supplied to the memory by the battery. This is at the time of writing to the memory or an important processing equivalent thereto. Thus, battery consumption is suppressed. Thus, even in a harsh environment or the like in which a sudden change in the power supplied by the electromagnetic induction coupling method is required, the battery does not need to be replaced for a long time, and at least high reliability of data writing to the memory is ensured. be able to.

Therefore, the ripple capacitor of the memory can be omitted even if the write abnormal voltage exceeding the reset voltage is detected and the write process is not limited only when the power supply is sufficient. Alternatively, even if not omitted, the capacity of the capacitor can be reduced to a place close to it. Therefore, according to the present invention, it is possible to realize a data storage body that does not require a capacitor for power supply at the time of memory writing.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment for implementing the data storage of the present invention achieved by such a solution will be described.

[First Embodiment] A first embodiment of the present invention (as described in claim 2 at the beginning of the application) is a data storage unit of the above-mentioned solving means, wherein the opening / closing control means is provided. Controls the opening and closing of the opening / closing means after maintaining the closing state of the opening / closing means for at least a fixed time exceeding the writing time to the memory. As a result, power is reliably supplied from the battery until an important process such as writing to the memory is completed, and waste of the battery is prevented after the process is completed. In addition, the fixed time facilitates the realization by a window pulse generating circuit or a program processing in a loop.

[Second Embodiment] A second embodiment of the present invention is a data storage device according to the above-described solving means and the embodiment, wherein the power supply line is controlled in addition to the memory. It also extends to circuits and reset signal generation circuits. As a result, while power is being supplied by the battery, the undesired occurrence of a reset signal being output due to fluctuations in the power supply voltage and interrupting the writing to the memory is reduced.

[Third Embodiment] A third embodiment of the present invention is a data storage device according to the above-described solving means and the embodiment, wherein the battery, the opening / closing means, and the opening / closing control means comprise: It is provided instead of, or in addition to, a ripple capacitor for the power supply of the memory. If the ripple capacitor is replaced and omitted, the number of large-capacity and bulky elements is reduced, so that the cost and size of the device can be reduced. Even when a ripple capacitor is used together, the capacitor requires only a relatively small capacity and small size.In addition, the battery life is remarkably small because little or no power is supplied by the battery except in abnormal or emergency situations. Extend.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the data storage of the present invention will be described.
The specific configuration will be described with reference to the drawings. FIG.
FIG. 2 is a circuit block diagram of the counter circuit, FIG. 2 is a circuit diagram of the counter circuit, and FIG. 3 is a circuit diagram of the reset signal generation circuit. The IC card 100 as the data storage includes a ripple capacitor 12 and a diode D
This is different from the IC card 20 of the conventional example in that a battery 101 and the like are introduced instead of 0.

Therefore, the repeated explanation is omitted,
Hereinafter, the difference will be mainly described, but together with the battery 101, a transistor 102 as opening / closing means, a counter circuit 103 as opening / closing control means, and Schottky diodes D1, D2, D3, and D4 for selecting a high voltage are provided. It was added. Further, the reset signal generation circuit 90 has been partially changed. Specifically, a small lithium battery having an output voltage of about 3 V is used as the battery 101, and its negative terminal is connected to the line of the ground voltage GND.

As the transistor 102, an enhancement type P-channel MOS transistor is used.
Its source is connected to the positive terminal of the battery 101, and its drain is connected to the anode of the diode D4. The cathode of the diode D4 has an anode connected to the power supply voltage Vou.
via the line of the memory power supply voltage Vb together with the cathode of the diode D3 connected to the line of
11 power supply terminal Vin. Thereby, the battery 1
A power supply line from 01 to the EEPROM 11 via the transistor 102 and the diode D4 is defined, and the transistor 102 is interposed in the power supply line so that the line can be turned off (open / closed).

The counter circuit 103 is mainly composed of a binary counter which receives a write command detection signal A, which is a pulse transmitted when a write command is received by the write command detection means of the control unit 10, at a count value clear terminal Clr. The carry or the output of the upper bit (Out) of this counter is inverted and then sent out as the switching control signal B. Further, the clock terminal CK of the counter is output.
And the logical product of the switching control signal B by the AND gate and the clock signal CLK. Therefore, the counter circuit 103 generates the switching control signal B of the window pulse. The original signal of the switching control signal B is extracted from the bit position corresponding to the count value such that the pulse width becomes equal to or longer than the writing time to the EEPROM 11. It is. This allows
The counter circuit 103 controls the transistor 102 to be in a conductive (closed) state after receiving the write command, and at the same time, keeps the transistor 102 in a conductive state for at least a certain period of time exceeding the writing time to the memory, and then shuts off. (Open) state is controlled.

A diode D1 is inserted and connected in series with the supply power supply voltage Vout connected to the power supply terminal Vin of the control unit 10 with the cathode facing the control unit 10, so that the logic power supply voltage is used instead of the supply power supply voltage Vout. Vc is sent to the control unit 10. Further, a diode D2 having an anode connected to the anode of the diode D4 has a cathode connected to the line of the logic power supply voltage Vc together with the diode D1. This line of the logic power supply voltage Vc is connected to the reset signal generation circuit 90 in addition to the counter circuit 103. As a result, the power supply line
In addition to the EEPROM 11, the control unit 10, the counter circuit 103, and the reset signal generation circuit 90 are also reached. The reset signal generating circuit 90 is modified so that the comparator and the reference voltage source operate by receiving the logic power supply voltage Vc instead of the supply power supply voltage Vout. Then, the reference voltage Vref and the power supply voltage V
out is compared to generate a reset signal RST. As a result, the reset signal RST is not made significant while the power is being supplied by the battery 101 at the time of memory writing, even if the supply power supply voltage Vout becomes 2 V or less.

The usage and operation of the data storage of this embodiment will be described with reference to the drawings. FIG.
8 shows an example of a signal waveform at the time of memory writing in the IC card 100.

The IC card 100 having such a configuration approaches the reader / writer 1 until communication is possible and receives energy from the reader / writer 1 via the coils 2 and 3. When Vout exceeds 2 V, the reset state due to the reset signal RST is released and operation becomes possible. Then, as shown in FIG.
At 0, the supply power supply voltage Vout, the memory power supply voltage Vb, and the logic power supply voltage Vc all reach approximately 4V. During this time, since the switching control signal B remains at the initial value, the transistor 10
Reference numeral 2 denotes a cutoff state, in which the power of the battery 101 is not consumed.

When a write command is received from the reader / writer 1 in this state, a pulse of the write command detection signal A is output (see t1 in FIG. 4), and subsequently, a window pulse of the switching control signal B is also output (see FIG. 4). 4 t1 to t
6). As a result, the transistor 102 is turned on, but the power supply voltage Vout is higher than the battery voltage Va, so that the power of the battery 101 is not consumed yet. Then, during the period of the window pulse, the control unit 10 controls the EEPRO through the memory control signal CTL.
Write control to M11 is performed (t2 to t5 in FIG. 4).
reference).

At this time, since much power is consumed by the EEPROM 11 and there is no ripple capacitor 12,
The power supply voltage Vout or the like rapidly drops (from t2 in FIG. 4).
t3). However, the supply voltage Vout is equal to the battery voltage Vout.
When the voltage drops to the point a, the magnitude relationship between the supply power supply voltage Vout and the battery voltage Va is reversed, so that the required power is supplied from the battery 101, thereby providing the supply power supply voltage Vout and the memory power supply voltage Vb. , The logic power supply voltage Vc stops falling near the battery voltage Va, and the state continues to complete the writing to the EEPROM 11 (see t3 to t5 in FIG. 4). Thereafter, the supply power supply voltage Vout and the like quickly recovers and rises (see t6 to t7 in FIG. 4).
On the way, with the end of the window pulse of the switching control signal B, the transistor 102 returns to the cut-off state, and thereafter the power consumption of the battery 101 is prevented.

Thus, in the IC card 100, power is supplied by the battery only when writing to the memory. Therefore, even without the ripple capacitor 12, the processing of the write command can be reliably performed. Further, even when the power supply from the reader / writer 1 is suddenly interrupted during the writing process (time t4), the memory power supply voltage Vb and the logic power supply voltage Vc are maintained until the window pulse of the switching control signal B ends. Maintain the voltage near the battery voltage Va (see the broken line Vb2 in FIG. 4), so that the writing to the memory is completed in this case as well. It is not necessary for the capacitor 6 to cover the power of the control unit 10 and the like other than the EEPROM 11, so that the supply power supply voltage Vout only drops slowly. Thus, the reliability of writing to the memory can be ensured without using a large-capacity capacitor.

The IC card 200 shown in FIG.
A comparatively small ripple capacitor 201 is used in place of the conventional ripple capacitor 12. The aforementioned memory power supply voltage Vb (or logic power supply voltage Vc)
And the ground voltage GND line, a ripple capacitor 201 is connected, and the diode D0 is connected to the ripple capacitor 20 with respect to the memory power supply voltage Vb line.
1 is inserted in series from the connection point to the battery 101 side. Thus, the memory power supply voltage Vb supplied to the EEPROM 11
Is supplied by the ripple capacitor 201, and power is supplied from the battery 101 only when the ripple capacitor 201 cannot supply enough power during memory writing. The capacity of the ripple capacitor 201 is sufficient even if it is a fraction of the ripple capacitor 12 or less.

[0034]

As is apparent from the above description, in the data storage of the present invention, the power is supplied from the battery during the writing to the memory or the important processing equivalent thereto, and the processing is completed. This has the advantageous effect of eliminating the need for a large-capacity capacitor for power supply during memory writing. In addition, since the consumption of the battery is suppressed, even if the battery is used in combination, there is almost no need to replace the battery, so that there is no need for maintenance and the like.

[Brief description of the drawings]

FIG. 1 shows a data storage device according to an embodiment of the present invention.
It is a circuit block diagram about C card.

FIG. 2 is a circuit diagram of the counter circuit.

FIG. 3 is a circuit diagram of the reset signal generation circuit.

FIG. 4 is an example of a signal waveform.

FIG. 5 is another embodiment of the data storage of the present invention.

FIG. 6 is a circuit block diagram of a conventional data storage body.

FIG. 7 is a circuit diagram of the reset signal generation circuit.

FIG. 8 is an example of a signal waveform.

FIG. 9 is a circuit block diagram of a conventional data storage body.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 reader / writer (data writing device) 2 coil (transmitting antenna) 3 coil (receiving antenna) 4 resonance capacitor 5 rectifier 6 capacitor 7 clock signal generation circuit 8 communication unit 9 reset signal generation circuit 10 control unit 11 EEPROM (non-volatile) Memory) 12 Ripple capacitor 20 IC card (data carrier; data storage) 21 IC card (data carrier; data storage) 22 abnormal writing voltage detection circuit 23 control unit 90 reset signal generation circuit 100 IC card (data carrier; data) Storage device 101 Battery 102 Transistor (opening / closing means) 103 Counter circuit (window pulse generating circuit; opening / closing control means) 200 IC card (data carrier; data storage body) 201 Ripple capacitor D0, D1, D2, D3, D4 Iode Vout Supply power supply voltage Va Battery voltage Vb Memory power supply voltage Vc Logic power supply voltage Vd Memory power supply voltage Vref Reference voltage GND Ground voltage A Write command detection signal B Switching control signal RST Reset signal CLK Clock signal RCV Receive signal SND Transmission signal CTL Memory control Signal CTL DAT data signal

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Megumi Iiyama 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. Inside

Claims (2)

[Claims] In a data storage body receiving power supply and a write command to a memory by an electromagnetic induction coupling system utilizing a mutual induction action of coils or an induction electromagnetic field of an antenna, at least a power supply line to the memory is provided. Data comprising: a connected battery; opening / closing means interposed in the power supply line; and opening / closing control means for controlling the opening / closing means to be closed after receiving the write command. Memory body. 2. The open / close control means controls the open / close means to be in an open state after the closed state of the open / close means is maintained for at least a fixed time exceeding a writing time to the memory. And the data storage.