JPH10143117A - Active matrix display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix display device reducing current consump tion in a signal driver. SOLUTION: A vertical scanning circuit 1 line sequentially scans a gate line G, and selects pixels 4a, 4b, 4c,... by a row at every a horizontal period. The signal driver 2 outputs a video signal through video lines V. A horizontal scanning circuit 3 outputs a sampling pulse for performing point sequentially the write-in of the video signal in the pixels 4a, 4b, 4c,... by one row selected in one horizontal period. Cross switches 5a, 5b, 5c,... exist on one ends of signal lines S, and are connected to the video lines V, and open/close operate according to the sampling pulse. Then, the switches supply the video signal to the signal lines S, and write the video signal in the pixels 4a, 4b, 4c,....

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix display device, and more particularly to an active matrix display device having a row-like gate line, a column-like signal line, and a matrix-like pixel arranged at each intersection of the two. It relates to a display device.

[0002]

2. Description of the Related Art Liquid crystal displays have the characteristics that they can be easily made thinner, consume less power, and are easier to colorize, and are widely used for display screens of OA equipment and the like. In recent years, an active matrix type TFT liquid crystal display (AM-TFT LCD: Active Matrix-Thin Fil) has been developed.
m Transistor Liquid Crystal Display) has become mainstream. The thin film transistor is arranged as a switch for applying a voltage to each dot of the display, and is excellent in contrast, response speed, color purity, and the like.

FIG. 5 is a configuration diagram of an active matrix TFT liquid crystal display. Active matrix T
The FT liquid crystal display includes a row-shaped gate line G and a column-shaped signal line S. In addition, matrix liquid crystal pixels LC1, LC2,... Are arranged at the intersection of the two.
Each of the liquid crystal pixels LC1, LC2,... Is driven by a thin film transistor Tr1, Tr2,.

[0006] The vertical scanning circuit 10 includes a gate line G
Are line-sequentially scanned, and one row of liquid crystal pixels L
C1, LC2,... Are selected. The horizontal scanning circuit 30
Sequentially samples the video signal to each signal line S within one horizontal period.

Each signal line S is connected to a horizontal switch (HSW1,
HSW2, HSW3,...) Are connected to the video line V and supplied with a video signal from the signal driver 20. The horizontal scanning circuit 30 sequentially outputs horizontal sampling pulses A1, A2, A3,.
SW2, HSW3,... Are opened and closed.

In this way, HSW1, HSW2, H
SW3,... Are sampling pulses A1, A2, A3,
, And the video signal is sampled on the corresponding signal line S. Then, the video signal is written to the selected liquid crystal pixels LC1, LC2,... For one row.

[0007]

However, in the above-described conventional technique, as the number of video lines V increases, the wiring cross capacitance also increases.

FIG. 6 shows a conventional video line V and a signal line S.
FIG. 4 is a diagram showing a wiring cross capacitance of FIG. Here, the configuration when the HSW is sampled simultaneously is shown as one unit. The wiring cross capacitance between the video lines V1 to V6 and the signal lines S1 to S6 that straddle the video lines is represented by C1. Further, video lines V1 to V6 and HSW1 to 6
Is represented by C2.

In one unit, when there are N video lines, the wiring cross capacitance per video line is HS
When W1 to W6 are off, (N-1) C1 + C2. In the figure, since there are six video lines, the wiring cross capacitance per line is 5C1 + C2.

For example, since the wiring cross capacitance of the video line V6 is in a range 200 surrounded by a dotted line, 5C1 + C
2. Similarly, the wiring cross capacitance of the video line V5 is 5C1 + C2 because it is the range 210 surrounded by the broken line.

Further, when HSW1 to HSW6 are on, the wiring cross capacitance per video line when there are N video lines is (N-1) C1 + C2 + CS in addition to the signal line capacitance CS (not shown). Becomes

As described above, when the number of video lines V is increased, there is a problem that the wiring cross capacitance is increased regardless of whether the HSWs 1 to 6 are turned on or off, and the current consumption of the signal driver 20 is increased.

The present invention has been made in view of the above points, and has as its object to provide an active matrix display device that reduces current consumption of a signal driver.

[0014]

In order to solve the above-mentioned problems, the present invention comprises a row-like gate line, a column-like signal line, and a matrix-like pixel arranged at each intersection of the two. In the active matrix display device, a vertical scanning circuit for line-sequentially scanning the gate lines to select the pixels for one row every one horizontal period, a signal driver for outputting a video signal through a video line, A horizontal scanning circuit that outputs a sampling pulse for writing the video signal in a dot-sequential manner to the pixels of one row selected in the above, and the sampling pulse is connected to the video line at one end of the signal line. Open and close according to
And a cross switch for supplying the video signal to the signal line.

Here, the vertical scanning circuit scans the gate line line-sequentially and selects one row of pixels every one horizontal period. The signal driver outputs a video signal through a video line. The horizontal scanning circuit outputs a sampling pulse which is a drive signal for writing a video signal in a dot sequential manner to one row of pixels selected in one horizontal period. The cross switch is connected to a video line at one end of a signal line, and opens and closes in response to a sampling pulse.
Then, the video signal is supplied to the signal line, and the video is written to the pixel.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram of an active matrix display device of the present invention. The active matrix display includes a row-shaped gate line G, a column-shaped signal line S,
It has. The pixels 4a, 4b, 4c,... Are arranged at the intersection of the two.

The vertical scanning circuit 1 scans the gate line G line-sequentially and scans one row of pixels 4a, 4b, 4c,
Select…. The signal driver 2 outputs a video signal through a video line V. The horizontal scanning circuit 3 includes one row of pixels 4a, 4b, 4c,
.. Output a sampling pulse which is a drive signal for writing a video signal in a dot-sequential manner. The cross switches 5a, 5b, 5c,... Are connected to the video line V at one end of the signal line S, and open and close according to a sampling pulse. Then, the video signal is supplied to the signal line S, and the video is written to the pixels 4a, 4b, 4c,.

Next, the operation will be described. FIG. 2 is a flowchart illustrating an operation procedure of the active matrix display device. [S1] The vertical scanning circuit 1 scans the gate line G line-sequentially and selects one row of pixels 4a, 4b, 4c,... Every horizontal period. [S2] The signal driver 2 outputs a video signal through the video line V. [S3] The horizontal scanning circuit 3 outputs a sampling pulse for writing a video signal in a dot-sequential manner to one row of pixels 4a, 4b, 4c,... Selected within one horizontal period. [S4] The cross switches 5a, 5b, 5c,... Are connected to the video line V at one end of the signal line S, and open and close in response to a sampling pulse.
, And writes an image to the pixels 4a, 4b, 4c,.

Next, the cross switches 5a, 5
b, 5c,... will be described. FIG. 3 is a diagram illustrating a cross switch and a wiring cross capacitance. This is a case where the configuration when the HSW is simultaneously sampled is one unit and there are six video lines V and six signal lines S.

The signal driver 2 has a video line V1
To output a video signal through V6. Video line V1
Cross switches 5a to 5f are provided in the vicinity of the intersections between the signal lines S1 to S6 and the signal lines S1 to S6. Via these cross switches 5a to 5f, the signal line S1 is connected to the video line V1, the signal line S2 is connected to the video line V2, and thereafter the signal line S6 is connected to the video line V6. The horizontal scanning circuit 3 receives the cross switches 5a to 5a through a drive line D that outputs a sampling pulse.
Opening / closing control of each of 5f is performed.

A horizontal switch H is connected to one end of the signal line S.
SW1 to SW6 are connected, open and close in response to sampling pulses from the horizontal scanning circuit 3, and finally supply video signals to the signal lines S1 to S6.

The wiring cross capacitance between the video lines V1 to V6 and the signal lines S1 to S6 that cross the video lines is represented by C1. Further, a wiring cross capacitance between the video lines V1 to V6 and the drive line D is represented by C2.

When one unit has N video lines, the wiring cross capacitance per video line is HSW
When 1 to 6 are off, the cross switches 5a to 5f are also off, so they are 0.

When the HSWs 1 to 6 are turned on, the cross switches 5a to 5f are also turned on. Therefore, when there are N video lines, the wiring cross capacitance per video line is:
(N-1) C1 + C2. Therefore, since there are six video lines V, the wiring cross capacitance per line is:
5C1 + C2.

For example, since the wiring cross capacitance of the video line V6 is in a range 100 surrounded by a dotted line, 5C1 + C
2. Similarly, the wiring cross capacitance of the video line V5 is 5C1 + C2 because it is the range 110 surrounded by the broken line.

Further, taking into account the signal line capacitance CS (not shown), the video lines are substantially N in one unit.
When there are a plurality of video lines, the wiring cross capacitance per video line is (N-1) C1 + C2 + C in addition to the signal line capacitance CS.
S.

As described above, the active matrix display device of the present invention includes the cross switches 5a to 5f near the intersection of the video line V and the signal line S, and
Opening and closing operation according to the sampling pulse together with 1 to 6,
The video signal was supplied to the signal line S. As a result, the wiring cross capacitance when the HSWs 1 to 6 are turned off becomes almost 0, so that the current consumption of the signal driver 2 can be reduced.

Next, an active matrix display device for supplying a video signal to the signal line S with only the cross switches 5a to 5f excluding the HSWs 1 to 6 will be described. FIG.
FIG. 4 is a diagram illustrating a cross switch and a wiring cross capacitance,
This is a case where no SW is provided.

The signal driver 2 is connected to the video line V1
To output a video signal through V6. Video line V1
Cross switches 5a to 5f are arranged in the vicinity of the intersections between the signal lines S1 to S6 and the signal lines S1 to S6. Via these cross switches 5a to 5f, the signal line S1 is connected to the video line V1, the signal line S2 is connected to the video line V2, and thereafter the signal line S6 is connected to the video line V6. The horizontal scanning circuit 3 receives the cross switches 5a to 5a through a drive line D that outputs a sampling pulse.
Opening / closing control of each of 5f is performed.

Therefore, since the horizontal switches HSW1 to HSW6 are not provided at one end of the signal line S, the cross switches 5a to 5SW are not provided.
5f performs opening / closing operations in response to sampling pulses from the horizontal scanning circuit 3, respectively, and outputs video signals to the signal lines S1 to S
6 directly.

Further, a wiring cross capacitance between the video lines V1 to V6 and the signal lines S1 to S6 which cross the video lines is represented by C1. Further, a wiring cross capacitance between the video lines V1 to V6 and the drive line D is represented by C2.

When one unit has N video lines, the wiring cross capacitance per video line is 0 when the cross switches 5a to 5f are off. Furthermore, when one unit has N video lines, the video line 1
The wiring cross capacity per line is the cross switches 5a to 5
When f is on, (N-1) C1 + C2. In the figure, since there are six video lines, the wiring cross capacitance per line is 5C1 + C2.

Considering the signal line capacitance CS (not shown), the wiring cross capacitance per video line when one unit has N video lines is substantially equal to the cross switches 5a to 5f. At this time, the sum of the signal line capacitance CS and (N-1) C1 + C2 + CS is obtained.

As described above, the active matrix display device of the present invention is provided with the cross switches 5a to 5f in the vicinity of the intersection of the video line V and the signal line S to open and close according to the sampling pulse, and to perform the video signal To the signal line S
Was supplied directly to As a result, the wiring cross capacitance decreases, so that the current consumption of the signal driver 4 can be reduced. Further, the circuit scale can be reduced because it has no HSW.

[0035]

As described above, in the active matrix display device of the present invention, the cross switch is connected to one end of the signal line and the video line, and is opened and closed according to the sampling pulse, and the video signal is transmitted to the signal line. To be supplied. As a result, the wiring cross capacitance is reduced, so that the current consumption of the signal driver can be reduced.

[Brief description of the drawings]

FIG. 1 is a principle diagram of an active matrix display device of the present invention.

FIG. 2 is a flowchart illustrating an operation procedure of the active matrix display device.

FIG. 3 is a diagram showing a cross switch and a wiring cross capacitance.

FIG. 4 is a diagram illustrating a cross switch and a wiring cross capacitance, in a case without an HSW.

FIG. 5 is a configuration diagram of an active matrix TFT liquid crystal display.

FIG. 6 is a diagram showing a conventional wiring cross capacitance between a video line and a signal line.

[Explanation of symbols]

1. Vertical scanning circuit 2. Signal driver 3.
Horizontal scanning circuit, 4a, 4b, 4c... Pixels, 5a, 5
b, 5c ... cross switch.

Claims (1)

[Claims] 1. An active matrix display device comprising a row-shaped gate line, a column-shaped signal line, and a matrix-shaped pixel arranged at each intersection of the two, wherein the gate line is scanned line-sequentially. A vertical scanning circuit for selecting one row of the pixels every one horizontal period, a signal driver for outputting a video signal through a video line, and a dot driver for the one row of the pixels selected within one horizontal period. A horizontal scanning circuit that outputs a sampling pulse for writing a signal, and is connected to the video line at one end of the signal line;
An active matrix display device, comprising: a cross switch that opens and closes in response to the sampling pulse and supplies the video signal to the signal line.