JPH10126371A - Device and method for multiplexing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a reception-side buffer from overflowing or underflowing by entering a transport stream TS from an encoding device into a memory in its arrival order, and reading it in the storage order and multiplexing it. SOLUTION: Input parts 22A to 22N enter TS packets in pieces D4A to D4N of input information from encoding devices 7A to 7N into 1st memories 23A to 23N in the arrival order. Then data quantity detecting circuits 24A to 24N measure those TS packets and return discrimination signals 13, according to a rear signal S12 of a read circuit 31. A recognizing circuit 32 recognizes the input order of the input parts 22A to 22N and enters respective input part information r signals S15 into a 2nd memory 35, together with specific added write addresses. Then a multiplexer 37 reads the packets of the input part information S15 in the memory 35 out in the writing order and multiplexes them. Consequently, delay times accompanying the multiplexing process are held constant by the packets, and the buffer quantity on the reception side is adjusted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order.

2. Description of the Related Art Prior Art (FIG. 12) Problems to be Solved by the Invention (FIGS. 13 to 17) Means for Solving the Problems Embodiments of the Invention (1) First Embodiment (FIGS. 1 to 3) (2) Second Embodiment (FIGS. 4 to 11) Effects of the Invention

[0003]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexing apparatus and a multiplexing method, and is suitably applied to, for example, a digital broadcasting system.

[0004]

2. Description of the Related Art In recent years, MPEG2 (Moving Picture Experts) has been used as a compression encoding method for video data and audio data.
There is a method called Group Phase 2). This MPEG
The two systems are based on ITU-T (International Telecommunicat
ion Union-Telecommunication Standardization Secto
r: Standardized (for example, recommendation, H.222.0, etc.) by an organization such as the International Telecommunication Union Telecommunications Standardization Sector), compresses and encodes video and audio data, multiplexes them, and stores and transmits them. It is standardized for the purpose.

In the MPEG2 system, a program stream (PS: Program Stream) is actually used as a data format for multiplexing video data and audio data that have been compression-encoded.
m) (hereinafter referred to as PS data format) and a transport stream (TS: Transpo).
rt Stream) (hereinafter referred to as TS
Data format). By the way, PS
The data format is applied when multiplexed video data and audio data are stored in a predetermined digital storage medium, and the TS data format is applied when multiplexed video data and audio data are transmitted. .

Here, in the TS data format, for example, compression-encoded video data and audio data are packets in predetermined units (for example, 188-byte data amounts), respectively (hereinafter referred to as TS (Transport Stream) packets). )
It is defined that the resulting TS packets are time-division multiplexed to form a TS packet sequence (a so-called transport stream). As shown in FIG. 12, the TS packet 1 is composed of a header part and a data part, and the header part has a synchronization byte and a packet identifier (hereinafter, PID (Packet Identifier).
) and various other packet control data, and the data portion stores compression-encoded video data or audio data. Incidentally, the synchronization byte is data indicating the start of TS packet 1, and
D is data indicating the contents of the information stored in the TS packet 1.

By the way, in recent years, the above-described MPEG
2. Description of the Related Art A digital broadcasting system has been conceived in which video data and audio data are compression-encoded and multiplexed using two methods, and are broadcast using terrestrial waves, satellite waves, cables, or the like. In such a digital broadcasting system, it is conceivable that a plurality of television programs can be broadcasted on one line by compressing and encoding video data and audio data into TS packets and multiplexing them as described above. .

That is, this digital broadcasting system is actually applied to digital television broadcasting such as DVB (Digital Video Broadcasting). For example, when a broadcasting satellite is used as a transmission medium, about 20 to 30 transponders are usually provided for the broadcasting satellite. , And each transponder has a bandwidth of about 30 [Mbps]. Therefore, assuming that one transponder has a bandwidth of about 36 [Mbps] and that a bandwidth of about 4 [Mbps] is used for one television program on a channel, the following equation per transponder is used.

(Equation 1) It is believed that nine channel television programs can be broadcast simultaneously, as represented by. This is called multi-channeling (or multiplexing).

[0009]

FIG. 13 shows an example of the configuration of a transmitter 5 of such a digital broadcasting system. In this transmitter 5, each data output corresponding to a plurality of channels is provided. The video data D1A to D1N, the audio data D2A to D2N, and the program information data D3 corresponding to the television program from the units 6A to 6N, respectively.
A to D3N are supplied to the corresponding encoding devices 7A to 7N,
The corresponding video data D1A to D1N and audio data D2A to D2N and program information data D3A to D3N are compression-encoded and multiplexed by the MPEG2 system in each of the encoding devices 7A to 7N, and obtained in this manner. The multiplexed data is sequentially converted into T
The transport streams D4A to D4N are formed by S-packetization and supplied to the multiplexer 8.

In addition to this, in the transmitting device 5, the multiplexing information generating device 9 uses the data representing the contents of the television program for each channel (the name of the television program being broadcast, the television program table to be broadcast, etc.). Is compression-encoded by the MPEG2 system and multiplexed, and the multiplexed data obtained in this way is sequentially TS-packeted for each predetermined unit to form a transport stream D5 and a multiplexer. 8 Thereby, in the transmitting device 5, the multiplexing device 8 multiplexes the transport streams D4A to D4N and D5 to form one transport stream D6 and supplies the transport stream D6 to the modulator 10, and the modulator 10 Modulates the transport stream D6 by a predetermined method, and transmits the transmission signal S1 thus obtained to the antenna 1
1 to a broadcast satellite (not shown). Thus, the transmitting device 5 can simultaneously broadcast a plurality of television programs (for N channels) via a broadcasting satellite.

As shown in FIG. 14, the multiplexing device 8 includes transport streams D4A to D4 supplied from the encoding devices 7A to 7N and the multiplexed information generating device 9.
When multiplexing the 4N and D5, the plurality of TS packets TS1 to TS12 included in the transport streams D4A to D4N and D5 are sequentially read in the order in which they arrived and transmitted in that order. Execute the process.

That is, as shown in FIG.
For example, the transport stream D4A is formed such that the TS packets TS1 to TS9 are formed at different timings by the encoding devices 7A to 7N, for example.
.. D4N (FIGS. 15 (A), (B) and (C)) and supplying them to the multiplexing device 8, thereby multiplexing the TS packets arriving sequentially without duplication in the multiplexing device 8. To process. Therefore, in this transmitting device 5,
The order in which the TS packets TS1 to TS9 arrive at the multiplexing device 8, and the TS included in the transport stream D6 formed by the multiplexing process in the multiplexing device 8.
The order of the packets TS1 to TS9 becomes equal (FIG.
(D)).

As described above, in the digital broadcasting system, each TS packet TS included in the transport stream D6 received as the transmission signal S1 by the receiving device.
1 to TS12, TS packets TS1 to TS3 (FIG. 15E) corresponding to a desired channel, and TS packets T
S4 to TS6 or TS packets TS7 to TS9 are selected, and the selected TS packets TS1 to TS3, TS packets TS4 to TS6 or TS packets TS7 to TS9 are selected.
Are sequentially decoded in the order in which they are received, so that the video data, audio data, and program information data corresponding to the TS packets TA1 to TS9 can be correctly reproduced. Incidentally, each of the TS packets TS1 to TS9 included in the transport stream D6 formed in the multiplexing device 8 is delayed by the processing time Td required for the multiplexing process in the multiplexing device 8 (FIG. D)).

However, in each of the encoding devices 7A to 7N, the processing time required for the encoding process and the packetization varies depending on the amount of supplied video data, audio data, and program information data. It is conceivable that a plurality of other TS packets TS1 to TS9 are supplied to the multiplexer 8 while reading the TS packets TS1 to TS9 which have arrived earlier.

That is, as shown in FIGS. 16 (A) to 17 (B), the multiplexing device 8 usually includes the encoding devices 7A to 7A.
7N to transport streams D4A to D4D, respectively.
4N is supplied from the input unit, and a multiplexing unit that multiplexes the transport streams D4A to D4N from the input unit in such a manner that the transport streams D4A to D4N are sequentially read in units of TS packets TS10 to TS14 included therein. For example, the first TS packet TS10 corresponding to the television program of the first channel CH1 arrives at the input unit at the timing of, for example, time "n" when the first TS packet TS10 is formed.
A second TS packet TS11 corresponding to the television program of the fifth channel CH5 is supplied so as to arrive at the input unit at the timing of, for example, time "n + 1" when the television program of the fifth channel CH5 is formed, and the television program of the second channel CH2 is supplied. Is supplied such that it arrives at the input unit at the timing of, for example, the time "n + 2" at which it was formed (FIG. 16A).

In this case, the multiplexing device 8 first reads the first TS packet TS 10 arriving first at the input unit into the multiplexing unit, and during this time, reads the second TS packet TS 10 arriving at the input unit.
The packet TS11 is made to wait at the input unit, and then the third TS packet TS12 arriving at the input unit is also made to wait at the input unit. In this state, the third
No. 4 corresponding to the television program of channel CH3
The TS packet TS13 is supplied so that it arrives at the input unit at the timing of, for example, time “n + 3” when it is formed (FIG. 16B).

After that, in the multiplexing device 8, when the reading of the first TS packet TS10 by the multiplexing unit is completed, the second TS packet TS11 waiting at the input unit and the third TS packet TS11 next. Of the packet TS12,
One of them is read into the multiplexing unit. In this case, in the multiplexing unit, for example, the TS packets corresponding to the channel numbers are sequentially read in ascending order of the channel numbers, and accordingly, the third TS packet TS12 is read.
(Channel CH2) is read first, and the second TS packet TS11 (channel CH5) waits further. In this state, the fourth TS packet T
S13 arrives at the input unit and waits. Further, a fifth TS corresponding to the television program of the fourth channel CH4
When the packet TS14 is formed, for example, at time "n +
It is supplied so as to arrive at the input unit at the timing of "4" (FIG. 17A).

In this way, in the multiplexing device 8, when the reading of the third TS packet TS12 by the multiplexing unit is completed, the second TS packet TS1 in the standby state is set.
1 (channel CH5) and the fourth ST packet TS1
3 (channel CH3), the fourth TS packet TS13 is read by the multiplexing unit.
The TS packet TS11 waits again. In this state, the multiplexer 8 in the fifth TS packet TS1
4 arrives at the input unit and waits, so that the multiplexing unit
When the reading of the TS packet TS13 of the
TS packet TS11 (channel CH5) and the fifth
Of the TS packet TS14 (channel CH4), the fifth TS packet TS14 is read first, and the second TS packet TS11 stands by (FIG. 17B).

Accordingly, in such a case, the order in which the first to fifth TS packets TS10 to TS14 arrive at the multiplexer 8 and the transport formed by the multiplexer 8 in the multiplexing process. The order of the first to fifth TS packets TS10 to TS14 included in the stream D6 is different, and a desired first to fifth T packet among the first to fifth TS packets TA10 to TS14 in the receiving device is different.
When the S packets TS10 to TS14 are decoded and reproduced, the second TS packet TS11 waiting at the input unit of the multiplexer 8 is not received by the receiving device as shown in FIG. It is considered that a problem arises in that it is difficult to correctly reproduce video data, audio data, and program information data.

The present invention has been made in view of the above points, and an object of the present invention is to propose a multiplexing apparatus and a multiplexing method capable of correctly reproducing predetermined data corresponding to packet data in a receiving apparatus. .

[0021]

According to the present invention, there is provided a first storage means provided in correspondence with each channel to sequentially store packet data to be supplied, and a first storage means for sequentially storing the supplied packet data. Detecting means for detecting that one packet data is stored in the corresponding first storing means; and storing the data based on the detection results obtained from the respective detecting means. First to read packet data
Determining means for determining the order of the storage means, and multiplexing processing means for sequentially reading and multiplexing the packet data from each first storage means based on the order determined by the determining means. I do.

Further, in the present invention, a first step for sequentially storing packet data for each channel, and detecting that one packet data is stored for each channel, and storing the packet data based on the detection result. A second step for determining the order of reading packet data and a third step for sequentially reading and multiplexing the stored packet data based on the determined order are provided.

Accordingly, in the present invention, a first storage means provided in correspondence with each channel and sequentially storing the supplied packet data, and a first storage means provided in correspondence with each first storage means, respectively, are provided. The order of the detecting means for detecting that one piece of packet data is stored in the corresponding first storing means, and the order of the first storing means for reading out the stored packet data based on the detection results obtained from each of the detecting means are determined. By providing a deciding means for deciding and a multiplexing processing means for sequentially reading and multiplexing the packet data from each of the first storage means based on the order determined by the deciding means, a conventional multiplexing means is provided. By preventing packet data arriving at the input unit from being read out as in a multiplexing device and being kept in a standby state, Packet data can be reliably read from the first storage means in the order in which the packet data was written, whereby the order in which the packet data was written to the first storage means and the multiplexing process were performed. The order of the packet data included in the transport stream formed as described above can be made equal.

According to the present invention, packet data is sequentially stored for each channel, and then it is detected that one packet data is stored for each channel. Based on the detection result, the order of reading the stored packet data is determined. When the packet data reading order is determined as in a conventional multiplexing device, the stored packet data is sequentially read out and multiplexed based on the determined order. The packet data reading order can be easily determined without the need for complicated processing steps such as comparing and determining the time information indicating the arrival time added to the packet data, and the stored packet data is read in that order. The data can be sequentially read out and easily multiplexed.

Further, in the present invention, predetermined data of a plurality of systems supplied by a plurality of channels are packetized for each predetermined unit, and reference clock data is added to the packet, and each packet data thus obtained is sequentially multiplexed. In the multiplexing device for outputting the data, time information is added to the packet data stored in the storage means provided corresponding to each channel, and is read out from the storage means based on the time information of the packet data stored in the storage means. The reading order of the packet data is determined, the time required for multiplexing the packet data read from the storage means and multiplexed is detected based on time information, and based on the processing time detected by the detecting means. Correct the reference clock data of the packet data.

As described above, by making the reading order of the packet data read from the storage means coincide with the writing order, it is necessary for the multiplexing of the multiplexed packet data after being read from the storage means. The delay time can be kept constant. Further, by sharing the time information added to the packet data for reading from the storage means and for correcting the reference clock data of the multiplexed packet data, the configuration of the multiplexer can be simplified.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(1) First Embodiment In FIG. 1 in which corresponding parts in FIG.
Reference numeral 20 denotes a transmission device of the digital broadcasting system as a whole, which is configured similarly to the transmission device 5 of the digital broadcasting system shown in FIG.

As shown in FIG. 2, when the multiplexing device 21 multiplexes the transport streams D4A to D4N supplied from the encoding devices 7A to 7N, the multiplexing device 21 converts the transport streams D4A to D4N respectively. It is supplied to the corresponding input units 22A to 22N. Each of the input units 22A to 22N has the same configuration, and writes the TS packets included in the transport streams D4A to D4N respectively corresponding to the first memories 23A to 23N in the order in which they arrive.

Each of the data amount detection circuits 24A to 24N
Supplies the data amount measurement signal S10 to the corresponding first memories 23A to 23N, thereby measuring the data amount of the TS packets written in the first memories 23A to 23N. Here, the data amount detection circuits 24A to 24A
N is a data amount detection signal S11 having a logical "L" level.
When all TS packets (data amount of 188 bytes) are written in the corresponding first memories 23A to 23N based on the data amount measurement result by the data amount measurement signal S10, the data is read out. The amount detection signal S11 is raised to a logical "H" level.

On the other hand, in the decision circuit 30 of the multiplexing unit 27, the readout circuit 31 sends the readout signal S1 from the data amount detection circuit 24A to the data amount detection circuit 24N sequentially at a predetermined cycle.
When the read signal S12 is supplied to the data amount detection circuits 24A to 24N, the identification signal S13 for identifying the data amount detection circuits 24A to 24N is supplied to the recognition circuit 32.

Here, each data amount detection circuit 24A to 24N
Supplies the data amount detection signal S11 to the recognition circuit 32 when the read signal S12 is supplied. Incidentally, when each of the data amount detection circuits 24A to 24N supplies the data amount detection signal S11 to the recognition circuit 32 in a state where the data amount detection signal S11 has been raised to the logic "H" level, the data amount detection signal S11 is output. Thereafter, this is lowered to the logical "L" level, and the corresponding first memories 23A to 23A to 23L are respectively set.
The data amount detection signal S11 is raised to a logical "H" level when all of one TS packet is written again to 23N. Thus, each of the data amount detection circuits 24A to 24N can detect the TS packets written in the corresponding first memories 23A to 23N one by one.

The recognition circuit 32 includes a data amount detection circuit 24
When the data amount detection signal S11 is supplied from A to 24N, the input unit 22A having the data amount detection circuits 24A to 24N that output the data amount detection signal S11 based on the identification signal S13 supplied from the readout circuit 31. ~ 22
Identify N. The recognition circuit 32 also determines the data amount detection signal S based on the supplied data amount detection signal S11.
11 is at the logic "L" level, no TS packet has been written in the corresponding first memories 23A to 23N, and the first memories 23A to 23N store the TS packets.
When the data amount detection signal S11 is at the logical "H" level, it is recognized that the packet is out of the read target, and all the TS packets are written in the corresponding first memories 23A to 23N. And that the TS packets can be read from the first memories 23A to 23N.

Further, when the supplied data amount detection signal S11 is at the logic "H" level, the recognition circuit 32
The data amount detection signal S11 is digitized to generate input unit information representing the corresponding input units 22A to 22N, and the input unit information is supplied to the second memory 35 as the input unit information signal S15. In addition to this, the recognition circuit 32
Supplies a write control signal S16 specifying a predetermined write address (hereinafter referred to as an i address) to the second memory 35 together with the input section information signal S15. The writing is controlled, and the input section information is written to the address i of the second memory 35 in this way.

The recognizing circuit 32 sets the initial setting of the address i at which the input section information is written to the second memory 35 to, for example, address 0. Each time the input section information is written to the second memory 35, the address becomes 0. A write control signal S16 for designating the address i, which sequentially increases the address i by one, is supplied to the second memory 35, so that the input section information is sequentially written to the second memory 35. It has been done.

As a result, the recognition circuit 32 operates the input section 22A.
1N in which the TS packets supplied to .about.22N are written.
Of the memories 23A to 23N of the second memory 35 in accordance with the recognized order.
Are written sequentially. Thus, the determination circuit 10 can determine the order of the input section information sequentially written in the second memory 35 as the order of the first memories 23A to 23N when reading out the TS packets from the first memories 23A to 23N. Has been made.

Here, the multiplexer 37 outputs the read control signal S20 for designating the address i at which the input section information is first written in the second memory 35 as a read address (hereinafter referred to as an address j). Of the input unit information signal S15 by supplying the input unit information corresponding to the read control signal S20 to the input unit information signal S15.
Read as Thus, the multiplexer 37
Are the input units 22A to 22N represented by the read input unit information.
And reads the TS packet from the first memories 23A to 23N of the identified input units 22A to 22N as TS packet data D10.

Note that the multiplexer 37 sets the initial setting of the address j designated for reading the input section information from the second memory 35 to, for example, address 0 (similar to the above-mentioned address i), and inputs the address from the second memory 35. Each time the set information is read, a read control signal S20 for designating an address j, which sequentially increases the address j consisting of address 0 by one, is supplied to the second memory 35, whereby the second memory 35 , The input section information is sequentially read.

Thus, the multiplexer 37 writes the TS packets from the first memories 23A to 23N in the order in which they are written to the first memories 23A to 23N based on the input section information sequentially read from the second memory 35. The multiplexing process can be performed by sequentially reading.

Actually, as shown in FIGS. 3A to 3N,
The multiplexing device 21 transmits the transport stream D4
When executing the multiplexing process of A to D4N, first, as an initial operation, all the input section information written in the second memory 35 is deleted, and then the multiplexing process is executed. Here, each of the data amount detection circuits 24A to 24N corresponding to the channels CH1 to CHN is connected to the corresponding first memory 23.
A to 23N are supplied with a data amount measurement signal S10 at all times to measure the data amount in which the TS packets are written in the first memories 23A to 23N. Incidentally, at this time, the TS packets have not yet been written in the first memories 23A to 23N, and accordingly, the respective data amount detection circuits 24A to 24N.
Is a data amount detection signal S having a logical "L" level.
11 (FIGS. 3B, 3D, and 3F).

Thereafter, for example, from the encoding device 7A to the input unit 2
When the transport stream D4A is supplied to the first memory 23A of 2A, and all the one TS packet included in the transport stream D4A is written to the first memory 23A at the time t (a) (FIG. 3).
(A)), the data amount detection circuit 23A corresponding to the first memory 23A raises the data amount detection signal S11 having the logic “L” level to the logic “H” level at the time t (a) (FIG. 3). (B)).

Here, the readout circuit 31 sequentially supplies the readout signal S12 from the data amount detection circuit 24A to the data amount detection circuit 24N at a predetermined cycle shorter than the read time of the TS packet data D10 by the multiplexer 37.
In this case, the readout circuit 31 first supplies the readout signal S12 to the data amount detection circuit 24A at the time t (b) (FIG. 3 (I)), and identifies the data amount detection circuit 24A that supplied the readout signal S12. The identification signal S13 is supplied to the recognition circuit 32. At this time, the data amount detection circuit 2
4A supplies a data amount detection signal S11 having a logic "H" level to the recognition circuit 32 based on the supplied read signal S12 (FIG. 3 (J)). L ”level (Fig. 3
(B)).

The recognition circuit 32 generates a data amount detection signal S based on the identification signal S13 supplied from the read circuit 31.
11 (consisting of a logic "H" level) and identifying the input unit 22A having the data amount detection circuit 24A,
Based on the data amount detection signal S11, it is recognized that the entire TS packet has been written in the first memory 23A of the input unit 22A, and that the TS packet can be read from the first memory 23A. Detection signal S1
1 is converted into a numerical value to generate input section information representing the input section 22A corresponding thereto. In addition to this, the recognition circuit 32
The input unit information is supplied as an input unit information signal S15 to the memory 35, and a write control signal S16 for designating the address i (FIG. 3 (L)) is supplied, and the input unit information is written to the address i (FIG. 3). (K)). Note that the recognition circuit 32
After the input unit information is written in the memory 35, the address i in which the input unit information is written is increased by one address to generate an i-th address, and preparation is made for writing the input unit information.

While the recognition circuit 32 is writing the input unit information in the second memory 35, the input unit 22
The N first memory 23N is supplied with the transport stream D4N from the corresponding encoding device 7N, and writes all one TS packet included in the transport stream D4N at time t (c) (FIG. 3).
(F)). As a result, the data amount detection circuit 23N corresponding to the first memory 23N outputs the data amount detection signal S11 at the logic "L" level to the logic "H" at the time t (c).
Start up to the level (Fig. 3 (G)).

On the other hand, read circuit 31 supplies read signal S12 to data amount detection circuit 24B at time t (d) (FIG. 3 (I)), and identifies data amount detection circuit 24B that supplied read signal S12. Identification signal S1
3 is supplied to the recognition circuit 32. At this time, the first memory 2
No TS packet is written in 3B, and accordingly, the data amount detection circuit 24B outputs the supplied read signal S12.
Based on the data amount detection signal S at the logical "L" level
11 is supplied to the recognition circuit 32 (FIG. 3 (J)).

As a result, the recognizing circuit 32 reads the read circuit 3
1, the input unit 22B having the data amount detection circuit 24B that has output the data amount detection signal S11 (having a logical "L" level) is identified, and the data amount detection signal S11 is output. No TS packet is written in the first memory 23B of the input unit 22B based on the above, and it is recognized that the first memory 23B is not a target for reading the TS packet. Here, an input unit (not shown) between the input unit 22B and the input unit 22N.
Does not write the TS packets in the first memory, and therefore, the recognition circuit 32 recognizes that these are not the targets of reading the TS packets as in the case of the input unit 22B described above.

Read circuit 31 supplies read signal S12 to data amount detection circuit 24N at time t (e) (FIG. 3 (I)), and identifies data amount detection circuit 24N that supplied the read signal S12. Identification signal S1
3 is supplied to the recognition circuit 32. At this time, the data amount detection circuit 24N supplies a data amount detection signal S11 having a logic “H” level to the recognition circuit 32 based on the supplied read signal S12 (FIG. 3 (J)), and detects the data amount. The signal S11 falls to the logic “L” level (FIG. 3
(G)).

As a result, the recognition circuit 32 reads the read circuit 3
Based on the identification signal S13 supplied from No. 1, the input unit 22N having the data amount detection circuit 24N that has output the data amount detection signal S11 (having a logical "H" level) is identified, and the data amount detection signal S11 It is recognized that all the one TS packet has been written to the first memory 23N of the input unit 22N based on the data, and that the TS packet can be read from the first memory 23N. Input unit 2 corresponding to this
Input unit information representing 2N is generated.

In addition to this, the recognition circuit 32 supplies the input section information to the second memory 35 as the input section information signal S15, and also generates the address i (the second memory) generated after the input section information is previously written. The write control signal S16 is supplied to the address 35 to specify the address i at which the input unit information was previously written by incrementing the address by 1 (FIG. 3 (L)), and the input unit information is stored in the i address. Write (FIG. 3 (K)). Note that the recognition circuit 32 writes new input section information in the second memory 35 in the same manner as when writing the input section information first, and then increases the address i in which the input section information is written by one address. The address i is generated, and then preparations are made for writing the input section information.

In this manner, the readout circuit 31 sequentially repeats the data amount detection circuits 24A to 24A at a predetermined cycle.
4N to the first memory 23.
The writing status of TS packets of A to 23N is sequentially detected. Thus, the recognition circuit 32 can sequentially write new input unit information before the multiplexer 37 reads out all the input unit information written in the second memory 35.

Here, the multiplexer 37 designates the address j in which the input section information representing the input section 22A (having the first memory 23A in which the TS packet is first written) is written in the second memory 35 (see FIG. 2). FIG. 3 (N) supplies a read control signal S20, thereby controlling the reading of the second memory 35, and reading the input section information corresponding to the read control signal S20 as the input section information signal S15 (FIG. 3). (M)). Thus, the multiplexer 37 identifies the input section 22A in which the TS packet is written based on the read input section information, and starts reading the TS packet from the first memory 23A of the input section 22A at time t (f). (FIG. 3C). Note that the multiplexer 37 reads the input unit information from the second memory 35, generates an address j in which the address j from which the input unit information is read is increased by one, and reads the input unit information. Prepare.

Here, the first memory 23B of the input section 22B
Multiplexor 37 transmits the first memory 23A to T
While the S packet is being read out as the TS packet data D10, the transport stream D4B is supplied from the encoding device 7B, and the transport stream D4 is supplied.
All of the one TS packet included in 4B is time t (g).
(FIG. 3D). This makes the first
The data amount detection circuit 23B corresponding to the memory 23B of
The data amount detection signal S11 at the logical "L" level is raised to the logical "H" level at time t (g) (FIG. 3).
(E)).

The multiplexer 37 is connected to the input section 22A.
While reading the TS packet from the first memory 23A as the TS packet data D10, the address j generated after reading the input unit information into the second memory 35 first (the input unit information is input first from the second memory 35). A read control signal S20 is specified (FIG. 3 (N)) to specify the address j which is obtained by increasing the address j by one address when the information is read (FIG. 3 (N)), thereby inputting the input section information written at the address j. It is read out as a unit information signal S15.

Thus, the multiplexer 37 identifies the input section 22N in which the TS packet has been written based on the read input section information, and sends the TS packet from the first memory 23A to the TS section.
Time t at which reading of packet data D10 is completed
In (h), the first memory 23N of the input unit 22N
Starts reading of the TS packet from FIG.
(H)). The multiplexer 37 is connected to the second memory 3
5, after reading the input unit information from the second memory 35 in the same manner as when reading the input unit information first, the address j from which the input unit information is read is increased by one.
The address is generated, and preparations are made for reading out the input section information.

Thus, the multiplexing device 21 sequentially writes the TS packets included in the transport streams D4A to D4N supplied from the encoding devices 7A to 7N by sequentially repeating the above-described multiplexing operation. The transport streams D4A to D4N can be multiplexed by reading from the first memories 23A to 23N to the multiplexer 37 of the multiplexing unit 27 in the order of the first memories 23A to 23N. ing.

In the case of this embodiment, in the multiplexer 21, the first memory 2 of each of the input sections 22A to 22N is provided.
3A to 23N are, for example, at least the encoding devices 7A to 7N
Has a write capacity of a data amount capable of writing the same number of TS packets as the number of TS packets. Thus, when the multiplexer 37 of the multiplexer 27 sequentially reads out the TS packets from each of the first memories 23A to 23N as the TS packet data D10, the multiplexer 21 continues to the at least one first memory 23A to 23N. Even if a TS packet arrives and the first memories 23A to 23N are in a standby state for a time during which the same number of TS packets as the number of the first memories 23A to 23N are read out, the corresponding TS
Packets can be written reliably.

In the above configuration, the multiplexing device 21
, One T is stored in each of the first memories 23A to 23N.
The fact that all the S packets have been written is detected by the corresponding data amount detection circuits 24A to 24N, and the readout circuit 31 detects the data amount detection circuits 24A to 24N.
, A data amount detection signal S11 representing a detection result is read out at a predetermined cycle, and based on the read data amount detection signal S11, the recognition circuit 32 recognizes the order of the first memories 23A to 23N in which the TS packets are written. This order is sequentially written into the second memory 35 as input section information. Thereby, the first memory 2 for reading the TS packet is read.
The order of 3A to 23N can be determined. Also, by reading the input unit information from the second memory 35 in the order in which it was written by the multiplexer 37, the TS packets are read out in the order in which they were written to the first memories 23A to 23N based on the read input unit information. The multiplexing process can be performed as described above.

Therefore, in the multiplexing apparatus 21, the order of the first memories 23A to 23N in which the TS packets have been written is written in the second memory 35. By reading the TS packets from the first memories 23A to 23N, it is possible to prevent the TS packets that have arrived at the input unit earlier from being read out as in the conventional multiplexing device 8 without being read out. The TS packets can be reliably read from the first memories 23A to 23N in the order of the first memories 23A to 23N in which the TS packets have been written, and thus the first memories 23A to 23N can be read.
The order in which the TS packets are written in the 3N can be made equal to the order of the TS packets included in the transport stream D6 formed by multiplexing.

In the multiplexing device 21, the readout circuit 31 supplies the readout signal S12 to the data amount detection circuits 24A to 24N sequentially and repeatedly at a predetermined cycle shorter than the readout time of the TS packet data D10 by the multiplexer 37. Thus, while the multiplexer 37 reads the input unit information from the second memory 35 and reads the ST packets from the first memories 23A to 23N based on the input unit information, the recognition circuit 32 outputs the new input unit information. The input information can be sequentially written to the second memory 35, and thus all the input section information written to the second memory 35 is read out during the multiplexing process. Therefore, the first memories 23A to 23A by the multiplexer 37 are read.
It is possible to prevent the reading of the TS packets from N from being stopped, and to continuously and efficiently read the TS packets.

Further, in the multiplexing device 21, the data amount detection circuits 24A to 24N are set to the logic "H" level by writing all the TS packets to the corresponding first memories 23A to 23N. By causing the data amount detection signal S11 to fall to the logical "L" level every time the data is read out by the readout circuit 31, one TS packet written in the first memories 23A to 23N is sent to the multiplexer 37. The readout signal S12 is supplied from the readout circuit 31 to the data amount detection circuits 24A to 24N a plurality of times before the data is read out, and each time the data amount detection circuits 24A to 24N are read.
Can be prevented from being supplied to the recognition circuit 32 with the data amount detection signal S11 having the logic "H" level redundantly for one ST packet.

Further, in the multiplexing method using such a multiplexing device 21, it is detected that a TS packet has been written into the first memories 23A to 23N, and the first packet is read out based on the detection result. Memory 23A-2
By determining the order of 3N, time information indicating the arrival time is added to the arriving TS packet as in the multiplexing device considered conventionally, and the time is determined when the reading order of the TS packet is determined. The number of TS packets to be read can be easily determined without requiring complicated processing steps such as comparing and judging information. Thus, the TS packets are read from each of the first memories 23A to 23N in the reading order. Packets can be sequentially read out and easily multiplexed.

According to the above configuration, the plurality of first memories 23A to 23N for sequentially writing the TS packets included in the transport streams D4A to D4N supplied from the corresponding encoding devices 7A to 7N, respectively. A plurality of data amount detection circuits 2 for detecting that the TS packets have been written into the first memories 23A to 23N.
4A to 24N, a readout circuit 31 for sequentially reading out a data amount detection signal S11 representing a detection result from each of the data amount detection circuits 24A to 24N at a predetermined cycle, and a data amount detection circuit 2
The first memory 23 in which a TS packet is written based on the data amount detection signal S11 supplied from 4A to 24N.
A recognition circuit 32 for recognizing the order of A to 23N, a second memory 35 in which the recognition circuit 32 sequentially writes recognition results as input unit information, and input unit information sequentially written from the second memory 35 The first memories 23 </ b> A to 23 </ b> A read in order and correspond to the read input unit information.
A multiplexer 37 for performing multiplexing processing by sequentially reading TS packets from N is provided, so that the TS arriving at the input unit as in a conventional multiplexer is provided.
The first memory 23A in which the TS packet is written is prevented by preventing the packet from being read out and entering a standby state.
To the first memories 23A to 23N in the order of
, The order in which the TS packets are written into the first memories 23A to 23N is made equal to the order of the TS packets included in the transport stream D6 formed by the multiplexing process. Thus, it is possible to realize a multiplexing apparatus capable of correctly reproducing video data, audio data, and program information data corresponding to a TS packet in a receiving apparatus.

Each of the corresponding encoding devices 7A to 7A
7N transport streams D4A-
The TS packets included in D4N are stored in the first memories 23A to 23A.
23N, and then detects that the TS packets have been written in the corresponding first memories 23A to 23N, and determines the order of the first memories 23A to 23N in which the TS packets have been written based on the detection result. Recognition, the recognition result is sequentially written as input unit information in the second memory 35, and subsequently, the input unit information is sequentially read from the second memory 35 in the order in which the input unit information was written, and the read input unit information is stored in the read input unit information. First memory 23A to
The multiplexing process is performed by sequentially reading the TS packets from the 23N, so that the arrival time added to the TS packet is determined when the reading order of the TS packets is determined as in the multiplexing device considered conventionally. The order in which TS packets are read out can be easily determined without the need for complicated processing steps such as comparing and judging time information to be represented.
The TS packets can be sequentially read out from the first memories 23A to 23N in the same order and can be easily multiplexed, so that the receiving apparatus correctly reproduces the video data, audio data and program information data corresponding to the TS packets. Multiplexing method that can be realized.

In the above embodiment, a case has been described in which the present invention is applied to the multiplexing device 21 used in the transmitting device 20 of the digital broadcasting system. However, the present invention is not limited to this, and the present invention is not limited thereto. The present invention may be applied to various other transmitting apparatuses and transmitting / receiving apparatuses to which the system is applied, and to a multiplexing apparatus used for a recording apparatus and a recording / reproducing apparatus.

In the above-described embodiment, the first memories 23A to 23N are provided as the first storage means provided in correspondence with the respective channels and sequentially storing the supplied packet data. However, the present invention is not limited to this. If the packet data provided for each channel can be sequentially stored, the first storage means having various other configurations can be used. May be applied.

Further, in the above-described embodiment, the first storage units 23A to 23N are provided corresponding to the first storage units 23A to 23N, respectively.
As described above, the case where the data amount detection circuits 24A to 24N are applied as the detection means for detecting that one packet data is stored in the first storage means 23A is not limited to this. To 23N, and the first storage means 2 respectively corresponding to
As long as it is possible to detect that one packet data is stored in 3A to 23N, detection means having various other configurations may be applied.

Further, in the above-described embodiment, the determination means for determining the order of the first storage means 23A to 23N for reading out the stored packet data based on the detection results obtained from the detection means 24A to 24N, respectively. , The decision circuit 30 is applied, but the present invention is not limited to this, and each of the detection means 24A to 24A
4N for reading stored packet data based on the detection results respectively obtained from the 4N.
As long as the order of 23N can be determined, a determining means having various other configurations may be applied.

Further, in the above-described embodiment, the multiplexer 37 is applied as multiplexing processing means for sequentially reading out packet data from each first storage means based on the order determined by the determination means 30 and performing multiplexing processing. However, the present invention is not limited to this case, and packet data can be sequentially read from each first storage means and multiplexed based on the order determined by the determination means 30. Alternatively, multiplexing processing means having various other configurations may be applied.

Further, in the above-described embodiment, a case has been described in which the reading circuit 31 is applied as reading means for sequentially reading the detection results of the respective detecting means 24A to 24N at a predetermined cycle. However, the present invention is not limited to this. As long as the detection results of each of the detection units 24A to 24N can be sequentially read at a predetermined cycle, a reading unit having various other configurations may be applied.

Further, in the above-described embodiment, the order of the first storage means 23A to 23N in which the packet data is stored based on the detection results sequentially read from the respective detection means 24A to 24N by the read means 31. Although the recognition circuit 32 is applied as the recognition means for recognizing the detection result, the present invention is not limited to this, and the detection result sequentially read from the detection means 24A to 24N by the reading means 31 is described. If it is possible to recognize the order of the first storage means 23A to 23N in which the packet data is stored based on the above, recognition means having various other configurations may be applied.

Further, in the above-described embodiment, the case where the second memory 35 is applied as the second storage means for sequentially storing the recognition results obtained from the recognition means 32 has been described. The present invention is not limited to this, and a second storage unit having various other configurations may be applied as long as the recognition results obtained from the recognition unit 32 can be sequentially stored.

Further, in the above-described embodiment, the data amount detection signal S11 having the logic "H" level is digitized by the recognition circuit 32, and the input signals representing the input sections 22A to 22N corresponding to the data amount detection signal S11 are input. Although the description has been given of the case where the unit information is generated, the present invention is not limited to this, and the data amount detection signal S1 having a logical “H” level is
A first memory 23 for reading a TS packet based on
If A to 23N can be represented, the corresponding first memories 23A to 23N and channels CH1 to CH are determined based on the data amount detection signal S11 at the logical "H" level.
Information indicating other various circuits such as N may be generated.

(2) Second Embodiment FIG. 4 shows a digital broadcasting system 130. First, in the transmitting apparatus 106, each data output unit 107A
To 107N (eg, video data D1A to D1).
N and the audio data D2A to D2N and the program information data D3A to D3N)
A to 108N, the compression-encoded video data, audio data, and program information data obtained in this manner are sequentially transferred to the TS every predetermined block.
The packets are packetized to form TS packet data D4A to D4N, which are sequentially supplied to the multiplexer 109.

Here, each of the encoding devices 108A to 108N
Are the corresponding clock generation circuits 110A to 110A, respectively.
0N, the operation clocks CLK _1A to CLK _1N are supplied.
Executes processing such as compression encoding, and TS packets of the timing of the operation clock CLK _1A ~CLK _1N. The respective clock generation circuit 110A~110N each has supplied the corresponding PCR generator also operates clock CLK _1A to CLK _1N to 111a to 111n, each PCR generation circuit 111a to 111n are operating clock CLK _1A corresponding ~ Counting is performed sequentially in synchronization with CLK _1N , and the count value is supplied to the corresponding encoding devices 108A to 108N as count value data D5A to D5N, respectively.

Thus, each of the encoding devices 108A-108
N is a plurality of TS packet data D4A to D4, respectively.
When N is formed, the count value when these are formed is stored as PCR in predetermined TS packet data TS1 to TS3 to be stored in the PCR. In addition to this, each of the encoding devices 108A to 108N transmits the data between the TS packet data TS1 to TS3 (that is, the TS packet data T
(Between S1 and TS packet data TS2, or between TS packet data TS2 and TS packet data TS3)
Of the TS packet data D4A so that the time interval (count number) in which the PCR is stored coincides with the time interval at which these TS packet data TS1 to TS3 are supplied.
To D4N are supplied to the multiplexer 131, respectively.

Thus, the multiplexing apparatus 131 outputs the TS packet data D4A to D4N (the TS in which the PCR is stored) input from the encoding apparatuses 108A to 108N, respectively.
(Including packet data) to form a transport stream D7 and supply it to the transmitting circuit 112. The transmission circuit 112 converts the transport stream D7 into a transmission signal S1 of a predetermined format and transmits the transmission signal S1.

In this case, as shown in FIG.
31 is supplied with TS packet data D4A to D4N from the encoding devices 108A to 108N to the corresponding input units 132A to 132N, respectively. Each input unit 132
A to 132N have the same configuration, and the input unit 132A supplies the supplied TS packet data D4A to the TS packet identification circuit 134 of the detection unit 133 and also supplies the TS packet data D4A to the time stamp addition circuit 135.

The TS packet identification circuit 133 identifies the last one of the input TS packet data D4A, and indicates the last one (for example, the TS packet data D4).
A timing signal S10 (consisting of the number of data bits from the beginning to the end of A) is supplied to the time stamp adding circuit 135. Here, the multiplexing unit 140 of the multiplexing device 131 is provided with a time stamp generating circuit 141,
The time stamp generation circuit 141, clock generating circuit 110 a - 110 n (FIG. 1) is synchronized with the operation clock CLK _1A to CLK _1N that caused operating clock CLK _T
, And counts in synchronization with this. The count value is supplied to the time stamp adding circuit 135 as count value data D30.

As a result, the time stamp adding circuit 135
A adds a count value at the end of each sequentially arrived TS packet data D4A as a first time stamp (start time of the multiplexing process) based on the timing signal S10. That is, as shown in FIG. 6, the size of the TS packet data D4A is

(Equation 2) Where the size of the first time stamp TM1 is

(Equation 3) Assuming that the TS packet data D4A
Is added to the last time stamp TM1.

Thus, the time stamp adding circuit 1
35 sequentially supplies the TS packet data D31A to which the first time stamp is added to the memory 142A, and the memory 142 stores the inputted TS packet data D3.
1A are sequentially stored.

When the time-stamped TS packet data is stored in each of the memories 142A to 142N of each of the input units 132A to 132N, the read circuit 1
43 is each T stored in each of the memories 142A to 142N.
The time stamp of the S packet data is read by the time stamp read signal S11, and the storage order of the TS packet data stored in each of the memories 142A to 142N is determined based on the read time stamp.

Then, the read circuit 143 determines the memory 142A-142N according to the determination result based on the time stamp.
The TS packet data is read out in the order in which the packet data is stored, and supplied to the time stamp identification circuit 144, the PCR identification circuit 146 of the correction unit 145, and the PCR correction circuit 147, respectively.

As described above, the plurality of memories 142A to 142A
By reading the TS packet data in the order in which it is stored in the 2N, the delay time D of each TS packet data from the time when it is stored in each of the memories 142A to 142N to the time when the multiplexing processing is performed can be made constant.

That is, the number of channels input to the multiplexer 131 is n, and the respective channels are channel 1, channel 2, channel 3,... Channel n. The input rates of channels 1 to n are R1, R2, R3,..., Rn [bits / sec]. Memory of channel 1 to channel n (FIFO)
The data capacities buffered to 142A to 142N are V1, V2, V3,..., Vn [bits]. Also, the output rate at which each TS packet data is multiplexed and output from the multiplexing device 131 is R [bits / se
c].

Here, the delay time due to multiplexing (multiplexing) in each of the channels 1 to n will be described. Each T input to the multiplexer 131
The S packet data is transmitted to each of the encoding devices 108A to 108A-1 at the preceding stage.
08N, the sum of the input rates of each channel 1 to channel n (R1 + R2 + R3 +... + Rn [bits / se
c]) is subjected to a so-called statistical multiplexing process that is the same as the output rate R [bits / sec]. In this statistical multiplexing process, the input rate of each of the channels 1 to n fluctuates.

In this case, the sum of the input rates (R1 + R2
+ R3 + ... + Rn [bits / sec]) is the output rate R [bits /
sec]

(Equation 4) Becomes

Normally, since the output transmission capacity is predetermined, it can be assumed that the output rate R [bits / sec] is constant. Memory of each channel 1 to channel n (FIF
O) Assuming that the total amount of data buffered in 142A to 142N is V [bits], the following equation is obtained.

(Equation 5) Becomes

In this case, the input rate (R1 + R2 + R3
+... + Rn [bits / sec]) is the output rate R [bits / sec.
sec], the total sum V [bits] of the data capacity is always constant.

Here, the delay time for the first channel 1 is calculated. The input rate is R1 [bits / sec], the amount of buffered data is V1 [bits], and the delay time D1 in this case is expressed by the following equation.

(Equation 6) Becomes

When the TS packet data is read out from the memories 142A to 142N in the input order and multiplexed, the data capacity buffered to each of the channels 1 to n becomes the ratio of the rates, so that the bi-ringing is performed in the memory 142A of the channel 1. The data amount V1 [bits] is expressed by the following equation.

(Equation 7) Becomes

Therefore, by substituting equation (4) into equation (7), the following equation is obtained.

(Equation 8) Becomes Further, from the equations (6) and (8), the delay time D1 when multiplexing is performed in the input order is obtained by deleting V1 and calculating the following equation.

(Equation 9) Becomes

Here, the output rate R [bits / sec] and the memory (FIFO) 142A of each channel 1 to channel n
Since the sum V [bits] of the data volumes buffered to .about.142N is constant as described above, the delay time D1 in the channel 1 is constant regardless of the fluctuation of the input rate R1.

By the way, if multiplexing is attempted in the order of the amount of data buffered in each of the memories 142A to 142N, the amount of data buffered in each channel is constant in any of the channels. Therefore, the buffered data capacity V1 [bits] is divided into n equal parts, and the following equation is obtained.

(Equation 10) Becomes In this case, from the above equations (6) and (10),
The delay time D1 when multiplexing the buffered data amount in descending order is V1 [bits], and the following equation is used.

[Equation 11] Becomes Therefore, from equation (11), the sum V [bits] of the buffered data amount and the number n of the channels are constant, but if the input rate R1 [bits / sec] fluctuates, the delay time D1 is correspondingly changed. Also fluctuates. Therefore, when the input rate R1 changes as needed, as in the case of statistical multiplexing, the delay time D1 of the channel also changes accordingly.

Thus, in this embodiment, the TS packet data input to each channel is read out in the order of writing to the memories 142A to 142N and multiplexed, so that multiplexing processing is required in each of the channels 1 to n. The delay time can be made constant. This makes it possible to easily prevent overflow and underflow of the buffer memory on the demodulation side described later.

In FIG. 5, the read circuit 143
TS packet data D3 read from memory 142A
A timing signal S indicating the addition position of the first time stamp of 1A (indicating the number of data bits from the beginning of the TS packet data D31A to the beginning of the first time stamp)
15 is supplied to the time stamp identification circuit 144 and the time stamp removal circuit 150, and indicates the storage position of the flag indicating whether or not the PCR is stored in the TS packet data D31A (data bits from the head of the TS packet data D31A to the head of the flag). The timing signal S16 (which indicates the number of data bits from the beginning of the TS packet data D31A to the beginning of the PCR) indicating the storage location of the PCR of the TS packet data D31A is supplied to the PCR identification circuit 146. It is supplied to the correction circuit 147.

The time stamp identification circuit 144 generates the TS packet data D31A based on the timing signal S15.
, The first time stamp is extracted, and is extracted as the first time stamp data D.
As 35, it is supplied to the arithmetic circuit 151.

[0097] calculation circuit 151, from the time stamp generating circuit 141 always operates clock count value in synchronism with the CLK _T are inputted as the count value data D30, the count when a first time stamp data D35 arrives The value is fetched as a second time stamp (end time of the multiplexing process on the TS packet data D31A). In this way, the arithmetic circuit 151 performs the first time stamp (count value) and the second time stamp (count value) indicated by the first time stamp data D35.
From the above, the processing time t required for the TS packet data D31A to perform the multiplexing processing is expressed by the following equation.

(Equation 12) And supplies the calculation result (processing time t) to the PCR correction circuit 147 as processing time data D36. Thus, the detecting unit 133 outputs the TS packet data D4
The processing time required for the multiplexing processing after A arrives at the time stamp adding circuit 135 of the input unit 132A can be detected.

The PCR identification circuit 146 inputs the TS packet data D3 based on the timing signal S16.
1A is identified, and PCR is performed based on the identification result.
Identify the presence or absence of Thereby, the PCR identification circuit 146
When the PCR is stored in the TS packet data D31A, for example, the control signal S20 corresponding to the logic “H” level is supplied to the PCR correction circuit 147 so that the PCR correction circuit 147 performs the PCR correction processing operation. Is executed, and the PC data is stored in the TS packet data D31A.
When R is not stored, for example, the control signal S21 corresponding to the logic “L” level is supplied to the PCR correction circuit 147 so that the P
The CR correction processing operation is stopped.

As a result, the PCR correction circuit 147 sends the TS packet data D31A input from the memory 142A.
If the PCR is stored in the TS packet data, the correction processing operation of the PCR is executed, the PCR of the TS packet data D31A is extracted based on the timing signal S17, and the PCR (count value) and the processing time data D36 are indicated. A PCR corrected from the processing time t (count value) (hereinafter, referred to as a corrected PCR) is represented by the following equation.

(Equation 13) The modified PCR is obtained by the TS packet data D
31A is stored at a predetermined position where the PCR was stored,
The TS packet data D31A is supplied to the time stamp removing circuit 150. Also, this PCR correction circuit 147
Is the TS packet data D input from the memory 142.
If the PCR is not stored in 31A, the PC
The R correction processing operation is stopped, and the input TS packet data D31A is supplied to the time stamp removing circuit 150 as it is.

The time stamp removing circuit 150 removes the first time stamp from the input TS packet data D31A based on the timing signal S15, and thereby encodes the TS packet data D31A into the encoding device 1.
08A (FIG. 4) and returns to the same data format as the TS packet data D4A in FIG.
To supply. Thus, the correction unit 145 corrects the PCR of the TS packet data D31A in which the PCR is stored based on the processing time of the multiplexing process, and determines the time interval for supplying each of the TS packet data D31A in which the corrected PCR is stored. Time interval between PCR (count)
Has been made to match.

In the multiplexing device 131, the storage signal S11 is supplied from the memory 142 corresponding to each of the input units 135A to 135N to the read circuit 143, so that the read circuit 143 causes each TS in each of the memories 142A to 142N. Packet data D31A to 31N
Of the TS packet data D31A-
When the storage amount of D31N reaches a predetermined amount, each memory 142
(For example, first, the input unit 1
32A, the memory 142N of the input unit 132N, and then the memory of the input unit 132B).
12 is supplied. As a result, in the multiplexing device 131, the read circuit 143 sets the TS packet data D31A to D31.
By reading N one by one into the multiplexing unit 140 one by one, the respective TS packet data D31A to D31N can be multiplexed.

In addition to this, in the multiplexer 131,
Each TS packet data D31A-D storing PCR
Correction processing is sequentially performed on the 31N PCRs. Thus, in the multiplexing device 131, the TS packet data D4A to D4A which are sequentially input are input.
N is sequentially multiplexed, and the PCR of the TS packet data D4A to D4N in which the PCR is stored can be modified based on the processing time required for the multiplexing process.

Here, in practice, in the multiplexer 131,
As shown in FIG. 7, first, the TS packet data D60 to D62 are sequentially supplied to the input unit, and the leading positions of the PCRs 55 to 57 corresponding to the respective TS packet data D60 to D62 sequentially arrive at the time stamp adding circuit. The count values are respectively assigned to the first time stamp T
TS corresponding to these as M10 to TM12
It is added to the end of the packet data D60 to D62 (FIG. 7A).

On the other hand, in the multiplexing section 140, even when each of the TS packet data D60 to D62 supplied from the memory of the input section is supplied without waiting in the corresponding memory (that is, without causing a time delay due to the standby). , The respective TS packet data D60 to D60 in the multiplexing unit 140.
For 62, a fixed delay td due to the multiplexing process occurs.
Therefore, in such a case, each TS packet data D6
0 to D62, and second time stamps TM20 to T2 each of which is a count value when the multiplexing process of each of the TS packet data D60 to D62 is completed.
Based on M22 and the fixed delay td,

[Equation 14] The PCRs 55 to 57 are respectively calculated by the following equations.

(Equation 15) Is corrected based on the fixed delay td (see FIG. 7).
(B)).

In the multiplexing section 140, of the TS packet data D60 to D62 supplied from the memory of the input section, the TS packet data D61 enters a standby state in the memory, and a predetermined process is performed for the multiplexing of the TS packet data D61. Assume that time tmd is required. In such a case, the predetermined processing time tmd for the TS packet data D61 is set to the first time stamp TM11 added to the TS packet data D61 and the second time when the multiplexing process of the TS packet data D61 is completed. Based on the stamp TM23,

(Equation 16) The PCR56 is calculated by the following equation.

[Equation 17] Is corrected by the processing time tmd. Further, in this case, in each of the TS packet data D60 and D62, the PCRs 55 and 57 are corrected as described above (FIG. 7B) due to the occurrence of the fixed delay td (FIG. 7C).

On the other hand, receiving apparatus 115 receives transmission signal S 1 via ANT 2, and demodulates it in demodulator 234 to form transport stream D 21.
3 is restored. The transport stream D213 thus obtained is supplied to the decoding device 235, and one of the selected desired program data is decoded and output.

That is, the decoding device 235 inputs the input transport stream D 213 to the switch 236. The switch 236 controls the transport buffer 23 according to the PID value of the input TS packet data.
7, 238 or 239, and divides the transport stream D213 into image data, audio data or TS packet data in which PSI is recorded. Each of the divided TS packet data is stored in the transport buffer 237, 238 or 23.
9 is temporarily stored.

The transport buffer 237 temporarily stores the image data obtained by dividing the transport stream D 213, and then sends it to the main buffer 240. The transport buffer 238 temporarily stores the audio data obtained by dividing the transport stream D 213, and then sends the data to the main buffer 241.
Further, the transport buffer 239 temporarily stores system data obtained by dividing the transport stream D213, and then sends out the system data to the main buffer 242. The decoding device 235 temporarily stores the image data, audio data, or system data sent from the transport buffers 237, 238, and 239 in the main buffer 240, 241 or 242, respectively.
These data are read and decoded.

In the decoding process, the P is determined based on the PCR of each TS packet data corrected on the transmitting device 106 side.
An LL (Phase Locked Loop) circuit (not shown) is phase-locked, and each data (image data, audio data, etc.) is decoded by the generated operation clock. Accordingly, the decoding device 235 can decode the image data and the audio data at the timing of the operation clocks synchronized with the operation clocks CLK _{1A to} CLK _1N in the encoding devices 108A to 108N of the transmission device 106 (FIG. 5). it can.

FIG. 9 shows a change in the amount of data stored in the main buffer 240, 241 or 242 of the decoding device 235. The transmitting device 106 adds a DTS (Decoding Time Stamp) added to the TS packet data.
Data is read from the main buffer 240, 241, or 242 according to the decoding time indicated by (DTS1, DTS2, DTS3) and decoded.

In this case, the PCR added to the predetermined TS packet data designates the time at which the data is input to the decoding device 235 (that is, each main buffer 240, 241 or 242).
If there is a change in the difference, the amount of data stored in the main buffer 240 (or 241, 242) overflows or underflows as shown in FIG.

Variation in the difference between PCR and DTS is caused by the fact that the delay time in the multiplexing process of the transmitting device 106 varies in each channel. Therefore, as described above with reference to FIG. 5, the multiplexing device 131 of this embodiment reads out and multiplexes the TS packet data in the order in which the TS packet data has been written to each of the memories (FIFOs) 142A to 142N. By performing the processing, the delay time associated with the multiplexing processing in each channel is kept substantially constant.

As a result, as shown in FIG. 9 (B), by writing and reading TS packet data corresponding to a fixed delay time with respect to the main buffer 240 (or 241, 242), the main buffer 240 (or 241) is written.
(Or 241 and 242), the fluctuation of the data occupancy is remarkably reduced, and the occurrence of overflow or underflow can be prevented. FIG. 9A shows a change in the data occupancy when data not subjected to multiplexing processing is stored in the main buffer 240.

In the above configuration, the multiplexing device 131 of the transmitting device 106 adds a time stamp to each of the TS packet data D4A to D4N output from the decoding devices 108A to 108N, and then adds the time stamp to the TS packet data D4A to D4N. D4N is stored in memory (FIFO) 142A-
142N.

The read circuit 143 is connected to each memory (FIF
O) The storage order is determined from the time stamps of the TS packet data stored in the 142A to 142N, and the memories (FIFOs) 142A to 142 are determined based on the determination result.
N, out of all the TS packet data stored in N, in order from the TS packet stored at the earliest time.
Read this.

As described above, the memories (FIFO) 142A-
By reading the TS packet data in the order in which they are stored in the 142N, the delay time in the statistical multiplexing process is changed regardless of the input rate variation for each channel, as described above for the equations (4) to (9). Can be kept constant.

The TS packet data multiplexed in this manner is stored in the memory (FIFO) 142A-142N by using a time stamp added before being written to the memory (FIFO) 142A-142N.
The CR is corrected and transmitted to the receiving device 115 side.

In the receiving apparatus 115, the received demodulated TS packet data is input to each main buffer (multiplex buffer) 240, 241 and 242 of the decoding apparatus 235 with a fixed delay time for each channel.

Accordingly, in each main buffer (multiplex buffer) 240, 241 and 242, after the relevant TS packet data is written, each read time (by DTS) is used.
By reading these TS packet data, the occupancy of the buffer always keeps a certain range.

Thus, according to the above configuration, the transmitting apparatus 1
In the multiplexing device 131, the TS packet data is read out in the order of writing the TS packet data to each of the memories (FIFOs) 142A to 142N, so that the input data rate can be changed as required in the statistical multiplexing process. Even if it changes, each memory (FIFO) 14
The time interval at which the TS packet data read from 2A to 142N is transmitted can be kept constant. Thus, the main buffer 240,
241 and 242 can be prevented from overflowing or underflowing.

Incidentally, each memory (FIFO) 142A-
Since the time stamp added to each TS packet data for determining the order of writing to the 142N is shared for PCR correction, it is possible to prevent the configuration of the multiplexer 131 from becoming complicated.

In the above embodiment, the case where the first time stamp TM1 is added to the end of each of the TS packet data D4A to D4N in the multiplexer 131 (FIG. 6) has been described. Is not limited to this. For example, as shown in FIG. 10, a first time stamp TM3 is added to the head of TS packet data D4A to D4N.
0, or as shown in FIG. 11, the first time stamp TM is added in parallel to the TS packet data D4A to D4N.
For example, the first time stamp may be added to the TS packet data D4A to D4N in various other formats, such as by adding 31.

Here, as shown in FIG. 10, a first time stamp T is added to the head of TS packet data D4A to D4N.
When M30 is added, the first time stamp TM
30 can be easily identified, and thus the circuit configuration of the time stamp identification circuit 144 can be simplified. Further, as shown in FIG. 11, the TS packet data D4
When the first time stamp TM31 is added in parallel to A to D4N, the TS packet data D
Since the first time stamp TM31 can be added without changing the length in the time direction of 4A to D4N, a plurality of T
When the S packet data D4A to D4N are successively multiplexed, the TS packet data D4A to D4N
The first time stamp TM1 is added to the end of D4N, or the TS packet data D4A to
T that can perform multiplexing processing per unit time as compared with the case where the first time stamp TM30 is added to the head of D4N
The number of S packet data D4A to D4N can be increased, and the efficiency of the multiplexing process can be improved.

Further, in the above-described embodiment, each TS packet data D
31A to 31N, each T in which a PCR is stored.
Although the case has been described where the PCR of the S packet data D31A to D31N is modified based on the corresponding processing time, the present invention is not limited to this, and the multiplexing device 13
1 is supplied to all TS packet data D4A to D4.
N, the PCR may be stored, and the PCRs of all the TS packet data D4A to D4N may be modified based on the corresponding processing time, whereby each of the TS packet data D4A to D4N is respectively received by the receiving device 115. Can be correctly decoded.

Further, in the above-described embodiment, the case where the present invention is applied to the multiplexing device 131 of the digital broadcasting system 130 has been described. However, the present invention is not limited to this, and the present invention is not limited to this. The present invention may be applied to various transmission devices, transmission / reception devices, and multiplexing devices used in recording devices and recording / reproduction devices.

Further, in the above-described embodiment, at least packet data D4A to D4N to which time information has been added.
Although the detection unit 133 (FIG. 2) has been described as a detecting means for detecting the processing time required for the multiplexing processing of the present invention, the present invention is not limited to this, and the present invention is not limited to this. Of these, if it is possible to detect at least the processing time required for the multiplexing of the packet data D4A to D4N to which the time information has been added, detection means having various other configurations may be applied.

Further, in the above-described embodiment, the correction unit 145 (FIG. 2) is applied as correction means for correcting the time information of the corresponding packet data D4A to D4N based on the processing time detected by the detection means 133. However, the present invention is not limited to this. The present invention is not limited to this, and if the time information of the corresponding packet data D4A to D4N can be corrected based on the processing time detected by the detecting means 133, various other configurations are possible. Some modification means may be applied.

[0128]

As described above, according to the present invention, the first storage means provided in correspondence with each channel and sequentially storing the supplied packet data and the first storage means respectively correspond to the first storage means. Detecting means for detecting that one piece of packet data is stored in the corresponding first storage means; and a first means for reading out the stored packet data based on the detection results obtained from each of the detecting means. Determining means for determining the order of the storage means, and multiplexing means for sequentially reading and multiplexing the packet data from each of the first storage means based on the reading order determined by the determining means. This prevents packet data arriving at the input unit of the multiplexing device from being left in a standby state without being read out. The packet data is written 1
The packet data is reliably read from the first storage means in the order of the storage means, so that the packet data is written in the first storage means and included in the transport stream formed by the multiplexing process. The order of the packet data can be made equal, and thus a multiplexing device can be realized in which the receiving device can correctly reproduce predetermined data corresponding to the packet data.

Further, packet data is sequentially stored for each channel, and then it is detected that one packet data is stored for each channel. Based on the detection result, the order of reading the stored packet data is determined. Based on the determined reading order, the stored packet data is sequentially read and multiplexed, so that the packet data reading order is determined when the packet data reading order is determined as in a multiplexing device conventionally considered. The packet data reading order can be easily determined without the need for complicated processing steps such as comparing and judging the time information indicating the added arrival time, and the stored packet data can be read out sequentially in that order. Multiplexing processing, so that packet data can be Multiplexing method capable of correctly reproducing the predetermined data can be realized.

Further, by reading out and multiplexing the packet data stored in the storage means for each channel in the order of storage, the delay time associated with the multiplexing process can be kept constant for each packet data. . Therefore, the time interval of the packet data transmitted for each channel can be kept constant, and overflow or underflow in the buffer at the receiving side can be avoided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a transmission device used in a digital broadcasting system according to the present invention.

FIG. 2 is a block diagram showing a first embodiment of the multiplexing device of the present invention.

FIG. 3 is a timing chart for explaining a multiplexing process according to the first embodiment;

FIG. 4 is a block diagram showing a digital broadcasting system using a multiplexer according to a second embodiment.

FIG. 5 is a block diagram showing a multiplexer according to a second embodiment.

FIG. 6 is a schematic diagram showing TS packet data to which a time stamp is added.

FIG. 7 is a timing chart for explaining the modification of PCR.

FIG. 8 is a block diagram showing a configuration of a decoding device.

FIG. 9 is a characteristic curve diagram showing a change in data amount of a main buffer.

FIG. 10 is a schematic diagram showing TS packet data according to another embodiment.

FIG. 11 is a schematic diagram showing TS packet data according to another embodiment.

FIG. 12 is a schematic diagram illustrating a structure of a TS packet.

FIG. 13 is a block diagram showing a circuit configuration of a transmission device used in a digital broadcasting system.

FIG. 14 is a schematic diagram for explaining a multiplexing process in the multiplexing device.

FIG. 15 is a timing chart for describing a multiplexing process in the multiplexing device.

FIG. 16 is a schematic diagram supplied to explain a delay of a TS packet in the multiplexing process.

FIG. 17 is a schematic diagram supplied to explain a delay of a TS packet in a multiplexing process.

[Explanation of symbols]

1... TS packet, 5, 20, 106...
8, 21, 131 ... Multiplexer, 22A to 22N, 1
32A to 132N ... input unit, 23A to 23N ... first
24A to 24N... Data amount detection circuit, 27
... Multiplexing section, 30... Decision circuit, 31... Readout circuit, 32... Recognition circuit, 35.
... Mux, 115 ... Receiving device, 135A ...
Time stamp adding circuit, 142A to 142N memory, 147 PCR correction circuit, 235 decoding device,
240, 241, 242: Main buffer.

Claims (10)

[Claims] 1. A multiplexing apparatus for packetizing predetermined data of a plurality of systems supplied by a plurality of channels for each predetermined unit, and sequentially multiplexing and outputting each packet data thus obtained. And a first memory for sequentially storing the supplied packet data.
Storage means, respectively provided corresponding to each of the first storage means,
Detecting means for detecting that one piece of the packet data is stored in the corresponding first storage means; and reading the stored packet data based on the detection results obtained from the respective detecting means.
Determining means for determining the order of the storage means, and multiplexing processing means for sequentially reading and multiplexing the packet data from each of the first storage means based on the order determined by the determining means. A multiplexing device comprising: 2. The reading means according to claim 1, wherein said determining means sequentially reads said detection results for each of said detecting means at a predetermined period, and said reading means reads out said detecting results from said detecting means sequentially from said detecting means. A recognition means for recognizing an order of the first storage means in which the packet data is stored; and a second means for sequentially storing recognition results obtained from the recognition means.
2. The multiplexing method according to claim 1, wherein the order of said recognition results sequentially stored in said second storage means is the order of said first storage means for reading said packet data. Device. 3. The reading means reads out the detection result of each of the detecting means at a predetermined period shorter than a time when the multiplex processing means reads out one packet data from the first storage means. The multiplexing device according to claim 2, wherein Each detecting means detects that one packet data is stored in the corresponding first storing means each time the reading means reads out the detection result; 3. The multiplexing apparatus according to claim 2, wherein the storage means detects that one new packet data is stored. 5. A multiplexing method in which predetermined data of a plurality of systems supplied by a plurality of channels are packetized for each predetermined unit, and each packet data thus obtained is sequentially multiplexed and output. A first step of sequentially storing packet data, and a second step of detecting that one packet data is stored for each of the channels and determining an order of reading the stored packet data based on the detection result.
And a third step of sequentially reading and multiplexing the stored packet data based on the determined order. 6. In the second step, the detection result of detecting that one packet data is stored for each of the channels is sequentially read in a predetermined cycle, and based on the read detection result, 6. The multiplexing method according to claim 5, wherein the order in which the packet data is stored is recognized, and the recognition results are sequentially stored, so that the order of the sequentially stored recognition results is the order in which the packet data is read. Method. 7. The multiplexing method according to claim 6, wherein in the second step, the detection result is read out at a predetermined period shorter than a time for reading out one stored packet data. 8. In the second step, every time a detection result of detecting that one packet data is stored is read, it is detected that one new packet data is stored. Item 7. A multiplexing method according to Item 6. 9. Multiplexing means for packetizing predetermined data of a plurality of systems supplied by a plurality of channels for each predetermined unit, adding reference clock data to said packets, and sequentially multiplexing and outputting each of the packet data thus obtained. Storage device, provided in correspondence with each of the channels, for storing the packet data supplied thereto, and time information adding means for adding time information to the packet data stored in the storage device. Reading means for determining a reading order of the packet data to be read out from the storage means based on the time information of the packet data stored in the storage means; read out from the storage means in the determined reading order and multiplexing The time required for the multiplexing process of the processed packet data is A multiplexing apparatus comprising: detecting means for detecting based on time information; and correcting means for correcting the reference clock data of the packet data based on the processing time detected by the detecting means. 10. Multiplexing means for packetizing predetermined data of a plurality of systems supplied by a plurality of channels for each predetermined unit, adding reference clock data to the packet, and sequentially multiplexing and outputting each of the packet data thus obtained. In the conversion method, time information is added to the packet data stored in the storage means provided corresponding to each of the channels, and the storage means is provided based on the time information of the packet data stored in the storage means. Determining the reading order of the packet data read from the storage unit, detecting the time required for the multiplexing process of the packet data read from the storage unit and multiplexed based on the time information, The reference clock data of the packet data is calculated based on the detected processing time. A multiplexing method characterized by correcting.