JPH10126280A - Parallel process error correcting and decoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correct an error with a low-speed clock, without increasing the circuit scale by inputting a (p)-bit receive signal (p: integer larger than 2) in parallel, correcting the error of the reception signal by a syndrome-calculating circuit, an error position detecting circuit, etc., and outputting a (p)-bit decoding result in parallel. SOLUTION: An input terminal 10 inputs the (p)-bit reception signal (p: integer larger than 2) in parallel, and a delay circuit 11 delays the reception signal. The syndrome-calculating circuit 12 inputs the reception signal inputted from the input terminal 10 sequentially and outputs an element of a Galois expansion body GF(2<m> ). An error position coefficient calculating circuit 12 calculates the coefficient of an error position polynomial from the output of the syndrome- calculating circuit 12. An error position detecting circuit 14 detects an error position from the coefficient, outputted from the error position coefficient calculating circuit 13. An error position detecting circuit 15 corrects the error of the reception signal outputted from the delay circuit 11. An output terminal 16 outputs the (p)-bit decoding result in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an error correction decoding device, and more particularly to a parallel processing error correction decoding device for decoding a block code such as a BCH code or a Reed-Solomon code.

[0002]

2. Description of the Related Art Conventionally, as a decoding apparatus for decoding a block code such as a BCH code or a Reed-Solomon code of this type, for example,

[0003]

[Outside 4]

[0004] An error correction decoding apparatus for a BCH code using a symbol as a symbol is configured as shown in FIG. In FIG. 5, 1 is an input terminal for inputting serial data (received signal), 2 is a delay circuit for delaying the received signal by n clocks, 3 is a syndrome calculation circuit for calculating a syndrome, and 4 is a coefficient for calculating an error locator polynomial. An error position coefficient calculation circuit, 5 is an error position detection circuit for detecting an error position, 6 is an error position correction circuit for correcting an error, and 7 is an output terminal.

Here, in a circuit constituting a decoding device for sequentially processing input data, it is necessary to perform processing in units of bits. Therefore, the clock frequency of the circuit constituting the decoding device is the same as the speed of the input data. Must be configured. As an example, there is a problem that the clock frequency of the decoding device for the 80 Mbps BCH code must be set to 80 MHz, and it is difficult to implement the LSI depending on the process of configuring the LSI. Therefore, by processing these in parallel every 8 bits, the clock frequency of the decoding apparatus can be reduced to 1/8 of 10 MHz (if any,
If a process that operates even at 80 MHz is used, the speed can be increased eight times by parallel processing.)

Heretofore, several high-speed error correction decoding devices using parallel processing have been proposed. For example, 1991 IEICE Spring National Convention, A-283 "High-speed BCH-LSI
In "Development of", the syndrome of the received word and the syndrome of the code that divides the received word into 8 bits and generates a 1-bit error in each bit in a pseudo manner are calculated,
When the number of error bits is smaller by one bit than the number of error bits of, it is determined that an error has occurred at the position where the error has been artificially added. Since this algorithm requires a pseudo syndrome generation circuit, there is a problem that the processing is complicated and the circuit scale becomes large. Furthermore, the IEICE Technical Report CS89-54, "Parallel Decoding of Algebraic Error Correcting Codes", has a problem that the circuit scale becomes large because it has a decoder with the number of bits that can be decoded in parallel at a time. There is.

In the "error correction decoding apparatus" disclosed in Japanese Patent Application Laid-Open No. 6-276106, p (p is an integer of 2 or more) input terminals are provided and input signals are processed in parallel.
The syndrome is calculated by obtaining partial syndromes and adding them all at the end. This requires p input / output terminals and an adder, which causes a problem that the circuit scale becomes large.

[0008]

As described above, each of the error correction decoding devices having such a configuration has a problem that the scale of the circuit configuration becomes large.

An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a parallel processing error correction decoding device which realizes error correction with a low-speed clock without increasing the circuit scale. .

[0010]

In order to achieve this object, a parallel processing error correction decoding apparatus according to the present invention comprises an input terminal for inputting a p-bit received signal in parallel, and a delay circuit for delaying the received signal. And, sequentially input the reception signal input from the input terminal,

[0011]

[Outside 5]

A syndrome calculation circuit for outputting an element of
An error location coefficient calculation circuit that calculates the coefficients of the error location polynomial from the output of the syndrome calculation circuit; an error location detection circuit that detects the error location from the coefficients output from the error location coefficient calculation circuit; and a reception output from the delay circuit An error position correcting circuit for correcting a signal error and an output terminal for outputting a p-bit decoding result in parallel are provided.

According to the above configuration, the operating frequency of the circuit can be reduced to about 1 / p.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a parallel processing error correction decoding device according to an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes an input terminal for inputting parallel data, 11 denotes a delay circuit, 12 denotes a syndrome calculation circuit, 13 denotes an error position coefficient calculation circuit, 14 denotes an error position detection circuit, 15 denotes an error position correction circuit, and 16 denotes a parallel position. Output terminal for outputting data.

For example, if the generator polynomial is

[0016]

Equation 3] ^{G (x) = X 10 +} X 9 + X 8 + X 6 + X 5 + X 3 + X 0 = (X 5 + X 2 +1) (X 5 + X 4 + X 3 + X 2 +1) at given GF (2 ⁵⁾ As a decoder for the above error-correcting BCH (31,21) code, a 5-bit parallel input and p = 5
The operation will be described below. Note that the operation shown here is an operation of mod2, and all the operations shown below are mod2.
Is performed by the following calculation. Also, if the 31-bit input signal is |
R ₀ , R ₁ , R ₂ ,..., R ₂₈ , R ₂₉ , R ₃₀ |

In FIG. 1, received signals (R ₀ , 0, 0, 0, 0) (R ₅ , R ₄ , R ₃ , R ₂ , R ₁ ) (R ₁₀ , R ₉ , _{R 8, R 7, R 6} ) · · · (R 30, R 29, R 28, R 27, R 26) are sequentially inputted. Here, each received signal is an element of GF (2 ⁵ ), and since one symbol is represented by 5 bits, it is necessary to add 0 first.

The 5-bit received signal input from the input terminal 10 is supplied to the delay circuit 11 and also to the syndrome calculation circuit 12, respectively.

In the delay circuit 11, the input signals | R ₀ , R ₁ , R
₂ ,..., R ₂₈ , R ₂₉ , R ₃₀ |

The syndrome calculation circuit 12 calculates syndromes S1, S2 and S3 from the input received signal. FIG. 2 is a circuit diagram showing an example of a syndrome calculation circuit according to the present embodiment. Reference numeral 20 denotes an input terminal, reference numerals 21 and 21 'denote a repetitive product-sum operation circuit, and reference numerals 22 and 22' have a delay function. The circuit is a 5-bit D flip-flop, 23 is an output terminal of the syndrome S1, 24 is a square circuit, 25 is an output terminal of the syndrome S2, 26 is a cubic circuit,
27 is an output terminal of the syndrome S3.

The syndrome S1 is the remainder of the division operation circuit of X ⁵ + X ² +1. As shown in Table 1, in the case of a serial input, the operation result is obtained from 1 to 5 every clock. In the case of a 5-bit parallel input, the calculation result can be obtained within one clock by using the calculation formula at the fifth clock.

[0022]

[Table 1]

Here, the calculation formula is shown.

[0024]

## EQU4 ## S1

[0] = x

[0] + x [3] + a4 S1 [1] = x [1] + x [4] + a3 S1 [2] = x

[0] + x [2] + x [3] + a2 S1 [3] = x [1] + x [3] + x [4] + a1 S1 [4] = x [2] + x [4] + a0 x is the previous one The value of S1 corresponds to the output Q of the D flip-flop 22, and the initial value is 0. a0 to a4 indicate 5-bit input data.

For the syndrome S2 ((S1) ² ),
This is a syndrome obtained by substituting α ² for α of the syndrome S1. Here, a virtual root α having a generator polynomial
Assuming that α ⁵ + α ² + 1 = 0 is satisfied, mo
α ⁵ = α ² +1 next S2 from operations d2 are determined as follows.

[0026]

## EQU5 ## S1

[0] Substituting α ² for α of α ⁰ = 1 S1 [1] Substituting α ² for α of α ¹ = α ² S1 [2] Substituting α ² for α of α ² = α ⁴ S1 [3] Substituting α ² for α ³ = α ⁶ = α · α ⁵ = α (α ² +1) = α ³ + α S1 [4] Substituting α ² for α ⁴ = α ⁸ = α ³ · α ⁵ = Α ³ (α ² +1) = α ⁵ + α ³ = α ³ + α ² +1

[0027]

S2 = S1

[0] alpha ⁰ + S1 (1) alpha ² + S1 (2) alpha ⁴ + S1 (3) alpha ⁶ + S1 [4] alpha ⁸ = S1

[0] + S1 [1] alpha ² + S1 (2) alpha ⁴ + S1 (3) (α ³ + α) + S1 (4) ^{(α 3 + α 2 +1)} = S1

[0] + S1 [1] alpha ² + S1 (2) alpha ⁴ + S1 [3] alpha ³ + S1 [3] alpha + S1 [4] alpha ³ + S1 (4) alpha ² + S1 [4] = (S1

[0] + S1 [4]) + S1 [3] alpha + (made by S1 [1] + S1 [4]) alpha ² + (S1 (3) + S1 (4)) alpha ³ + S1 (2) alpha ^4. That is, if S1 obtained by substituting α ² is S2,

[0028]

## EQU7 ## S2

[0] = S1

[0] + S1 [4] S2 [1] = S1 [3] S2 [2] = S1 [1] + S1 [4] S2 [3] = S1 [3] + S1 [4] S2 [4] = S1 [2 ].

For syndrome S3, X ⁵ + X ⁴ +
A syndrome obtained by substituting α ³ for α of the syndrome S1 ′ which is the remainder of the division operation circuit of X ³ + X ² +1. S1 ′ can be obtained as shown in Table 2 in the same manner as S1.

[0030]

[Table 2]

Here, the calculation formula is shown.

[0032]

## EQU8 ## S1 '

[0] = x

[0] + x [3] + a4 S1 '[1] = x [1] + x [2] + a3 S1' [2] = x

[0] + x [1] + x [2] + x
[3] + x [4] + a2 S1 '[3] = x

[0] + x [2] + x [3] + a1 S1 '[4] = x

[0] + x [3] + a0 x is the value of the previous S1 'and is the D flip-flop 22'
And the initial value is 0. a0 to a4 indicate 5-bit input data.

The syndrome S3 is a syndrome obtained by substituting α ³ for α of the syndrome S1 ′, and the result obtained in the same manner as S2 is shown below.

[0034]

(Equation 9) S3

[0] = S1 '

[0] S3 [1] = S1 '[2] + S1' [3] + S1 '[4] S3 [2] = S1' [4] S3 [3] = S1 '[1] + S1' [2] + S1 ' [3] + S1 '[4] S3 [4] = S1' [3] Here, the syndromes S1, S2 and S3 are elements of GF (2 ⁵ ).

The error position coefficient calculation circuit 13 receives the outputs S1, S2, and S3 of the syndrome calculation circuit 12 and generates an error position detection polynomial.

[0036]

Equation 10] σ (x) = S1 + S2α + ((S1) 3 + S3) α 2 coefficient (S1) ³ + S3 is calculated. If there is no error S
1 = S2 = S3 = 0, and in the case of a 1-bit error,

[0037]

(S1) ³ = S3 ((S1) ³ + S3 = 0, (S1) ³
= S3 ≠ 0), and in the case of a 2-bit error, (S1) ³ ≠ S3.

FIG. 3 is a circuit diagram showing a configuration as an example of an error position detection circuit according to the present embodiment.
32 is an input terminal, 33 and 33 'are product-sum operation circuits, 34 is an α multiplication circuit, 35 is an α ² multiplication circuit, 36 is an addition circuit, and 37 is an output terminal.

In the error position detection circuit 14, the coefficient (S1) ³ + S3 output from the error position coefficient calculation circuit 13 is input to an input terminal 32.
To the syndrome S of the output of the syndrome calculation circuit 12.
1 and S2 are set to be input to the input terminals 30 and 31,

[0040]

The calculation of σ (x) = S1 + S2α + ((S1) ³ + S3) α ² is parallel-processed, and an error is output as 0.

FIG. 4 is a circuit diagram showing a configuration as an example of the error position correction circuit according to the present embodiment. Reference numeral 40 denotes an input terminal for inputting the output of the error position detection circuit 14, and reference numeral 41 denotes the output of the delay circuit 11. , An NOT (NOT) circuit, 43 an exclusive OR (EXOR) circuit provided for each bit, and 44 an output terminal.

The error position correction circuit 15 corrects the error by taking the exclusive OR of the output of the delay circuit 11 and the output of the error position detection circuit 14, and outputs the result.

In the error correction decoding processing of this configuration, the code length is
Since it is 31 bits and cannot be divided by 5, the clock can only be set to 1/4 clock (four times the processing speed) as compared with the conventional decoding device. However, if the code length n is a number divisible by p, the clock speed can be reduced to 1 / p.

The above description is an example of the present invention, and the present invention is not limited to this.

[0045]

As described above, according to the present invention,
Since the syndrome calculation circuit and error position detection circuit are processed in parallel, the circuit scale does not increase so much.
There is an advantageous effect that the operating frequency of the circuit can be reduced to about 1 / p.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a parallel processing error correction decoding device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration that is an example of a syndrome calculation circuit according to the present embodiment;

FIG. 3 is a circuit diagram illustrating a configuration that is an example of an error position detection circuit according to the present embodiment;

FIG. 4 is a circuit diagram illustrating a configuration that is an example of an error position correction circuit according to the present embodiment;

FIG. 5 is a block diagram illustrating a configuration of a conventional error correction decoding device.

[Explanation of symbols]

1, 10, 20, 30, 31, 32, 40, 41 ... input terminals, 2, 11
... delay circuit, 3,12 ... syndrome calculation circuit, 4,
13 ... Error position coefficient calculation circuit, 5,14 ... Error position detection circuit, 6,15 ... Error position correction circuit, 7,16,23,25,
27, 37, 44 ... output terminal, 21, 21 ', 33, 33' ... product-sum operation circuit, 22, 22 '... D flip-flop, 24 ... square circuit, 26 ... cube circuit, 34 ... alpha multiplier circuit , 35… α ²
Multiplication circuit, 36 addition circuit, 42 negation (NOT) circuit,
43 ... Exclusive OR (EXOR) circuit.

Claims (2)

[Claims] (1) An (n, k) error correction decoding device that uses an element of (m is a positive integer) as a symbol, comprising: an input terminal for inputting a p-bit (p is an integer of 2 or more) reception signal in parallel; A delay circuit for delaying
Receiving signals sequentially input from the input terminals, , An error position coefficient calculation circuit for calculating a coefficient of an error locator polynomial from the output of the syndrome calculation circuit, and an error for detecting an error position from the coefficient output from the error position coefficient calculation circuit. Parallel processing error correction decoding comprising: a position detection circuit; an error position correction circuit for correcting an error of a received signal output from the delay circuit; and an output terminal for outputting a p-bit decoding result in parallel. apparatus. 2. The input terminal receives a received signal as The received signal | R ₀ , R ₁ ,...
R _n−2 , R _n−1 | P ₀ = (R _p−1 ,..., R ₁ , R ₀ ) P ₁ = (R _2p−1 ,..., R _{p + 1, R p) ·} · · P m = (R n-1, ........., sequentially inputs the R _{mp + 1,} R _mp) in parallel by p bits, the syndrome calculation circuit from the input terminal The product-sum operation is sequentially performed on the input received signals. 2. The parallel processing error correction decoding device according to claim 1, wherein an element of?