JPH1012527A - Semiconductor chip and reticle for semiconductor manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable understanding of the position in a chip from designed coordinate values at an uppermost layer part on a chip material area or a layer detectable at observation by placing a pattern on specified region of the marginal area of the chip in the horizontal and vertical directions. The pattern includes coded positions on each coordinate axis of the designed coordinate system. SOLUTION: A guard ring 8, a region formed at the marginal area of a semiconductor chip 1, is used as a region on which a pattern is formed. The pattern has positions coded on coordinate axes of a designed coordinate system, so that the positions in the chip are known from designed coordinate values. The coordinate system is shown by axes X and Y, defined by the design coordinate origin 3 and scribe center. A coded example using the ring 8 is shown, where section U is a unit of the coded pattern, section D is a delimiter indicating the delimitation of the pattern unit and section B is a bit pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip and a reticle for manufacturing a semiconductor, and more particularly to a semiconductor chip whose design coordinate position can be easily specified by a pattern provided on the semiconductor chip and a reticle for manufacturing the semiconductor chip.

[0002]

2. Description of the Related Art Conventionally, the position of a final functional defect of a semiconductor chip detected by a fail bit inspection is designated by CAD data, and when the defect cause is visually checked to observe and analyze the defect, it is difficult to observe the defect. In order to load the target semiconductor chip or the semiconductor wafer on which the semiconductor chip is built into a stage equipped with a microscope or the like such as a review station, and to locate at a location specified by the CAD data, An alignment marker used for other uses such as a stepper has been used.

[0003]

However, an alignment marker used for another purpose such as a stepper does not exactly coincide with a virtually existing design coordinate system based on a scribe center. Deviations of tens of micrometers occur when positioning with markers.
Therefore, when observing a defect indicated by design coordinate values using a review station or the like described in the related art,
Even if the stage is moved to the designated coordinate value, the stage is located at a location several to ten cells away from the target location, and it takes a lot of man-hours to visually search the surroundings thereafter. For this reason, it is necessary to reduce the man-hour for the observation by devising the actual chip so as to correspond to the design coordinate system.

[0004]

The object of the present invention is to use a peripheral region of a chip formed on a semiconductor wafer to form a chip on the uppermost layer during visual observation or a layer detectable during observation. By providing a pattern in which the position on each coordinate axis of the design coordinate system is coded in a specific area in the horizontal and vertical directions on the outer periphery of the chip so that the position in the area can be identified by the design coordinate value, the pattern can be used for computer observation. This is achieved by reading out the position information on each coordinate axis from the pattern read and encoded by decoding and positioning the chip.

[0005]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an enlarged view of one of the semiconductor chips formed on a semiconductor wafer. A rectangular area around the diagonal line indicated by 1 is one semiconductor chip, and a diagonal area near the perimeter 8 is a semiconductor chip formed on a semiconductor wafer adjacent to one semiconductor chip. Show. The dashed line indicated by 2 is called a scribe center, and is a line that is used as a guide when the semiconductor chip 1 and surrounding chips are diced to be separated and finally cut into individual semiconductor chips. In FIG. 1, two vertically running scribe centers and two horizontally running scribe centers are indicated by alternate long and short dash lines. The position in the semiconductor chip 1 shown at the center is the origin at the intersection of the scribe centers shown at 3,
The range is a rectangular area surrounded by points 3, 4, 5, and 6, which is represented by an XY coordinate system defined by X and Y coordinates shown in FIG. The origin indicated by 3 is called the design origin. For example, the design origin of the semiconductor chip adjacent above the semiconductor chip 1 is 4, and the same coordinate system and region are recursively defined. Depending on the design data, the design origin is not 3,
It could be 4, 5 or 6. Also, as shown in FIG. 2, there are eight possible ways to define the XY coordinate system, including the method shown in FIG. Hereinafter, description will be made using the design origin position and the design coordinate system defined by the XY coordinate system shown in FIG.

Design data such as all wiring patterns and circuit positions in a semiconductor chip is described by XY coordinate values having the origin at the design origin 3 shown in FIG. FIG. 3 is an enlarged view of the semiconductor chip 1 shown in FIG. 7 is a rectangular area 3,
A region sandwiched between the semiconductor chips 1 and 4, 5, and 6 is called a scribe region. Reference numeral 8 denotes a region provided on the outer peripheral portion of the semiconductor chip 1 and is called a guard ring portion. The guard ring portion is provided for the purpose of preventing water or sodium from entering the chip from the side, and is formed of a material used in each step such as aluminum or silicon oxide having a width of about several tens of micrometers. . Reference numeral 10 denotes a chip body in which a wiring circuit pattern that actually functions is formed. Reference numeral 9 denotes an area between the guard ring portion 8 and the chip 10, usually 100 to 20.
It is a blank area of 0 micrometers.

A scribe area 7, a guard ring section 8, and a blank area 9 are used as an area for forming a pattern in which the position on each coordinate axis of the design coordinate system is formed so that the position in the chip 10 can be identified by the design coordinate value. It is possible.

First, a case where the guard ring portion 8 is used will be described as a first embodiment. FIG. 4 is an enlarged view of the lower left corner of the semiconductor chip shown in FIG. The design coordinate system is represented by an X axis and a Y axis defined by a design coordinate origin 3 and a scribe center. Reference numeral 8 denotes a guard ring portion, and reference numeral 10 denotes a chip. A pattern on a rectangular wave is cut on the outer periphery of the guard ring portion 8 shown in FIG. A coordinate value on the X axis or a coordinate value on the Y axis is encoded using the cut position of the rectangular wave in the directions corresponding to the X axis and the Y axis, the size of the rectangular wave, and the distance between the rectangular waves. FIG. 5 shows a first specific example of the encoding using the guard ring unit. Section U represents one unit of the encoded pattern. Section D is a delimiter indicating a break between units of the pattern. Section B is a bit pattern.
If a rectangular cut pattern as shown in the drawing exists in a part of the section B, the binary code is set to 1; In FIG. 5, the cut width of the rectangle is set to one half of one side of the bit area section B, but this width may be an arbitrary fixed distance. Delimiter and bit pattern are each pattern width S
1 and S2. In FIG. 5, S1: S2 = 2:
Although represented as 1, this ratio is arbitrary as long as it is the same between the pattern units. In FIG. 5, the code coded by the pattern unit is read as follows. First, the delimiter having the pattern width S1 is detected, and the subsequent bit pattern is read. In FIG. 5, the data is written with a 9-bit width, but this bit width may be changed as needed. The bit pattern in FIG.
0, which represents 370 in decimal. Since the 9-bit pattern can represent 0 to 511, considering the X-direction as shown in FIG. 5, the X-direction size XS of the chip 10 shown in FIG.
If the start position of the pattern unit is defined in advance as Xstart as shown in FIG. 4, the start position Xn of the pattern unit shown in FIG. 5 is Xn = Xstart + Xunit × 370 (101110
010: binary expression). Similarly, if a pattern in which the coordinate position on the Y-axis coordinate is encoded is formed in the guard ring unit 8 with respect to the Y axis, X, The position of Y is determined, and the position indicated by arbitrary design coordinates in the chip 10 can be determined. As mentioned earlier, X
When it is desired to define the position of n, the distance of the pattern unit section U may be shortened and the bit width may be increased. The same applies to the Y direction.

FIG. 6 shows a second embodiment using a guard ring. Section U represents one unit of the encoded pattern. The section D is a delimiter indicating a break between the patterns P1, P2, and P3 encoded by the length. The pattern lengths indicated by P1, P2, and P3 are quantized in ten stages. That is, assuming that the minimum unit distance is d, the pattern length Pn has ten steps of Pn = d × n (n = 1, 2,..., 10). Therefore, the number of combinations of P1, P2, and P3, which is the third power of 10, that is, 1000 combinations is possible. Therefore, the position of the delimiter can be specified by measuring the first three pattern lengths P1, P2, and P3 from one delimiter. However,
In order to realize this, the combination of the following three pattern lengths starting from an arbitrary delimiter is unique, that is, the combination is in the guard ring 8 corresponding to one axis direction of X or Y in one chip, and is continuous. The condition is that there is no overlap in the combination of the three pattern lengths. This is hereinafter referred to as a non-overlapping condition. In determining the pattern length, it is necessary to consider the following. First, the pattern length must be determined cyclically.
That is, if P1, P2, and P3 are determined, the first two of the next pattern are P2 and P3, and the next pattern P4 following P2 and P3 is determined while satisfying the above-mentioned non-overlapping condition under the conditions. There is a need to. Second, the distance U including the three pattern lengths needs to be averaged as a whole. This is where (P1, P2, P3) = (d, d, d),
Another reason is that if (p1, p2, p3) = (10d, 10d, 10d), the distribution of the delimiters for determining the coordinate position greatly varies, which causes practical inconvenience. The combination of P1, P2, and P3 determined under the above conditions complicates the correspondence with the actual coordinate values. Therefore, as shown in FIG.
Table data is stored in advance so that the coordinate value X can be obtained using the combination of 1, P2, and P3 as an index, and is referred to at the time of use. Similarly, if a pattern in which the coordinate position on the Y-axis coordinate is encoded is formed in the guard ring unit 8 with respect to the Y axis, X, The position of Y is determined, and the position indicated by arbitrary design coordinates in the chip 10 can be determined. If it is desired to define the position of Xn more finely as described above, the pattern unit section U
May be shortened and the bit width may be increased. The same applies to the Y direction. In the above description, the pattern combination is 3 and the pattern length is 10 steps. However, the number of pattern combinations and the number of steps of the pattern length may be different numerical values.

FIG. 8 shows a third embodiment using a guard ring. This method is a modification of the first embodiment using the guard ring unit shown in FIG. 5, and a section U represents one unit of an encoded pattern. Section D is a delimiter indicating a break between units of the pattern. Section B
Is a bit pattern. If a rectangular cut pattern as shown in the drawing exists in a part of the section B, the binary code is set to 1; In FIG. 8, the cut width of the rectangle is one half of the bit area section B, but this width may be an arbitrary fixed distance. The delimiter and the bit pattern are identified based on the difference between the pattern widths S1 and S2. Although FIG. 8 shows S1: S2 = 2: 1, this ratio is arbitrary as long as it is the same between the pattern units. In the first embodiment using the guard ring, one bit has a depth d. d is quantized in six stages. That is, if the minimum unit distance is w, the pattern length Pn
Has six lengths of d = w × n (n = 0, 1, 2,..., 5). As a result, a hexadecimal number can be represented by one bit, and the value of 6 to the fourth power, that is, a value from 0 to 1295, is about half as long as that of the first embodiment using the guard ring unit. Can be expressed by
The correspondence with the coordinate values is the same as in the first embodiment. The three embodiments using the guard ring unit have been described above. As another encoding method, NRZ-I, which is used in a magnetic recording device or the like, is used.
A bit pattern coding method such as MFM and MDM is also applicable. The pattern applied to the guard ring portion may be outside or inside the guard ring. Further, although the pattern to be formed has been described as a rectangle, other shapes such as a sawtooth shape, a triangle, and a semicircle may be used as long as the pattern can be detected.

Next, a case where the scribe area 7 is used as a second embodiment will be described. FIG. 9 is an enlarged view of the lower left corner of the semiconductor chip shown in FIG. The design coordinate system is represented by an X axis and a Y axis defined by a design coordinate origin 3 and a scribe center. Reference numeral 8 denotes a guard ring portion, and reference numeral 10 denotes a chip. A hatched rectangular area 11 shown in FIG. 9 is a pattern formed for the same purpose as the pattern formed on the edge of the guard ring portion in the above-described embodiment using the guard ring portion. A coordinate value on the X axis or a coordinate value on the Y axis is encoded using the position of the rectangular pattern in the directions corresponding to the X axis and the Y axis, the size of the rectangular pattern, and the distance between the rectangular patterns.

FIG. 10 shows a first specific example of encoding using a scribe area. Section U represents one unit of the encoded pattern. Section D is a delimiter indicating a break between units of the pattern. Section B is a bit pattern. If a rectangular cut pattern as shown in the figure exists in a part of the section B, the binary code is set to 1;
And In FIG. 10, the width of the rectangular pattern is set to one half of the bit area section B, but the width may be an arbitrary fixed distance. The delimiter and the bit pattern are identified based on the difference between the pattern widths S1 and S2. In FIG.
1: S2 = 2: 1, but this ratio is arbitrary as long as it is the same between each pattern unit. Now, in FIG. 10, the code coded by the pattern unit is read as follows. First, the delimiter having the pattern width S1 is detected, and the subsequent bit pattern is read.
In FIG. 10, the data is written in a 9-bit width, but this bit width may be changed as needed. The bit pattern in FIG. 10 is 101110010, which represents 370 in decimal.
Since a 9-bit pattern can represent 0 to 511, considering the X direction as shown in FIG. 10, an appropriate distance obtained by dividing the X direction size XS of the chip 10 shown in FIG. Then, the start position of the pattern unit is set in advance to Xstart as shown in FIG.
In this case, the start position Xn of the pattern unit shown in FIG. 10 is Xn = Xstart + Xunit × 370 (101110
010: binary expression). Similarly, if a pattern in which the coordinate position on the Y-axis coordinate is encoded is formed in the scribe area 7 with respect to the Y axis, the X and Y coded patterns in the X direction and the Y direction of the scribe area 7 are formed. The position is determined, and the position indicated by arbitrary design coordinates in the chip 10 can be determined. As mentioned earlier, X
When it is desired to define the position of n, the distance of the pattern unit section U may be shortened and the bit width may be increased. The same applies to the Y direction.

FIG. 11 shows a second embodiment using a scribe area. Section U represents one unit of the encoded pattern. The section D is a delimiter indicating a break between the patterns P1, P2, and P3 encoded by the length. The pattern lengths indicated by P1, P2, and P3 are quantized in ten stages. That is, assuming that the minimum unit distance is d, the pattern length Pn has ten steps of Pn = d × n (n = 1, 2,..., 10). Therefore, the number of combinations of P1, P2, and P3, which is the third power of 10, that is, 1000 combinations is possible. Therefore, the position of the delimiter can be specified by measuring the first three pattern lengths P1, P2, and P3 from one delimiter. However,
In order to realize this, the combination of the following three pattern lengths starting from an arbitrary delimiter is unique, that is, in the scribe area 7 corresponding to the X or Y axis direction in one chip, and continuously. The condition is that there is no overlap in the combination of the three pattern lengths. This is hereinafter referred to as a non-overlapping condition. In determining the pattern length, it is necessary to consider the following. First, the pattern length must be determined cyclically.
That is, if P1, P2, and P3 are determined, the first two of the next pattern are P2 and P3, and the next pattern P4 following P2 and P3 is determined while satisfying the above-mentioned non-overlapping condition under the conditions. There is a need to. Second, the distance U including the three pattern lengths needs to be averaged as a whole. This is where (P1, P2, P3) = (d, d, d),
Another reason is that if (p1, p2, p3) = (10d, 10d, 10d), the distribution of the delimiters for determining the coordinate position greatly varies, which causes practical inconvenience. The combination of P1, P2, and P3 determined under the above conditions complicates the correspondence with the actual coordinate values. Therefore, as shown in FIG.
Table data is stored in advance so that the coordinate value X can be obtained using the combination of 1, P2, and P3 as an index, and is referred to at the time of use. Similarly, if a pattern in which the coordinate position on the Y-axis coordinate is encoded is formed in the scribe area 7 with respect to the Y axis, the X and Y coded patterns in the X direction and the Y direction of the scribe area 7 are formed. The position is determined, and the position indicated by arbitrary design coordinates in the chip 10 can be determined. If it is desired to define the position of Xn more finely as described above, the pattern unit section U
May be shortened and the bit width may be increased. The same applies to the Y direction. In the above description, the pattern combination is 3 and the pattern length is 10 steps. However, the number of pattern combinations and the number of steps of the pattern length may be different numerical values.

FIG. 8 shows a third embodiment using a scribe area. This method is a modification of the first embodiment using the scribe area shown in FIG. 10, and a section U represents one unit of the encoded pattern. Section D is a delimiter indicating a break between units of the pattern. Section B is a bit pattern. If there is a rectangular cut pattern as shown in a part of section B, the binary code 1
And 0 if none. In FIG. 12, the cut width of the rectangle is set to one half of one side of the bit area section B, but this width may be an arbitrary fixed distance. The delimiter and the bit pattern are identified based on the difference between the pattern widths S1 and S2. Although FIG. 12 shows S1: S2 = 2: 1, this ratio is arbitrary as long as it is the same between the pattern units. In the first embodiment using the guard ring, one bit has a depth d. d is quantized in six stages. That is, assuming that the minimum unit distance is w, the pattern length Pn has six steps of d = w × n (n = 0, 1, 2,..., 5). This makes it possible to represent a hexadecimal number with one bit, and the value of 6 to the fourth power, that is, a value from 0 to 1295, is about half as long as the first embodiment using the scribe area. Can be expressed.
The correspondence with the coordinate values is the same as in the first embodiment using the scribe area. The embodiment using the scribe area is described in 3 above.
As described above, other encoding methods such as bit pattern encoding methods such as NRZ-I, MFM, and MDM used in magnetic recording devices and the like are also applicable. Also, the pattern to be formed has been described as a rectangle, but if it can be detected, other shapes,
For example, the shape may be a sawtooth shape, a triangle, a semicircle, or the like.

Next, a description will be given of a third embodiment in which a blank area 9 between the guard ring portion 8 and the chip 10 is used. FIG. 13 is an enlarged view of the lower left corner of the semiconductor chip shown in FIG. The design coordinate system is represented by an X axis and a Y axis defined by a design coordinate origin 3 and a scribe center. 8 is a guard ring portion, 10 is a chip, and 9 is a blank area between the guard ring portion 8 and the chip 10. A hatched rectangular area 12 shown in FIG. 13 is a pattern formed for the same purpose as the pattern described in the above embodiment using a scribe area. A coordinate value on the X axis or a coordinate value on the Y axis is encoded using the position of the rectangular pattern in the directions corresponding to the X axis and the Y axis, the size of the rectangular pattern, and the distance between the rectangular patterns.

The same pattern as the pattern disclosed in the scribe area 7 can be applied to the encoded pattern in the embodiment using the blank area 9. Xst in FIG.
“art” corresponds to “Xstart” in the first embodiment using the scribe area disclosed in the scribe area 7.

As described above, the case where the pattern in which the position information is encoded is formed in the guard ring portion, the case where the pattern is formed in the scribe region, and the case where the pattern is formed between the scribe region and the chip have been described. It is sufficient that the pattern encoded with is formed on the uppermost layer portion or a layer that can be observed by a method using an optical or an electron beam by an ultrasonic method at the time of visual observation.

In the above, a pattern obtained by encoding position information formed on a semiconductor chip has been described. In order to form this pattern at the above-mentioned predetermined position of each chip on a wafer, it is used for a stepper in an exposure process. The reticle must also be formed at a corresponding position.

[0019]

According to the present invention, a pattern obtained by coding the position on each coordinate axis of the design coordinate system so that the position in the chip can be identified by the design coordinate value is placed in a specific area in the horizontal and vertical directions on the outer periphery of the chip. By providing, the pattern is read by a computer at the time of observation, the pattern is extracted by image processing, the pattern encoded by its position, shape, distance between the patterns, etc. is decoded and the position information on each coordinate axis is read, Since it is possible to position the chip, when the defect position that causes the final functional defect of the semiconductor chip detected by the fail bit inspection is specified in the design data, to observe and analyze the defect cause Review the semiconductor chip to be observed or the semiconductor wafer on which the semiconductor chip is built when visually confirming Loaded onto stage microscope or the like, such as station is installed, search position in the location specified in the CAD data is performed accurately, the effect of reducing the man-hours of observation. In addition, since it is possible to observe a defect position which causes a final functional defect of the semiconductor chip in a short time, it is expected that feedback of process improvement is quickened.

[Brief description of the drawings]

FIG. 1 is a plan view showing an arrangement of semiconductor chips on a semiconductor wafer.

FIG. 2 is a diagram showing a variation of an XY coordinate system.

FIG. 3 is a plan view showing a schematic configuration of a semiconductor chip.

FIG. 4 is an enlarged plan view showing a corner portion of the semiconductor chip.

FIG. 5 is a plan view showing a pattern encoding method in a guard ring unit.

FIG. 6 is a plan view showing a pattern encoding method in a guard ring unit.

FIG. 7 is a diagram illustrating a correspondence table between an encoding pattern and a decode value.

FIG. 8 is a plan view showing a pattern encoding method in the guard ring unit.

FIG. 9 is an enlarged plan view showing a corner portion of the semiconductor chip.

FIG. 10 is a plan view showing a method of encoding a pattern in a scribe area.

FIG. 11 is a plan view showing a method of encoding a pattern in a scribe area.

FIG. 12 is a plan view showing a method of encoding a pattern in a scribe area.

FIG. 13 is an enlarged plan view showing a corner portion of the semiconductor chip.

[Explanation of symbols]

1. Semiconductor chip 2. Scribe center 3.
Design coordinate origin 4 ... Scribe center intersection 5 ... Scribe center intersection 7 ... Scribe center intersection 7 ... Scribe area 8 ... Guard ring 9 ... Blank area between chip and guard ring 10 ... Chip 11 ... Pattern with encoded position information 12 ... pattern in which position information is encoded

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masahiro Watanabe 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd.Production Technology Research Institute (72) Inventor Maki Maki Tanaka 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa (72) Inventor Seiji Ishikawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Japan Inside (72) Inventor Yusutoshi Sugimoto 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Inside the Manufacturing Device Development Center

Claims (12)

[Claims] 1. A pattern in which a position on each coordinate axis of the design coordinate system is encoded in a specific region on the chip so that a position in the chip can be identified by a design coordinate value in a peripheral region of the semiconductor chip. A semiconductor chip characterized by the above-mentioned. 2. The semiconductor chip according to claim 1, wherein the encoding according to claim 1 is performed using an interval between patterns of the same shape formed in a specific area on said chip. 3. The semiconductor chip according to claim 1, wherein the encoding according to claim 1 is performed by using a combination of shapes of patterns formed in a specific area on said chip. 4. The semiconductor chip according to claim 1, wherein the specific region on the chip is a guard ring portion of each chip formed on the semiconductor wafer. 5. A semiconductor chip according to claim 1, wherein the specific area on the chip is a scribe area of each chip formed on a semiconductor wafer. 6. The semiconductor chip according to claim 1, wherein the specific area on the chip is an area between the guard ring portion of each chip formed on the semiconductor wafer and the chip. . 7. A pattern in which a position on each coordinate axis of the design coordinate system is encoded in a specific region on the chip so that a position in the chip can be identified by a design coordinate value in a peripheral region of the semiconductor chip. A reticle for manufacturing a semiconductor, comprising: 8. The reticle according to claim 7, wherein the encoding according to claim 7 can be performed by using an interval between patterns of the same shape formed in a specific area on said chip. 9. A reticle according to claim 7, wherein the encoding according to claim 7 can be performed by using a combination of shapes of patterns formed in a specific area on said chip. 10. A reticle for manufacturing a semiconductor device according to claim 7, wherein the specific area on the chip is a guard ring portion of each chip formed on the semiconductor wafer. 11. A semiconductor manufacturing reticle according to claim 7, wherein the specific area on the chip is a scribe area of each chip formed on the semiconductor wafer. 12. A specific region on a chip according to claim 7 or 9, wherein the specific region on the chip is a region between the guard ring portion of each chip formed on the semiconductor wafer and the chip. Semiconductor manufacturing reticles.