JPH1011301A - Multitask processor and multitask processing control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the total performance of a microprocessor from decreasing even when the number of tasks to be processed is less than the number of register groups of the microprocessor. SOLUTION: When it is necessary to save and reload a context, a saving/ reloading control means 12 saves a context stored in one of register groups 24-1 to 24-M in a context storage means 18 through saving/reloading buses 11, 15, and 16 provided independently of a bus 17 and reloads a context to be processed which is stored in the context storage means 18 to the register group, so ordinary task processing can be performed simultaneously with the saving and loading of the contexts to reduce the overhead of the saving/ reloading processing, thereby improving the total performance of the multitask processor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multitasking processing apparatus and a multitasking processing control method, and more particularly to a context switching (Cont.
The present invention relates to a multitask processing device for performing ext switching) and a multitask processing control method.

[0002]

2. Description of the Related Art In recent microprocessors,
Multitasking for processing a plurality of tasks in parallel has been performed. There are a plurality of types of methods for realizing this multitasking, and context switching is known as the simplest of these methods.

Since a conventional microprocessor has only one set of register files (register groups), when switching tasks, the context which is the contents of the register file is stored in a context memory (for example, main memory) which is an external memory. In the case where the task is performed after saving the contents of the register file, the corresponding context is restored from the context memory to the register.

However, in the above-mentioned conventional microprocessor, access to the context memory is required every time task switching occurs. Switching of the context memory space, for example, switching of the main memory space, requires a considerable amount of time, and thus has the problem of degrading the performance of the entire microprocessor.

[0005]

In order to solve the above problem, there has been proposed a method of improving performance by providing a plurality of register files and reducing the frequency of switching of the context memory space.

FIG. 11 shows a schematic block diagram of a microprocessor having a plurality of register files. The microprocessor 100 includes a plurality of register files 101-1 to 101-1 each storing a context of one task.
01-n and a plurality of register files 101-1 to 101-n
And a register file selection circuit 105 that outputs a control signal for selecting a register file to be used for task processing, and a register file selection circuit 105 that determines which task stores a context corresponding to the task.
Internal bus (internal address bus and internal data bus) 10 for connecting 1-n to arithmetic circuit 110 and control circuit 111
6 and a bus control circuit 107 for controlling the internal bus 106 and the external data bus 109.

Further, the microprocessor 100 includes:
A context that cannot be stored in the register files 101-1 to 101-n is saved, and a data / context memory 108 for storing various data is connected via an external data bus 109.

Next, the operation will be described. 1) The number N of tasks to be processed is less than the number n of register files
In the following case (N ≦ n) In this case, the context of each task is stored in one of the register files.

Therefore, when task switching occurs, the register file selection circuit 105 determines the register file corresponding to the task to be switched from among the plurality of register files 101-1 to 101-n, and responds. A control signal for activating only the register file 101-X (X = 1 to n) is output.

Thus, thereafter, only the activated register file 101-X can be accessed, and the arithmetic circuit 110 and the control circuit 1 are controlled based on the context stored in the register file 101-X.
11 performs the operation.

Therefore, if the number N of tasks to be processed is less than the number n of register files, the register file 101
-1 to 101-n, and there is no need to access the data / context memory 108 for storing various data via the external data bus 109. Switching can be performed, and the performance of the entire microprocessor 101 can be improved. 2) The number N of tasks to be processed is equal to the number n of register files.
(N> n) In this case, among the contexts of the N tasks, n
The contexts corresponding to the tasks are stored in any of the register files, and the (N−n) contexts are stored in the data / context memory 108.

Therefore, when task switching occurs, the register file selection circuit 105 determines that the context corresponding to the task to be switched to is the register file 101.
-1 to 101-n, and if any of the register files 101-1 to 101-n has a context corresponding to the task to be switched to, the corresponding context is determined. Register file 101-X (X = 1 to
A control signal for activating only n) is output.

As a result, thereafter, only the activated register file 101-X can be accessed, and the arithmetic circuit 110 and the control circuit 1 are controlled based on the context stored in the register file 101-X.
11 performs the operation.

On the other hand, any register file 101-1
If there is no context corresponding to the task at the switching destination in any of the to-101-n, the register file selection circuit 105 stores the context to be saved in the data / context memory 108 based on the task priority and the like. Register file 101-Y (Y = 1 to n)
And by controlling the bus control circuit 107, the context stored in the register file 101-Y is transferred to the internal bus 106 and the data bus 10-Y.
9 to the data / context memory 108.

When the saving is completed, the register file selection circuit 105 controls the bus control circuit 107 again to change the context to be restored to the data bus 109.
And the register file 101-Y via the internal bus 106
To be stored. Then, the register file selection circuit 105
Outputs a control signal for activating only the register file 101-Y when the return of the context is completed.

Thereafter, only the activated register file 101-Y can be accessed, and the arithmetic circuit 110 and the control circuit 1 are controlled based on the context stored in the register file 101-Y.
11 performs the operation.

As described above, when the number N of tasks to be processed is larger than the number n of register files, not all contexts can be stored in the register file, and the time for saving / restoring contexts is not sufficient. However, there is a problem that the performance of the entire microprocessor is deteriorated.

An object of the present invention is to provide a multitask processing apparatus and a multitask processing apparatus which do not lower the performance of the entire microprocessor even when the number of tasks to be processed is larger than the number of register files (register groups) of the microprocessor. A task processing control method is provided.

[0019]

According to the first aspect of the present invention,
Each of which has M (M; an integer of 2 or more) registers for storing a context and a bus connected to the M registers for performing task processing, and is stored in any one of the selected registers. In a multitask processing device for sequentially performing a plurality of the task processes based on the context, the context storage means for storing the context, and the bus are provided separately, and the M registers are provided. Provided between a group and the context storage means to save / restore the context
The context is saved to the context storage means via the save / restore bus for performing the restoration and the save / restore bus, or the context is restored from the context storage means to the register group. Evacuation / recovery control means for performing control for causing the evacuation / recovery control to be performed.

According to the first aspect of the present invention, when it is not necessary to perform the context save / restore processing, the multitask processing device registers the register corresponding to the task to be processed among the M register groups. Tasks are processed by exchanging data stored in the group via a bus.

By switching the register group used for processing, multitask processing for sequentially performing a plurality of task processing is performed. On the other hand, when it is necessary to perform the context save / restore process, that is, when the context corresponding to the task to be processed is not stored in the M register groups, the save / restore control means performs the processing with the bus. The context stored in any of the register groups is saved to the context storage unit via the separately provided save / restore bus, and the context to be processed stored in the context storage unit is stored in the context storage unit. Return to the register group.

Therefore, normal task processing can be performed in parallel with the context save / restore via the bus. According to a second aspect of the present invention, in the first aspect of the present invention, the save / restore control means includes a priority order of each task process excluding the currently executing task process in parallel with the currently executing task process. Based on the processing state, a determination is made as to a task process that can be saved next and a task process that should be restored.

According to the second aspect of the present invention, in addition to the operation of the first aspect, the save / restore control means excludes the currently executing task processing in parallel with the currently executing task processing. Based on the priority and the processing state of each task process, a process of determining the next evacuable task process and the task process to be restored is performed.

According to a third aspect of the present invention, when the total number of tasks to be processed in parallel is L (L; an integer of 2 or more) in the first or second aspect, and L ≦ M, Stores a context corresponding to all task processing in L register groups of the M register groups.

According to the invention of claim 3, in addition to the effect of the invention of claim 1 or 2, the total number of tasks to be processed in parallel is L (L; an integer of 2 or more), If L ≦ M, the context corresponding to all task processes is set to M
Since the data is stored in the L register groups among the register groups, the processing can be performed at a high speed without the context saving / restoring processing accompanying the task switching.

The invention according to claim 4 has M (M; an integer of 2 or more) register groups each storing a context and a bus connected to the M register groups for performing task processing. A multitask processing control method for a multitask processing device that sequentially performs a plurality of the task processes based on the context stored in any one of the selected register groups; A discriminating step of discriminating a next evacuable task process and a task process to be restored based on the priority and the processing state of each task process except the task process that is currently being executed; and Are provided separately and provided between the M register group and the context storage means to save / restore the context. Control for saving a context corresponding to the task task that can be saved to the context storage means via the save / restore bus, or for returning the context from the context storage means to the register group. Evacuation / return control step of performing

According to the fourth aspect of the present invention, the determining step is performed next based on the priority and the processing state of each task process excluding the currently executing task process in parallel with the currently executing task process. A possible task process and a task process to be returned are determined. Thus, the save / restore step is provided separately from the bus based on the determination in the determination step, and is provided between the M register group and the context storage means to save / restore the context. A context corresponding to the savable task processing is saved to a context storage unit via a save / restore bus for performing, or control is performed to restore the context from the context storage unit to a register group. .

According to a fifth aspect of the present invention, in the multitask processing control method according to the fourth aspect, the total number of tasks to be processed in parallel is set to L (L; an integer of 2 or more), and when L ≦ M. Comprises a storing step of storing contexts corresponding to all task processes in L register groups of the M register groups.

According to the fifth aspect of the present invention, in addition to the effect of the fourth aspect of the present invention, the storing step is such that when L ≦ M, L register groups out of M register groups Stores the context corresponding to all task processing.

[0030]

Preferred embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows a schematic block diagram of a microprocessor as an embodiment of a multitask processing device.

The microprocessor 30 is roughly divided into
M register files (register group) 24-1 to
Register circuit 1 having 24-M and performing save / restore processing
0, an arithmetic circuit 26 for performing various operations based on the contents of the register files 24-1 to 24-M, and an internal bus (internal address bus) for connecting the register files 24-1 to 24-M and the arithmetic circuit 26 to be described later. And an internal data bus 17, and a bus control circuit 22 for controlling the internal bus 17 and an external data bus 13 described later.

The register circuit 10 is provided separately from the internal bus 17, and has register files 24-1 to 24-M to be described later.
And a control signal SC for selecting a register file to be used for task processing in order to control context save / restore in accordance with the processing state of the arithmetic circuit 26. Save / restore control circuit 12 and save / restore bus control circuit 14 for controlling save / restore internal bus 11, save / restore data bus 15, and save / restore address bus 16, which will be described later.
And M (M; an integer of 2 or more) register files (register groups) 24-1 to 24-M each storing a context of one task.

The bus control circuit 22 is connected to an external data bus 13 to which a data memory 20 as an external memory for storing various data is connected. The save / restore control circuit 12 includes a plurality of register files 24-1 to 24-M
Is provided with a register file selection circuit 12A that determines which task corresponds to which context.

The save / restore bus control circuit 14 has a context memory 18 as an external memory for storing the saved context via a save / restore data bus 15 and a save / restore address bus 16. It is provided with. Next, the outline operation will be described. 1) The number N of tasks to be processed is less than the number M of register files
In the following case (N ≦ M) In this case, the context of each task is stored in any of the register files 24-1 to 24-M.

Therefore, when task switching occurs, the register file selection circuit 12A determines the register file corresponding to the task to be switched from among the plurality of register files 24-1 to 24-M, and responds. A control signal SC for activating only the register file 24-X (X = 1 to M) is output.

Thus, thereafter, only the activated register file 24-X can be accessed, and the arithmetic circuit 26 operates based on the context stored in the register file 24-X. . Therefore, if the number N of tasks to be processed is less than the number M of register files, the register files 24-1 to 24
There is no occurrence of a context that cannot be stored in -M, and there is no need to access the context memory 18 via the save / restore data bus 15 and the save / restore address bus 16, so that task switching can be performed at high speed. This can improve the performance of the entire microprocessor 3. 2) The number N of tasks to be processed is equal to the number M of register files.
(N> M) In this case, among the contexts of the N tasks, M
The contexts corresponding to the tasks are stored in any of the register files 24-1 to 24-M.
(NM) contexts are context memory 1
8 is stored. i) Control when save / restore processing is not performed Therefore, when task switching occurs, the register file selection circuit 12A sets the internal bus 17, the bus control circuit
7. In parallel with the current processing of the task of the arithmetic circuit 26 using the external data bus 13 and the data memory 20, the context corresponding to the task to be switched is stored in the register files 24-1 to 24-M. It is determined whether there is any of them.

Based on the judgment of the register file selection circuit 12A, the save / restore control circuit 12 determines whether a context corresponding to the task to be switched exists in any of the register files 24-1 to 24-M. , And outputs a control signal SC for activating only the corresponding register file 24-X (X = 1 to M).

Thereafter, only the activated register file 24-X can be accessed, and the arithmetic circuit 26 performs task processing based on the context stored in the register file 24-X. Becomes ii) Control when performing save / restore processing On the other hand, if there is no context corresponding to the task to be switched to in any of the register files 24-1 to 24-M, the register file selection circuit 12A sets the task Then, the register file 24-Y (Y = 1 to M) storing the context to be saved in the context memory 18 is determined based on the priority or the like.

Thus, the save / restore control circuit 12 controls the save / restore bus control circuit 14 with the control signal SC, thereby saving the context stored in the register file 24-Y to the internal bus for save / restore. 11 and a save / restore data bus 15 and a save / restore address bus 16 to save to the context memory 18.

When the saving of the context stored in the register file 24-Y to the context memory 18 is completed, the saving / restoring control circuit 12 returns to the control signal S
By controlling the save / restore bus control circuit 14 by C, the context to be restored to the register file 24-Y is changed to the save / restore data bus 15, the save / restore address bus 16, and the save / restore internal bus 11 Is stored in the register file 24-Y.

When the context is completely restored to the register file 24-Y, the save / restore control circuit 12 outputs a control signal SC for activating the register file 24-Y. This makes it possible to access the activated register file 24-Y thereafter, and the arithmetic circuit 26 performs the processing of the corresponding task based on the context stored in the register file 24-Y. It will be.

The above save / restore processing is performed on the internal bus 17,
Using the bus control circuit 7, the external data bus 13, and the data memory 20, the task can be performed in parallel with the task of the arithmetic circuit 26 that is currently being performed. Therefore, it is possible to reduce the overhead of register file switching time. Therefore, the performance of the entire microprocessor can be improved.

As described above, even when the number N of tasks to be processed is larger than the number M of register files, it is possible to perform processing equivalent to the case where all contexts are stored in the register file. It is sufficient to prepare a sufficient number of register files so that the processing of the currently executing task is not affected by the return / save processing, so that the overhead required for register switching is minimized. Since the number of required register files is small, the performance of the entire microprocessor can be improved despite a simple configuration being achieved.

Next, a more specific operation will be described with reference to FIGS. Hereinafter, a case where the number of register files is M = 2 will be described for simplification of the description. In this case, as shown in FIG. 2, there are four tasks to be processed: a first task T1, a second task T2, a third task T3, and a fourth task T4. Priority of the first task T1 = 1 (highest priority), priority of the second task T2 = 2, priority of the third task T3 = 3, priority of the fourth task = 4 (lowest priority). Further, as shown in FIG. 2, the task state includes an execution state in which the task is being executed (indicated as “RUN” in the figure), and an executable state in which the task can be immediately shifted to the execution of the task (in the figure, “ READY ”), and a standby state such as key input waiting (indicated as“ WAIT ”in the figure). The information on the states of these tasks (for example, see FIG. 2) is held by the save / restore control circuit 12.

In FIGS. 2 to 10, for the sake of simplicity, the first task T1 is a task T1, the second task T2 is a task T2, the third task T3 is a task T3, and the fourth task T4 is a task T4. It is represented as T4. In FIGS. 4 to 10, the bus control circuit 22 and the save / restore bus control circuit 14 are omitted for simplification of the illustration.

In the initial state, FIG. 2 and FIG.
As shown in the figure, the first task T1 is in the execution state (= “RU
N "), the second task T2, the third task T3, and the fourth task T4 are in an executable state (=" READY "). At this stage, the arithmetic circuit 26 performs the processing of the first task T1 based on the context of the first task T1 stored in the first register file 24-1. The result of the processing of the first task T1 is stored in the data memory 20 via the internal bus 17, the bus control circuit 22, and the external data bus 13.

The context of the second task T2 having the priority = 2 is stored in the second register file 24-2. Furthermore, the context memory 18 stores the task of priority = 3, that is, the context of the third task T3 and the context of the fourth task T4 having the lowest priority at the present time.

When a state of waiting for data input via the keyboard or the like occurs during the processing of the first task T1,
As shown in FIG. 5A, the first task T1 enters a waiting state (= "WAIT"), and the arithmetic circuit 26 uses the context of the second task T2 stored in the second register file 24-2. To execute the second task T2 (=
"RUN").

In parallel with the execution of the second task T2, the register file selection circuit 12 of the save / restore control circuit 12
A makes a determination based on the priority and state of each task shown in FIG. 5A, and the first stored in the first register file 24-1 in the standby state (= "WAIT").
The context of task T1 is stored in context memory 18.
Is determined to be evacuated.

Based on the discrimination of the register file selection circuit 12A, the save / restore control circuit 12 sets the save / restore bus control circuit 1 as shown in the flowchart of FIG.
4 is controlled by the control signal SC, and the internal bus 11 for saving / restoring, the data bus 15 for saving / restoring, and the address bus 16 for saving / returning from the first register file 24-1.
Via the first task T1 in the context memory 18
Is saved (step S1).

FIG. 6 shows a state after the context of the first task T 1 has been saved in the context memory 18. Then, in parallel with the context saving processing of the first task T1, the arithmetic circuit 26 performs the processing of the second task T2 based on the context of the second task T2 stored in the second register file 24-2. (Step S3).

Further, the save / restore control circuit 12 is in the executable state (= “READY”) of the tasks whose context is stored in the context memory 18 and has the context (“READY”) of the task with the highest priority. 5 (a), that is, in this case, the context of the third task T3 is saved / restored by the bus control circuit 1
4 is controlled by the control signal SC, and the first register file 24 is saved via the internal bus 11 for save / restore, the data bus 15 for save / restore, and the address bus 16 for save / restore.
It returns to -1 (step S2).

FIG. 7 shows a state after the context of the third task T3 has been returned to the first register file 24-1. If a state of waiting for data input via the keyboard occurs during the processing of the second task T2, the second task T2 enters a waiting state (= "WAIT") as shown in FIG. 8A.
And the arithmetic circuit 26 calculates the first register file 24-1
The third task T3 is set to the execution state (= "RUN") using the context of the third task T3 stored in.

In parallel with the execution of the third task T3, the register file selection circuit 12 of the save / restore control circuit 12
A determines based on the priority and state of each task shown in FIG. 8A, and the second task stored in the second register file 24-2 in the standby state (= “WAIT”) T2 context is used as context memory 1
8 is determined to be evacuated.

Based on the determination by the register file selection circuit 12A, the save / restore control circuit 12 controls the save / restore bus control circuit 14 by the control signal SC, similarly to the processing shown in the flowchart of FIG. From the second register file 24-2 to the context memory 18 via the save / restore internal bus 11, the save / restore data bus 15 and the save / restore address bus 16,
The context of task T2 is saved (corresponding to step S1 in FIG. 3).

FIG. 9 shows a state after the context of the second task T 2 has been saved in the context memory 18. Then, in parallel with the process of saving the context of the second task T2, the arithmetic circuit 26 performs the process of the third task T3 based on the context of the third task T3 stored in the first register file 24-1. (Corresponding to step S3 in FIG. 3).

Further, the save / restore control circuit 12 is provided in
As shown in FIG. 5, among the tasks whose context is stored in the context memory 18, the executable state (=
"READY") and the context of the task with the highest priority (see FIG. 8A), that is, in this case, the context of the fourth task T4 is saved /
Internal bus 11 for restoration and data bus 15 for saving / restoring
Then, the process returns to the first register file 24-1 via the save / restore address bus 16 (corresponding to step S2 in FIG. 3).

Subsequently, the context is saved / restored and the registers are switched in the same manner to execute the multitask processing. As described above, according to the present embodiment, the context save / restore process can be performed without interrupting the execution of the task in the arithmetic circuit 26, that is, in parallel with the execution of the task in the arithmetic circuit 26. As a result, the overhead for the save / restore processing associated with the register file switching can be reduced, and the performance of the entire microprocessor can be improved.

[0059]

According to the first aspect of the present invention, the multi-task processing device needs to perform context save / restore processing, that is, the context corresponding to the task to be processed in the M register groups. Is not stored, the save / restore control means stores the context stored in any of the register groups in the context storage means via the save / restore bus provided separately from the bus. Since the context to be processed, which is stored in the context storage means, is restored in the register group, the normal task processing can be performed in parallel with the context save / restore. The overhead can be reduced and the performance of the entire multitask processing device can be improved.

According to the second aspect of the present invention, in addition to the effect of the first aspect, the save / restore control means excludes the currently executing task processing in parallel with the currently executing task processing. Based on the priority and the processing state of each task process, a task process that can be saved next and a task process that should be restored are performed. The register group can be switched immediately, and the overhead of switching can be further reduced.

According to the invention of claim 3, in addition to the effect of the invention of claim 1 or 2, the total number of tasks to be processed in parallel is L (L; an integer of 2 or more), If L ≦ M, the context corresponding to all task processes is set to M
Since the data is stored in the L registers among the plurality of registers, the processing can be performed at high speed without performing the context save / restore processing associated with the task switching, thereby deteriorating the performance of the multitask processing device. Nothing.

According to the fourth aspect of the present invention, the determination step is performed next based on the priority and the processing state of each task process excluding the currently executing task process in parallel with the currently executing task process. A possible task process and a task process to be restored are determined, and a save / restore process is provided separately from the bus based on the determination in the determination process, and is a save / restore bus for performing context save / restore. , The context corresponding to the task task that can be saved is saved to the context storage means, or the control for restoring the context from the context storage means to the register group is performed. The save / restore process is performed in parallel via the save / restore bus to reduce the overhead of the save / restore process. Multitasking overall performance can be improved.

According to the fifth aspect of the present invention, in addition to the operation of the fourth aspect of the present invention, the storing step is: if L ≦ M, L of the M register groups Since the contexts corresponding to all the task processes are stored, the process can be performed at a high speed without the context saving / restoring process accompanying the task switching, and the performance in the multitasking process is not reduced.

[Brief description of the drawings]

FIG. 1 is a schematic configuration block diagram of a multitask processing device according to an embodiment.

FIG. 2 is a diagram illustrating an example of task processing priorities and states;

FIG. 3 is an operation processing flowchart of the embodiment.

FIG. 4 is an operation explanatory diagram (part 1) of the embodiment;

FIG. 5 is an operation explanatory diagram (part 2) of the embodiment.

FIG. 6 is an operation explanatory view (3) of the embodiment.

FIG. 7 is an operation explanatory view (part 4) of the embodiment.

FIG. 8 is an operation explanatory view (No. 5) of the embodiment;

FIG. 9 is an operation explanatory view (No. 6) of the embodiment;

FIG. 10 is an operation explanatory view (No. 7) of the embodiment.

FIG. 11 is a schematic block diagram of a conventional multitask processing device.

[Explanation of symbols]

 Reference Signs List 10 register circuit 11 internal bus for save / restore 12 save / restore control circuit 12A register file selection circuit 13 external data bus 14 bus control circuit for save / restore 15 data bus for save / restore 16 address bus for save / restore 17 internal bus 18 Context Memory 20 Data Memory 22 Bus Control Circuit 24-1 to 24-M Register File (Register Group) 26 Arithmetic Circuit 30 Microprocessor

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akinori Shiomi 3776 Handa-cho, Hamamatsu City, Shizuoka Pref. Inside Yasushi Sogyo Co., Ltd., 1500, Yazaki Sogyo Co., Ltd., in Shizuoka Prefecture, Japan Inside the inventor's record, Masafumi 1500, Yazaki Sogyo Co., Ltd.

Claims (5)

[Claims] 1. Each of a plurality of M (M; an integer of 2 or more) registers for storing a context and a bus connected to the M registers for performing task processing. In a multitask processing device that sequentially performs a plurality of the task processes based on the context stored in the register group, a context storage unit that stores the context, and the bus is separately provided, and A save / restore bus provided between the M register group and the context storage means for saving / restoring the context; and storing the context via the save / restore bus. Save the context to the context storage means, or restore the context from the context storage means to the register group And a save / return control means for performing control for the multitask processing device. 2. The multi-task processing device according to claim 1, wherein said save / restore control means includes a priority order of each task process excluding said currently executing task process in parallel with a currently executing task process. A multi-task processing device that performs a determination process of a task process that can be saved next and a task process that should be restored based on a processing state. 3. The multitask processing device according to claim 1, wherein the total number of tasks to be processed in parallel is L (L; an integer of 2 or more). A multitask processing device, wherein a context corresponding to task processing is stored in L registers among the M registers. 4. A memory device comprising: M (M; an integer of 2 or more) registers each storing a context; and a bus connected to the M registers for performing task processing. A multitask processing control method for a multitask processing device that sequentially executes a plurality of the task processes based on the context stored in a group of registers, wherein the currently executing task is executed in parallel with the currently executing task process. A discriminating step of discriminating the next evacuable task process and the task process to be restored based on the priority and the processing state of each task process except the process; provided based on the discrimination, separately from the bus; A save / restore bus provided between the M register group and the context storage means for saving / restoring the context; A save / restore control step of saving the context corresponding to the task process that can be saved to the context storage means, or performing control for restoring the context from the context storage means to the register group. A multitask processing control method, comprising: 5. The multitask processing control method according to claim 4, wherein the total number of tasks to be processed in parallel is L (L; an integer of 2 or more), and when L ≦ M, the M tasks A multitask processing control method, comprising a storage step of storing a context corresponding to all task processes in L register groups of the register group.