JPH10107730A - Power consumption control system for tdma portable radio equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption further more for a reception slot intermittent reception period in the waiting state of a time division multiple access(TDMA) portable radio equipment. SOLUTION: The equipment is provided with a low frequency oscillator 11 that generates a low frequency clock and a transistor(TR) 15 that applies on/off control to a high frequency clock from a high frequency oscillator 2. A TDMA control section 7 is provided with two OR circuits 12, 13 and a clock flag generator 14. Every time a CPU 1 receives a reception slot, the power save mode is set, and when a time up to a succeeding reception slot is set to a timer counter 3, the timer counter 3 is operated by a low frequency clock, its status is given to the TR 15 and the two OR circuits 12, 13, by which the high frequency clock is stopped and clock supply to a slot counter 5 is stopped to stop the operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a slave unit of a digital cordless telephone system based on a time division multiple access (TDMA) system, and more particularly to reduction of power consumption by intermittent reception of a standby period of the slave unit. Power control (power saving) method for power consumption.

[0002]

2. Description of the Related Art One of the important technical issues is not only digital cordless telephones but also low power consumption for extending the battery duration of portable mobile devices as much as possible. FIG. 3 is a block diagram showing an example of a partial circuit configuration of a slave unit of a conventional digital cordless telephone. In FIG. 3, 1 is a CPU (central processing unit) having a power save mode, 2 is a high frequency oscillator for generating a high frequency clock, 3 is a timer counter,
4 is a frequency dividing circuit, 5 is a slot counter for generating a TDMA slot, 6 is a radio section control circuit, 7 is a T
The DMA control unit 8 is a radio unit and a modem unit. The high frequency clock generated by the high frequency oscillator 2 is transmitted to the CPU 1 and the TD
The signal is supplied to the frequency dividing circuit 4 of the MA control unit 7, and the frequency dividing circuit 4 divides the high frequency clock and outputs a reference clock for operating each circuit in the TDMA control unit 7. The timer counter 3 counts the power save mode and interrupts the CPU 1 to cancel the power save mode. The slot counter 5 generates a slot of the TDMA system and supplies the generated slot to the timer counter 3 and also to the radio unit control circuit 6 to control the radio unit and the modem unit 8.

Next, the battery saving control operation of the above-described conventional circuit during a standby period will be specifically described. FIG. 4 is a time chart for explaining a conventional power saving control method in a standby period. As shown in FIG. 4, the CPU 1 of the slave unit is in an operation mode of receiving the reception slot R1 of the slave unit at, for example, a one-second cycle, and is in a power save mode of saving power consumption between other slots. In such intermittent reception at the time of standby, unnecessary circuits during the power save mode, for example, a part of the reception mixer, the amplifier, the demodulator, the synthesizer, the switching control unit and the TDMA control unit are stopped to reduce the power consumption. Saving money. The high-frequency clock generated by the high-frequency oscillator 2 is, for example, about 20 MHz and operates continuously.
After the slave unit receives the reception slot R1 of the slave unit,
U1 sets the count value in the timer counter 3 and shifts to the power save mode. When the timer counter 3 counts up the set count value, the CPU 1 enters the operation mode to receive the next reception slot R1.

[0004]

However, the conventional circuit described above has a problem that the power saving efficiency is poor because the high frequency clock, the slot counter 5 and the radio section control circuit 6 always operate during the power saving period during standby. There is. In addition, the above problem is not limited to a cordless telephone handset, but also to a TDMA portable radio.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a TDMA portable radio which can solve the problem of the power saving efficiency during standby in the prior art which is low, and can further reduce the power consumption of the TDMA control unit during the power saving mode. An object of the present invention is to provide a power consumption control method.

[0006]

SUMMARY OF THE INVENTION A power consumption control method for a TDMA portable wireless device according to the present invention comprises a radio section and a modulation / demodulation section for transmitting and receiving TDMA radio waves, a high-frequency oscillator for continuously outputting a high-frequency clock, and a high-frequency oscillator. A CPU operating by a clock and having a power save mode; a frequency dividing circuit for dividing the high frequency clock; a slot counter for continuously generating a TDMA slot based on a reference clock output from the frequency dividing circuit; and a reference from the frequency dividing circuit A radio section control circuit for controlling the radio section and the modulation / demodulation section so that a clock is input and received in a reception slot of the slave unit by a TDMA slot from the slot counter; a reference clock from the frequency dividing circuit; and the slot counter TDMA slot is input and the count value given by the CPU is And a TDMA control unit provided with a timer counter that counts down. During a standby period, the CPU receives a reception slot of the wireless device and executes an operation of a predetermined circuit each time the operation mode shifts from the operation mode to the power save mode. A TDMA mobile phone configured to stop and give a count value indicating a power save mode period to the timer counter, and when the timer counter counts the count value and counts up, interrupts the CPU to cancel the power save mode. In the power consumption control method of a wireless device, a low-frequency oscillator that outputs a low-frequency clock, a transistor that outputs a signal for stopping the high-frequency oscillator by an external control signal, and an output of the high-frequency oscillator as one input. A first OR circuit for providing an output signal to the frequency dividing circuit; A second OR circuit that receives the output of the frequency divider circuit as one input and provides an output signal to the slot counter; and a clock flag generator that outputs a flag indicating slot stop recognition information based on the output of the second OR circuit. The timer counter shifts to a power save mode from the CPU, and when a count value indicating the power save mode period is given, performs operation by a low frequency clock from the low frequency oscillator to control the transistor. A signal is supplied to stop the high-frequency oscillator, and a status is applied to the other input of the first OR circuit and the second input of the second OR circuit. The supply of the high-frequency clock to the slot counter is stopped, and the second OR circuit according to the status outputs the reference clock to the slot counter. Clock supply is stopped to stop the operation of the slot counter, and a flag indicating slot stop recognition information is output from the clock flag generator to be recognized by the CPU. .

[0007]

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a TDMA
Monitoring the slot of the system and checking the reception slot R1 of the slave unit.
When the CPU 1 shifts to the power save mode after receiving the command, the output of the high-frequency oscillator 2 is stopped, the operation of the slot counter 5 is stopped, and the timer counter 3 is controlled by the low-frequency oscillator 11 from, for example, 32. 76
The gist of the present invention is to operate with a low frequency clock of 8 kHz to improve power saving efficiency.

[0008]

FIG. 1 is a block diagram showing an embodiment of the present invention.
In the figure, CPU 1 having a power save mode, C
A high-frequency oscillator 2 for supplying a high-frequency clock to the PU 1 and the frequency dividing circuit 4; a timer counter 3 for counting a power save period; a frequency dividing circuit 4 for generating a reference clock of a TDMA control unit; The slot counter 5 to be performed and the radio unit control circuit 6 for controlling the radio unit and the modulation / demodulation unit 8 are the same as the conventional circuit of FIG.
The portion surrounded by the double line is a portion provided in the present invention, and 11
Is a low frequency oscillator which outputs a low frequency clock of, for example, 32.768 kHz to be supplied to the timer counter 3 during the power saving period. Numeral 12 denotes an OR circuit, which stops the supply of the high frequency clock from the high frequency oscillator 2 to the frequency dividing circuit 4 according to the status from the timer counter 3 during the power saving period. An OR circuit 13 stops the reference clock supplied from the frequency dividing circuit 4 to the slot counter 5 according to the status from the timer counter 3. A clock flag generator 14 stops the reference clock and outputs slot stop recognition information (flag). Reference numeral 15 denotes a transistor for stopping oscillation of the high-frequency oscillator 2 during power saving.

Next, the operation of the present invention will be described with reference to the time chart of FIG. FIG. 2 is a time chart for explaining the operation of the present invention. The slave unit receives the data in the TDMA slot R1 during standby, and instructs the timer counter 3 to shift to the power save mode from the CPU 1 and, under the control of the timer counter 3, logically outputs the output of the frequency dividing circuit 4 which is the reference clock of the slot counter 5. Stop at the sum circuit 13. At the same time when the slot counter 5 stops, the reference clock is stopped, and the TDMA control unit 7 uses the flag from the clock flag generator 14 indicating the slot stop recognition information so that the CPU 1
The DMA controller 7 recognizes the start of the slot stop. The timing at which the reference clock supplied to the slot counter 5 is stopped is supplied from the timer counter 3 operated by the low frequency clock of the low frequency oscillator 11, and is managed by an internal timer at a fixed period of 5 msec. Timer counter 3
A transistor 15 for stopping the oscillation of the high-frequency oscillator 2 in accordance with a command from the
A logical sum circuit 12 that stops supplying power to A control unit 7
As soon as U1 enters the power save mode, the TDM
The operation of the circuits other than the timer counter 3 of the A control unit 7 is also stopped.

After that, when the count time for receiving the next reception slot R1 is increased by the timer counter 3 for managing the standby saving cycle, the transistor 15
Is operated (turned on) to oscillate the high-frequency oscillator 2,
After the oscillation output is stabilized, the TDMA control slot starts operating by supplying the clock flags by the OR circuits 12 and 13 to the CPU 1 and the frequency dividing circuit 4 and supplying the reference clock of the slot counter 5 to the slot counter 5. The next TDMA control slot R1 is received.

As described above, during the power saving period, the timer counter 3 is operated by the low frequency clock of the low frequency oscillator 11, and the supply of the high frequency clock to the TDMA controller 7 and the CPU 1 is stopped by the transistor 15 and the OR circuit 12. At the same time, the TDMA slot is stopped by the OR circuit 13. That is, the slot counter 5 of the TDMA control unit 7 is stopped during the standby saving, and the timer counter 3
Is operated by a low frequency clock, the power saving efficiency in the power save mode is further improved, and the power consumption can be reduced. High frequency clock is 20M
Hz and the low frequency clock is 32.768 kHz,
Since the current consumption is about 100 mA to about 2 mA, the power reduction rate is 1/50.

[0012]

As described in detail above, according to the present invention, in the digital cordless telephone system, when the slave unit shifts to the power saving mode while waiting,
The high frequency oscillator is stopped by the power save start command from the CPU, the operation of the slot counter of the TDMA control unit is stopped, and the high frequency oscillator is started by the timer count completion signal from the timer counter when the power save mode is released, and the slot of the TDMA control unit is started. Since the counter can be activated, the power consumption during the power save mode can be further reduced significantly, which has a great effect in practical use.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart illustrating the operation of the present invention.

FIG. 3 is a diagram illustrating an example of a conventional circuit configuration.

FIG. 4 is a time chart illustrating a conventional operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 High frequency oscillator 3 Timer counter 4 Divider circuit 5 Slot counter 6 Radio section control circuit 7 TDMA control section 8 Radio section and modulation / demodulation section 11 Low frequency oscillator 12, 13 OR circuit 14 Clock flag generator

Claims (1)

[Claims] 1. A radio section and a modulation / demodulation section for transmitting and receiving a radio wave of a TDMA system, a high-frequency oscillator for continuously outputting a high-frequency clock, a CPU operating with the high-frequency clock and having a power save mode, and dividing the high-frequency clock. And a slot counter for continuously generating a TDMA slot based on a reference clock output from the frequency divider circuit, and a reference clock from the frequency divider circuit input and a TDMA slot from the slot counter receiving slot of the slave unit. A radio unit control circuit for controlling the radio unit and the modulation / demodulation unit so as to receive the signal, a reference clock from the frequency dividing circuit, and a TDM from the slot counter.
A TDM provided with a timer counter which counts a count value given from the CPU when the A slot is inputted.
An A control unit, during the standby period, the CPU stops the operation of a predetermined circuit every time a reception slot of the wireless device is received and shifts from the operation mode to the power save mode, and the CPU saves power in the timer counter. A timer indicating a mode period, wherein the timer counter counts the count value and, when counting up, causes the CPU to interrupt the power save mode release.
A In a power consumption control method of a portable wireless device, a low frequency oscillator for outputting a low frequency clock, a transistor for outputting a signal for stopping the high frequency oscillator by an external control signal, and an output of the high frequency oscillator to one input A first OR circuit for providing an output signal to the frequency dividing circuit; a second OR circuit for receiving an output signal of the frequency dividing circuit as one input and supplying an output signal to the slot counter; A clock flag generator that outputs a flag indicating slot stop recognition information based on an output of the sum circuit, wherein the timer counter shifts to a power save mode from the CPU and receives a count value indicating the power save mode period. When the high frequency oscillator is operated by a low frequency clock from the low frequency oscillator and a control signal is given to the transistor. And a status is given to the other input of the first OR circuit and the second input of the second OR circuit. According to the status, the first OR circuit supplies a high frequency clock to the frequency dividing circuit. Stopping, the second OR circuit stops supplying the reference clock to the slot counter to stop the operation of the slot counter according to the status, and outputs a flag indicating slot stop recognition information from the clock flag generator. A power consumption control method for a TDMA portable wireless device, wherein the power consumption control method is configured to be recognized by the CPU.