JPH10107687A - Synchronization following circuit in spread spectrum communication and radio communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the design and to reduce the circuit scale in the synchronization hold circuit in the spread spectrum communication. SOLUTION: A delay device 10 is placed on a path of a reception signal to produce a signal a signal to be sent to a demodulation section 20 and a signal whose phase is shifted from a phase of the signal, and a subtractor 35 is used to generate a difference between the signals whose phases are shifted to each other. A spread code is multiplied (31) with a signal L fed to the demodulation section 20 and with the difference and the product is integrated (32). An integration result H or its code in the demodulation section 20 is multiplied with an integration result P to generate a control signal K to be outputted to an LPF 43. Thus, the synchronization hold circuit is configured with a same performance as a conventional circuit but with a remarkably small circuit scale and the power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization holding circuit and a radio communication apparatus using the same, and more particularly, a spread code synchronization holding circuit and a spreading code used for a spread spectrum communication type receiving apparatus and the like. The present invention relates to a wireless communication device using a synchronization holding circuit.

[0002]

2. Description of the Related Art In recent years, a spread spectrum communication system has been used in which a frequency band is broadened and transmitted more than the information transmission speed. In this communication system, a transmitting side transmits an information signal to be transmitted by spreading a frequency band using a spreading code having a spectrum wider than the band of the information signal, and a receiving side uses the spread band as an original. Convert to the band of the information signal. This communication system has excellent features such as interference resistance, confidentiality, and high-resolution ranging. In this communication system, it is necessary to synchronize the phase between the spreading code included in the received signal and the spreading code generated on the receiving side, and once synchronized, the phase synchronization is held by the synchronization holding circuit. . Phase synchronization holding circuits used for spread spectrum communication type receivers have been widely studied,
For example, the Digital Communication and Spread Spectrum System "Digital Communicat
ions and Spread Spectrum Systems '' (Rondger E. Zieme
r & Roger L. peterson, MACMILLAN) pp. 409-480
The page describes in detail the synchronization maintenance method and its characteristic analysis. Also, there are many patent applications (for example, Japanese Patent Laid-Open Publication No. Sho 62-15947).

FIGS. 7 and 8 show the basic configuration of a conventionally known synchronization holding circuit and changes in signals in respective sections, respectively. A spreading code A generated by a spreading code generator (hereinafter abbreviated as PNG) 50 and a spreading code having a time delay generated by passing the spreading code A through the delay unit 11 or the delay units 11 and 12. B and the spreading code C are multiplied by the input signal rd (t) input from the terminals in the multiplier 21 and the multipliers 31A and 31B. Here, the delay units 11 and 12 have a delay time of 1/2 chip of the spread code. Outputs E and G of multipliers 21, 31A and 31B
And F are integrated by integrators 22, 32A and 32B, respectively. The output of the integrator 22 is passed through a latch 24 to the demodulator 2.
3 and is output as received data. After the output J of the integrator 32A is synchronized with the output I of the integrator 32B by the latch 34, the absolute value circuit 33A,
The absolute value is taken at 33B. Absolute value circuits 33A, 33B
Is subtracted by the subtractor 35. Output K of subtractor 35
Is input to the loop filter 43, and a smoothed result is used as a control signal as a voltage controlled oscillator (hereinafter abbreviated as VCO).
42 is output. The VCO 42 has a reference clock CK
Is generated, and the reference clock CK is frequency-divided by the frequency divider 41, and various clocks (one chip period CK1,
1-bit period CK2) is generated. Here, the signal F,
A phase shift occurs between E and G. For despreading, integration for one cycle of the spreading code is necessary. However, in this configuration, since the spreading codes are shifted by 1/2 chip, the integrators 21, 32A, and 32B operate at different timings. There is a need. Therefore, CK1
And CK1 'with １／1 cycle shift of CK1, and CK2' with CK1's 1/2 cycle shift with respect to CK2 and CK2 and CK2 'with 1 cycle shift of CK1 with CK2 as CK2. In addition, since the timings at which the integrated values are generated vary, the integrators 22 and 32 are used to facilitate subsequent processing.
After A, it is necessary to arrange the latches 24 and 34 and adjust the timing.

In the above circuit configuration, the spreading code A is set to pn
(t), the input signal is rd (t), and the period of one chip of the spreading code A is T, the spreading code B is pn (t−T / 2),
The spreading code C is represented by pn (t-T), and the input to the loop filter 43 is represented by Expression (1).

| Σrd (t) pn (t) |-| Σrd (t) pn (tT) |...... (1) FIG. 9 to FIG. The principle is shown.

FIG. 9 shows a distribution with respect to a phase deviation as a result of integrating the result of multiplication of an input signal and a spread code.
As the characteristics of the spreading code, the maximum value is obtained without a phase deviation, the value is close to 0 when the phase is completely out of phase, and an intermediate value is shown in the range of 0 to ± 1 chip shift. Normally, as shown in FIG. 9, the value decreases almost linearly as the phase shifts.

FIG. 10 shows the phase comparison block 3 of the circuit shown in FIG.
9 shows a phase characteristic of an integrator output of 0. The peak on the right is the integrator output J when the phase deviation is +1/2, and the peak on the left is the phase deviation -1 /.
This is the integrator output I at 2 o'clock. Here, the phase deviation of +1/2 means that the spread code is advanced by 1/2 chip with respect to the demodulation signal, and the phase deviation of -1/2 is that the spread code is 1
/ 2 chips behind.

FIG. 11 shows the phase characteristics of the difference between the output of the integrator on the lag side and the output of the integrator on the lead side. The phase characteristic of the difference has an S-shaped distribution in FIG. This S-shaped difference signal is used as control information. That is, when the difference value is a negative value, the phase of the spreading code is delayed, and when the difference value is a positive value, the phase code is advanced. The phase control is performed by changing the frequency when a VCO is used. In performing the control, the difference value is considerably fluctuated by the influence of noise, and is used for control after being smoothed by the loop filter 43. By using the above-mentioned synchronization holding circuit, it is possible to generate control information corresponding to the difference between the phase of the spreading code on the transmitting side and the phase of the spreading code on the receiving side, and hold the synchronization between the spreading codes between transmission and reception. , The communication state can be maintained.

[0009]

However, in the above-mentioned conventional circuit configuration, three types of phase differences are generated for the input signal by the delay units 11 and 12 arranged on the path of the spread code on the receiving side. To perform integration for one cycle of the spreading code, a latch for timing adjustment (24, 3 in FIG. 7)
4) and CK1, CK1 ', CK2, CK2', CK
It is necessary to prepare five types of clocks of 2 ". Since a large number of clocks complicates circuit design,
It is desirable that the number is small. At the same time, additional circuits for generating these five types of clocks are required. As shown in FIG. 7, the circuit for generating the phase control signal requires that blocks 31 to 33 have a dual configuration with respect to the demodulation unit, and the circuit scale becomes large. In the field of portable communication devices and the like, miniaturization of circuits and reduction of power consumption are extremely important.

Accordingly, an object of the present invention is to realize a synchronization holding circuit which can be realized by a small-scale circuit, and in particular, to reduce the number of required clocks.

An object of the present invention is to provide a portable spread-spectrum communication device having a simple configuration, a small size, and low power consumption.

[0012]

In order to achieve the above object, the present invention provides a delay circuit for delaying an input signal by a predetermined time in a spread path, so that the phase of the input signal for demodulation is relatively shifted with respect to the phase of the input signal for demodulation. And a circuit for generating two types of control signals shifted in the above manner, the above two types of control signals are multiplied in phase by a spread code from a spread code generator for reception, and the result of the multiplication is used. A phase comparator for controlling a clock controller for controlling the phase of the spread code of the spread code generator is provided.

The preferred embodiments of the phase comparator include: (1) a subtractor for obtaining a difference between the two types of control signals at a spreading code rate, that is, a chip period; A first multiplier that multiplies the spread code from the multiplier, an integrator that integrates the multiplication result, and a multiplier that multiplies the output of the integrator by the integral value of the demodulator or the polarity code of the integral value of the demodulator. A second multiplier is provided. If the information included in the input signal is already known on the receiving side, the multiplier for multiplying the output of the integrator by the integral value of the demodulation unit or the sign of the integral value of the demodulation unit may be omitted.

In the configuration of the phase comparison unit, the order of the subtractor and the first multiplier is reversed, and the two control signals are each multiplied by the same spreading code from the spreading code generator. A configuration in which the difference between the multiplication results is integrated may be used.

As another preferred embodiment of the phase comparator, a circuit for multiplying one of the two types of control signals by −1, ie, a polarity inverting circuit, is provided in place of the subtractor.
A selector is provided for alternately switching the output of the multiplying circuit and the other control signal at twice the rate of the spreading code, and the integrator for integrating the output of the selector is operated at the selector switching speed. Is also good.

According to the above configuration, as will be described in detail in the following embodiments of the present invention, two types of clocks are required for the phase comparison block, and the frequency divider of the clock control block for generating the clock is used. The configuration can be extremely simple. Further, in the preferred embodiment of the phase comparator, the integrator can be integrated into one system, and the circuit configuration is further simplified.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION

<Embodiment 1> FIG. 1 is a block diagram showing a configuration of a first embodiment of a radio communication apparatus in spread spectrum communication according to the present invention, particularly a configuration of a synchronization holding circuit unit. FIG. 2 is a signal waveform diagram of each part in FIG.

In FIG. 1, a delay unit block 10 converts a spread spectrum input signal rd (t) into a half of a spread code.
T (T represents bits) and １ ／ to delay 1T
The delay units 11 and 12 of T are connected in series. The delay unit block 10 sends the output of the delay unit 11 to the demodulation block 20 as a demodulation signal L, and adds the input of the delay unit 11 and the output of the delay unit 12 to the phase comparison block 30 as control signals N and M, respectively.

The phase comparison block 30 generates a difference signal between the control signals N and M at the speed T of the spreading code.
5, a multiplier 31 for performing a correlation calculation between the spreading code pn (t) from the spreading code generator 50 of the receiving apparatus and the difference signal, and an output O of the multiplier 31 to one cycle SD of the spreading code. And an inverting multiplier 36 for multiplying the output P of the integrator 32 and the signal S from the demodulator 20 by using an output of the multiplier 36 as a control signal K. Send to control block 40.

The clock control block 40 divides the frequency of the output of the VCO 42, the loop filter 43 for smoothing the control signal K, the frequency of which is changed by the output of the loop filter 43, the spread code generator 50, and the delay units 11 and 1.
2. Clocks CK1, CK0, C for driving the integrator 32
It has a frequency divider 41 for generating K2.

The demodulation block 20 includes a multiplier 21 for calculating a correlation between the demodulation signal L and the spreading code pn (t), an integrator 22 for driving the output E of the multiplier 21 with clock signals CK1 and CK2, And a demodulation unit 23 for converting the output E of the demodulator 22 into reception data.

In the above circuit configuration, if the control signals N and M are represented by time functions e (t) and d (t), respectively, the outputs E and O of the multipliers 21 and 31 are c (t) pn
(T) and d (t) -e (t)) pn (t).
The outputs H and P of the integrators 22 and 32 are respectively Σ
c (t) pn (t) and Σ (d (t) -e (t)) pn (t).

Therefore, the input K to the loop filter 43 is given by equation (2).

Sgn (Σc (t) pn (t)) · Σ (d (t) -e (t)) pn (t) (integrated at t = 0 to 1 bit time) (2) sgn (x) is a function that takes the sign of x, and the signal S
Corresponds to this.

As described with reference to FIG.
Equation (3) holds because the sign of the integration result of the correlation value at the +0.5 chip shift is equal.

Sgn (Σc (t) pn (t)) = sgn (Σe (t) pn (t)) = sgn (Σd (t) pn (t)) (3) As shown in FIG. The value calculated as the input value to the loop filter 43 in the conventional configuration is shown in Expression (1), but the calculation in Expression (1) is performed instead of delaying the spreading code pn (t) instead of delaying the received signal rd (t). Is also expressed by Expression (4).

| Σrd (t) pn (t) |-| Σrd (t) pn (tT) | = | Σrd (tT) pn (t) |-| Σrd (t) pn (t) | = | Σd ( t) pn (t) |-| Σe (t) pn (t) | ……………………………………………………………………………………………………………………………………………… (4) Is equal to the operation of squaring, so equation (4) can be expressed by equation (5) from the relationship of equation (3).

| Σd (t) pn (t) |-| Σe (t) pn (t) | = sgn (Σd (t) pn (t)) Σd (t) pn (t) -sgn (gne (t ) pn (t)) Σe (t) pn (t) = sgn (Σc (t) pn (t)) (Σd (t) pn (t)-Σe (t) pn (t)) = sgn (Σc ( t) pn (t)) (Σd (t) -Σe (t)) pn (t) (5) Equation (5) is equal to equation (2), The phase comparison in the embodiment of the present invention has the same result as the phase comparison of the conventional circuit shown in FIG. 5, so that a predetermined phase synchronization holding control can be performed.

In this embodiment, only CK0, CK1, and CK2 whose clock numbers are phase-synchronized are required, and the phase comparator 30 has a simple configuration of one of the circuits 35, 31, 32, and 36. Further, there is an advantage that the subtraction circuit 35 is constituted by a circuit having a small number of bits because it is located before the integrator 32. Therefore, the required power is reduced as compared with the conventional circuit.

<Embodiment 2> Although this embodiment is not shown in the drawings, the demodulation block 20 shown in FIG.
And the multiplier 36 are omitted. This embodiment is applied to a case where a line on which no data is carried is used for synchronization between a base station and a terminal in a radio base station in a portable mobile radio service. That is, assuming that "1" or "0" is all transmitted,
Sgn (Σc (t) pn (t)) in equation (2) is “1” or “−1”
Is always constant. That is, since it is easy to know the value of sgn (pnc (t) pn (t)) in advance, the demodulation block 20 and the multiplier 36 are not required, and a circuit can be configured more easily.

<Third Embodiment> FIG. 3 shows a circuit configuration of a phase comparison block 30 of another embodiment of the synchronization holding circuit according to the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals.

The two types of control signals N and M are multiplied by spreading codes pn (t) by multipliers 31-1 and 31-2, respectively, and then subtracted by a subtractor 35. Subtractor 3
The processing circuit after the output of 5 is the same as in FIG.

<Embodiment 4> FIG. 4 shows a circuit configuration of a phase comparison block 30 of still another embodiment of the synchronization holding circuit according to the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals.

One of the two control signals N and M is applied to a coefficient unit 37 (which may be an inverter) which multiplies one control signal N by −1, and the output of the coefficient unit 37 and another control signal M
Are alternately switched by a selector 38 that switches at twice the rate of the spreading code, that is, at a half chip period, and is added to the integrator 32 that operates at the switching speed CKO of the selector 38.

<Embodiment 5> FIG. 5 is a block diagram showing an embodiment of a wireless communication apparatus according to the present invention. This embodiment is used for spread spectrum communication, has a synchronization holding circuit of the present invention, and employs synchronous detection as a detection method.

The transmission data is modulated by a spread code in a modulation block 72, and the output of the modulation block 72 is multiplied by a carrier generated by a local oscillator 82 of a carrier circuit 80 in a frequency converter 81 and then passed through a splitter 71. Is transmitted from the antenna 70. The input signal received by the antenna 70 passes through the splitter 71, is multiplied by the carrier recovered by the carrier recovery circuit (Phase Lock Loop, abbreviated as PLL) 84 by the frequency converter 83, and is synchronously detected. The signal after the detection is sent to the demodulation block 73.
“1” and “0” are determined and output as received data. On the other hand, the same received signal is input to the synchronization holding block 60. As the synchronization holding block 60, the synchronization holding circuit having the delay block 10, the phase comparison block 30, the clock control block 40, and the spreading code generator 50 shown in FIG. 1 is used.

<Embodiment 6> FIG. 6 is a block diagram showing a configuration of another embodiment of the wireless communication apparatus according to the present invention.
The present embodiment is used for spread spectrum communication, has the synchronization holding circuit of the present invention, and uses an asynchronous detection (delay detection) method as a detection method.

The transmission data is transmitted in the same manner as in the example of FIG. The received signal received by the antenna 70
1 and is input to the carrier wave unit 80. The received signal is
Multipliers 83A and 83B multiply the carrier generated by local oscillator 82B. Here, the carrier multiplied by the multiplier 83B passes through the phase shifter 84, and is
Since the phase is shifted by π / 2 with respect to the carrier multiplied in 3A, the received signal is divided into two orthogonal components of an I component and a Q component. In the demodulation unit 73, I · Q 2
A demodulated signal is generated based on the signal by delay detection processing and output as received data. On the other hand, the same received signal is input to the synchronization holding block 60, and after generating a phase comparison signal for each of the signal components I and Q, the adder 61 adds the signals to perform phase control.

Although the embodiment of the present invention has been described above, it is apparent that the present invention is not limited to the above embodiment. For example, in the embodiments of FIGS. 3 and 4, the case where the sign inverting multiplier 36 is used has been described.
As described above, the multiplier 36 may be omitted.

Further, although the effect of reducing the circuit scale is slightly reduced, a multiplier with a spreading code and an integrator for integrating the output of the multiplier are provided for each of the two control signals N and M, and the control signals N and M are provided. The configuration in which the subtraction output of the two integrators of M is used as the control signal K of 40 of the clock control group also reduces the number of required clocks and eliminates the need for a latch circuit for delay adjustment, and is included in the present invention. .

[0041]

According to the conventional synchronization holding circuit, the spread code generated in the receiving section is delayed, so that it is necessary to insert a delay circuit at a signal passing point to adjust the timing.
According to the circuit configuration of the present invention, no deviation occurs between the two control signals. Therefore, a latch circuit and an extra clock generation circuit for adjusting the timing at various points on the signal line become unnecessary, and the circuit design can be simplified. That is,
In the synchronization holding circuit of the present invention, since the integrators need only operate at the same timing, only two clocks, CK1 and CK2, need be prepared as operation clocks. Further, compared with the conventional example, a latch circuit for adjusting timing at various points on the signal line and a generation circuit for CK1 ', CK2', CK2 "are not required. These circuits operate at a relatively high speed in the whole. Therefore, the effect of reducing power consumption is great.

Further, since the processing circuit for comparing the phase of the conventional circuit is changed from a two-stage configuration to a one-stage configuration, the circuit scale is approximately one.
/ 2, and the absolute value circuits 33A and 33B become unnecessary. Further, in the embodiment in which the subtractor 31 is provided on the input side of the integrator 32, the number of operation bits can be reduced.

Also, according to the embodiment of FIGS. 1 and 4,
The scale of the control signal generation circuit is reduced to approximately ２, and the circuit scale can be significantly reduced. Further, since the operating frequency does not increase at the same time, power consumption can be reduced at the same time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a synchronization holding circuit according to the present invention.

FIG. 2 is a diagram showing signals in a main part of the synchronization holding circuit in FIG. 1;

FIG. 3 is a block diagram showing a configuration of a third embodiment of the synchronization holding circuit according to the present invention.

FIG. 4 is a block diagram showing a configuration of a fourth embodiment of the synchronization holding circuit according to the present invention.

FIG. 5 is a block diagram showing a configuration of one embodiment of a wireless communication device according to the present invention.

FIG. 6 is a block diagram showing a configuration of another embodiment of the wireless communication apparatus according to the present invention.

FIG. 7 is a block diagram showing a configuration of a conventional synchronization holding circuit.

8 is a diagram showing signals at respective points in the conventional synchronization holding circuit of FIG. 7;

FIG. 9 is a diagram showing a correlation value with respect to a phase deviation of a spread code obtained as a result of multiplying a signal transmitted by spread spectrum and a spread code prepared on a receiving side and integrating the result;

FIG. 10 is a phase characteristic diagram of an integrator output in a phase comparison unit of the synchronization holding circuit in FIG. 7;

FIG. 11 is a phase characteristic diagram of a control signal generated in a phase comparison unit of the synchronization holding circuit in FIG. 7;

[Explanation of symbols]

10: delay block, 20: demodulation block, 30: phase comparison block, 40: clock control block including loop filter / VCO / frequency divider, 50: spreading code generator, 60: control signal generation block, 70: antenna , 7
1: duplexer, 80: carrier circuit, 11 to 13: delayer,
21 ・ 31A ・ 31B: Multiplier of spread code and received signal, 22 ・ 32A ・ 32B: Integrator, 23: Demodulator, 3
3A / 33B: Absolute value circuit, 35: Adder, 24.3
4: Latch, 36: Sign inverting multiplier, 44A / 44B
44C: frequency divider, 81/83: frequency converter, 8
2: local oscillator, 84: phase shifter.

Claims (7)

[Claims] 1. A synchronization holding circuit for holding phase synchronization between a first spreading code included in an input signal and a second spreading code generated in a receiving device, wherein the second spreading code is provided. A spread code generator for generating a code; a clock control unit for controlling the phase of the spread code generator; a delay unit for delaying the input signal by 1/2 bit and 1 bit of the spread code; A phase comparator for inputting the bit-delayed delay signal as the first and second control signals, multiplying by the second spreading code, and generating a third control signal for controlling the clock controller; A synchronization holding circuit in spread spectrum communication. 2. A subtraction circuit, wherein said phase comparison section generates a difference signal between said first and second control signals at a speed of a spreading code, and a correlation between said second spreading code and said difference signal. A loop filter having a multiplier for performing calculation, an integrator for integrating the output of the multiplier to generate the third control signal, wherein the clock control unit smoothes the third control signal; 2. The synchronization holding circuit according to claim 1, further comprising an oscillator for changing a frequency by an output of the filter, and a frequency divider for dividing an output of the oscillator and controlling at least a phase of the second spreading code. 3. A multiplier for calculating a correlation between the first and second control signals and the second spreading code by the phase comparator, and a difference between outputs of the two multipliers. A loop filter for smoothing the third control signal, wherein the clock control unit has a subtraction circuit for obtaining a signal, an integrator for integrating the difference signal to generate the third control signal, 2. An oscillator for changing a frequency by an output, and a frequency divider for dividing an output of the oscillator and controlling at least a phase of the second spreading code.
Synchronous holding circuit as described. 4. A circuit for inverting one polarity of the first and second control signals, wherein the phase comparison unit converts the control signal having the inverted polarity and the other control signal into a spread code rate of 2. A selector for alternately switching and outputting at twice the speed; and an integrator for integrating the output of the selector at the switching speed of the selector to generate the third control signal. A loop filter for smoothing a control signal, an oscillator for changing the frequency with an output of the loop filter, and a frequency divider for dividing the output of the oscillator and controlling at least the phase of the second spreading code. The synchronization holding circuit according to claim 1. 5. The synchronization holding circuit according to claim 2, wherein the delay signal is multiplied by a signal obtained by delaying an input signal by 1/2 bit of a spread code by the second spread code. A synchronization inverting multiplier for multiplying a signal obtained by integrating the signal with an output of the integrator, wherein an output of the polarity inverting multiplier is used as the third control signal; Holding circuit. 6. A radio communication apparatus for spread spectrum communication having a receiving section and a receiving section, wherein the receiving section includes: a synchronous detection circuit; and a demodulation block for demodulating received data from an output of the synchronous detection circuit. 7. A spread code generator used for the demodulation block, and a control signal for controlling a phase of the second spread code using an output of the synchronous detection circuit unit is added to the spread code generator. A wireless communication device, comprising: the synchronization holding circuit according to any one of the above. 7. A wireless communication apparatus for spread spectrum communication having a receiving unit and a receiving unit, wherein the receiving unit obtains two orthogonal components of an I component and a Q component.
A demodulation block for demodulating received data from an output of the asynchronous detection circuit; a spreading code generator used for the demodulation block; and a spreading code generator for each of the I component and the Q component output from the asynchronous detection circuit. 7. A radio communication apparatus comprising: the synchronization maintaining circuit according to claim 1, wherein a control signal for controlling a phase of a spread code of a transmitter is added to the spread code generator.