JPH0998368A - Video signal phase correction device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a video image with high image quality even in the case of a non-standard signal at reproduction of a VTR by processing various signals with an optimum clock signal suitable for a standard signal and a non-standard signal when either of them is received. SOLUTION: A burst lock clock generating means 5 and a write reset signal generating means 6 write a video signal sampled by a burst lock clock to a memory 7, a line lock clock generating means 9 and a read reset signal generating means 10 apply time base conversion to the written signal at a line lock clock rate and a video data phase correction means 11 corrects the phase. Thus, the burst lock clock required for Y/C separation and color demodulation and the line lock clock required for signal processing such as wide conversion processing are used to conduct respective processing and high image quality video image is reproduced independently of a standard/a non-standard input video signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device for a television receiver, and more particularly to a video signal for processing a non-standard signal such as a VTR reproduction signal in a digital television receiver for digital signal processing. The present invention relates to a phase correction device.

[0002]

2. Description of the Related Art Conventionally, in a digital television receiver (hereinafter abbreviated as digital TV), a burst lock clock signal locked to a color burst signal or a horizontal sync signal is used as a synchronous system clock signal for signal processing for high image quality reproduction. Two types of system clock signals have been considered, line locked clock signals locked to signals. For that purpose, the synchronous reproduction circuit reproduces a stable synchronous reproduction signal based on the burst lock clock signal or the line lock clock signal, and the signal processing circuit inputs the clock signal to process the video signal for high image quality. Was being given.

As described above, two types of system clock signals are considered in the case of a standard signal such as a broadcast wave and the case of a non-standard signal such as a reproduction signal of a VTR. This is because the optimum clock signal to be supplied to the process is different. For example, separation of luminance signal and color signal,
It is desirable that the system clock signal of the color demodulation unit be synchronized with the color subcarrier. Therefore, in this case, a very stable burst lock clock signal may be used for both standard and non-standard input video signals.

On the other hand, it is desirable that the system clock signal for signal processing including line interpolation processing such as wide conversion and progressive scanning line conversion is synchronized with the horizontal synchronizing signal and the vertical synchronizing signal. Therefore, in this case, the line lock clock signal is used especially in the non-standard signal mode in which there is a lot of jitter in the horizontal direction like the VTR reproduction signal.

When the above technique is applied to an actual digital TV, in the signal processing from the A / D converter to the D / A converter, all system clock signals are burst lock clock signals at the standard signal, When the standard signal is used, the reproduced image is processed by switching to the line lock clock signal and used, or by selectively using the above two system clock signals by signal processing.

Incidentally, as a conventional system of a synchronization processing circuit for a non-standard signal in a digital TV, for example, there is a "television receiver" described in JP-A-64-89791. To be

[0007]

By the way, in the above prior art, the sampling clock signal of the A / D converter for the signal processing of the television receiver is used in the Y / C separation circuit and the color demodulation circuit succeeding to the next stage. A burst lock clock signal is usually used to match the system clock signal.

Therefore, even if the data sampled by the burst lock clock signal is supplied to the wide conversion processing circuit including the scanning line processing in the subsequent stage, the data is basically synchronized with the line lock clock signal. Since it does not exist, the reproduced image has a phase shift, and horizontal vibration occurs in the horizontal direction of the screen. This effect becomes remarkable when the burst lock clock signal and the line lock clock signal have a non-standard signal in which a frequency difference occurs, resulting in image deterioration.

The object of the present invention is to solve the above problems and to process various signals with an optimum clock signal suitable for both standard and non-standard signal input.
It is an object of the present invention to realize a video signal phase correction device for a television receiver that can obtain a high quality image even with a non-standard signal during R reproduction.

[0010]

In order to achieve the above object, the present invention is configured as follows. In a video signal phase correction device, means for separating and extracting a horizontal synchronizing signal and a color burst signal included in an input video signal, and a first clock signal of a predetermined frequency synchronized with the color burst signal and a predetermined frequency synchronized with the horizontal synchronizing signal. Means for generating the second clock signal, means for sampling the input video signal with the first clock signal, and the video signal sampled by the sampling means is written with the first clock signal, and The memory means read by the clock signal and the horizontal synchronizing signal are synchronized with the first clock signal, and the means for resetting the writing of the memory means is synchronized with the horizontal synchronizing signal with the second clock signal. Memory read, which is delayed by a predetermined time from the write reset timing based on the converted signal. Provided to the reset timing, and means for resetting read the memory means, the data read from the memory means, and means for phase correction according to the phase variation amount of the horizontal synchronizing signal.

Preferably, in the above-mentioned video signal phase correction apparatus, the phase correction means detects the phase fluctuation amount of the horizontal synchronizing signal from the standard signal time every horizontal cycle period, and the detected phase. Generating means for calculating an average phase difference of one sampling unit based on the variation, means for cumulatively adding the calculated average phase difference, means for generating a linear interpolation coefficient based on the cumulatively added data, Means for linearly interpolating the read data from the memory means in units of the second clock signal using the generated interpolation coefficient.

Further, preferably, in the above video signal phase correction apparatus, the means for resetting the writing of the memory means is at the same timing as the phase fluctuation amount detection in the phase fluctuation amount detection means of the phase correction means, and the first Generates a timing signal synchronized with the clock signal of.

Further, preferably, in the above-mentioned video signal phase correction apparatus, the phase correction means has a period variation amount for each horizontal period measured at a period of the first clock signal with reference to a predetermined position of the horizontal synchronizing signal. Is detected to detect the amount of phase fluctuation. Further, preferably, in the video signal phase correction apparatus, the predetermined position of the horizontal synchronizing signal is a predetermined position of a front edge portion or a rear edge portion of the horizontal synchronizing signal.

In the separating / extracting means, the horizontal synchronizing signal and the color burst signal are separated from the input video signal. The first and second clock signal generation means respectively generate a clock signal of a predetermined frequency (four times the frequency of the normal subcarrier) synchronized with the color burst signal and a clock signal synchronized with the horizontal synchronization signal of the same frequency. . In the memory means, the data sampled by the first clock signal is time-axis converted into the data sampled by the second clock signal.

Further, the write reset of the memory is
The write reset is performed by a signal from the means, which is based on a signal obtained by synchronizing the horizontal sync separation signal with the first clock signal. The memory read reset is performed by a signal from the read reset means, which is based on a signal obtained by synchronizing the horizontal sync separation signal with the second clock signal.

Further, the second clock signal read data from the memory is phase-corrected by the phase correction means in accordance with the phase fluctuation of the horizontal synchronizing signal, and is an image having a uniform phase in the horizontal direction on the reproduction screen. Output. Also,
The phase amount detecting means in the phase correcting means detects the time base fluctuation of the edge portion of the horizontal synchronizing signal. The average phase difference data cumulative addition means calculates an average phase difference for each unit sample (1 clock) based on the detected phase difference data, and cumulatively adds it every time the second clock signal is input. The linear interpolation coefficient generating means generates an interpolation coefficient used in the subsequent linear interpolation processing based on the cumulative addition data. The linear interpolation means uses this interpolation coefficient to compare the data from the memory with 1
Interpolation calculation is performed using the clock-delayed data and converted into the rate of the second clock signal, and the phase-corrected video signal is output.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a schematic configuration diagram of a digital video signal processing device to which an embodiment of the present invention is applied. In the figure, 1 is a video signal input terminal, 2 is an A / D converter, and 3 is a video signal processing circuit, which performs, for example, Y / C separation processing. Reference numeral 4 is a burst signal extraction circuit, 5 is a burst signal system PLL, 6 is a memory write reset signal forming circuit, which will be described later, 7 is a memory, 8 is a sync signal separating circuit, and 9 is a memory.
Is a line system PLL, and 10 is a read reset signal forming circuit of the memory 7.

Reference numeral 11 is a phase correction circuit, and 12 is a video signal processing circuit, which performs, for example, wide conversion processing. Reference numeral 13 is a D / A converter, 14, 38 and 39 are video signal output terminals, and 35 is a color demodulation circuit. 36 and 37 are
Shows a signal processing circuit, each of which is
The circuit has the same configuration as the circuit 40 surrounded by the broken line in FIG.

That is, the signal processing circuit 36, like the memory 7, outputs a burst lock clock signal BCK, a line lock clock signal LCK, a memory to which the color difference signal BY is supplied, and an output signal from this memory. The supplied phase correction circuit (similar to the phase correction circuit 11), the video processing circuit (similar to the video processing circuit 12), and the D / A converter (D
/ A converter 13).

Similarly to the memory 7, the signal processing circuit 37 is similar to the signal processing circuit 36 and a memory to which the burst lock clock signal BCK, the line lock clock signal LCK and the color difference signal RY are supplied. , A phase correction circuit, a video processing circuit, and a D / A converter.

Next, the operation of the apparatus shown in FIG. 1 will be described. The analog composite video signal input to the input terminal 1 is input to the A / D converter 2 and the sync signal separation circuit 8. The A / D converter 2 converts an analog video signal into a digital signal. The sync signal separation circuit 8 separates the horizontal / vertical sync signal from the composite video signal and inputs only the horizontal sync signal Hsync to the reset signal forming circuits 6 and 10, the line PLL circuit 9, and the phase correction circuit 11. To do.

The digital video signal from the A / D converter 2 is input to the video signal processing circuit 3 and the burst signal extraction circuit 4, and the video signal processing circuit 3 separates the composite video signal into a Y signal and a C signal. Then, the burst signal extraction circuit 4 extracts the burst signal from the video signal. The Y signal from the video signal processing circuit 3 is input to the memory 7, and the C signal is input to the color demodulation circuit 35.

Based on the burst signal, the burst system PLL circuit 5 generates a first system clock signal (burst lock clock signal) BCK and a reproduction subcarrier signal SC which are synchronized with the burst signal. Then, the clock signal BCK is supplied to the A / D converter 2, the video signal processing circuit 3, the write reset signal forming circuit 6, the memory 7, and the phase correction circuit 11.

The frequency of the system clock signal BCK is
Usually, the frequency is 4fsc, which is four times the subcarrier frequency fsc. The A / D converter 2 uses the clock signal BCK as a sampling clock signal. Further, the signal processing circuit 3 performs Y / C separation by three-dimensionally filtering using a frame comb filter or the like. The burst signal extraction circuit 4 extracts a burst signal included in the video signal using a 3.58 MHz bandpass filter or the like.

Further, in the line system PLL circuit 9,
Based on the horizontal synchronizing signal Hsync from the synchronizing signal separation circuit 8, a second system clock signal (line lock clock signal) LCK synchronized with this is generated. The system clock signal LCK is supplied to the memory 7, the read reset signal forming circuit 10, the phase correction circuit 11, the video signal processing circuit 12, and the D / A converter 13.

Next, in the write reset signal forming circuit 6, the write reset signal WR of the memory 7 is generated by the timing signal Ts from the phase correction circuit 11 based on the horizontal synchronizing signal Hsync synchronized with the burst lock clock signal BCK. That is, a timing signal is generated at the same timing as the phase fluctuation amount detection in the phase correction circuit 11 and in synchronization with the burst lock clock signal BCK, and the write data address of the memory 7 is reset. The read reset signal forming circuit 10 generates the read reset signal RR of the memory 7 delayed by the write reset signal WR for a predetermined time based on the horizontal synchronizing signal Hsync synchronized with the line lock clock signal LCK, and reads the memory 7. Reset the data address.

The relationship between the write / read address reset signal and the horizontal synchronizing signal and clock signal is shown in FIGS. FIG. 2 shows a synchronizing signal Hsync and a clock signal B.
The timing of CK and the reset signal WR is shown. The synchronization signal Hsync and the clock signal BCK are asynchronous, and the memory write reset signals created when the burst lock clock signal is BCK1 and BCK2 with respect to the synchronization signal Hsunc are WR1 and WR2 as shown in the figure. The case of occurs. Therefore, as shown in the figure, the write reset signal WR causes a phase shift of at most one clock difference with respect to the synchronization signal.

FIG. 3 shows the timings of the synchronization signal Hsync, the clock signal LCK and the read reset signal RR. The synchronization signal Hsync and the clock signal LCK are PL
Since the L circuit 9 is synchronized, the read reset signal RR is also synchronized with the horizontal synchronization signal Hsync as shown in the figure. However, the signal RR is delayed from the horizontal synchronizing signal Hsync by a predetermined time τr.

The purpose of using the memory 7 is to resample the Y signal sampled with the clock signal BCK from the video processing circuit 3 with the clock signal LCK asynchronous with the clock signal BCK, and This is for time-axis conversion into the rate of the lock clock signal LCK. This is particularly effective when a frequency difference occurs between the burst lock clock signal BCK and the line lock clock signal LCK like a VTR reproduction signal.

Here, the delay time τr may be such that the jitters of the clock signals BCK and LCK can be absorbed.
A time period of 00 ns to 1 horizontal cycle is appropriate. Also,
The write clock signal WCK in the memory 7 is the burst lock clock signal BCK and the read clock signal R
The line lock clock signal LCK is used as CK.

The Y signal data converted from the clock signal BCK to the rate of the clock signal LCK in the memory 7 is next input to the phase correction circuit 11, and the phase of the signal level is changed according to the time-axis fluctuation amount of the data. Correction is performed. This operation will be described later. In addition, the phase correction circuit 11
Then, the timing signal Ts for forming the reset signals WR and RR of the memory 7 is input to the reset signal generation circuits 6 and 10.

The Y signal completely phase-corrected at the rate of the line lock clock signal LCK by the phase correction circuit 11 is input to the video signal processing circuit 12. Here, for example, based on the line lock clock signal LCK, processing such as wide conversion including processing processing in scanning line units is performed.
The Y signal after wide conversion is the system clock signal LCK
D / A conversion is performed by the D / A converter 13 based on
4 is output.

The color demodulation circuit 35 described above demodulates the color difference signals BY and RY from the input C signal,
Input to the signal processing circuits 36 and 37, respectively. As described above, the signal processing circuits 36 and 37 are circuits equivalent to the broken line portion 40, and the color difference signals BY and RY sampled by the burst lock clock signal BCK are sampled by the line lock clock signal LCK. After converting to data, phase correction, wide conversion processing, D / A
The data is converted and output to the output terminals 38 and 39, respectively.

FIG. 4 shows a line lock clock signal LCK for video data sampled by the burst lock clock signal BCK in the phase correction circuit 11 described above.
Necessary to convert and correct the phase sampled by
It shows a method of detecting a phase error caused by a time base fluctuation of the horizontal synchronizing signal Hsync.

In FIG. 4, continuous horizontal synchronizing signal H
Level differences L1, L2, L3, L with respect to successive burst lock clock sample points (black circles in the figure) sandwiching a predetermined fixed threshold level L at the trailing edges of H1 and H2.
Measure 4. As a result, the phase change X of the horizontal synchronizing signal
l−1 and Xl are respectively Xl−1 = Tc × L1 / L
2, Xl = Tc × L3 / L4.

Here, Tc is 1 sampling period 1 /
4 fsc (sec), that is, It is about 70 nsec. The values of the phase changes Xl and Xl-1 represent the phase difference within one clock during one cycle of the horizontal synchronizing signal. Further, Yl in FIG. 4 is a count value of the burst lock clock signal in one horizontal period, and for a phase difference of 1 clock signal or more, the clock count value is 9 in one horizontal cycle period of the standard signal.
Since the number is 10, the number becomes Y1-910.

Therefore, the total phase difference is (Y1-910).
+ X1-X1-1), and the phase difference of one sample period average is (Y1-910 + X1-X1-l) / 910. Therefore, when the phase correction of the video signal in the next one horizontal cycle period is performed based on the phase difference, the correction amount for each sample is Z = Xl + n × in consideration of the initial phase Xl.
It becomes (Y1-910 + X1-X1-1) / 910.

Here, n increases to 1, 2, 3, ... For each sample (clock). Based on the average phase difference data per sample, the phase correction circuit 11 corrects the phase of the data sampled by the burst lock clock signal BCK. The signal T shown at the bottom of FIG.
s, WR, and RR are timing waveform diagrams of the memory reset reference signal, the write reset signal of the memory 7, and the read reset signal described in FIG. 1, respectively. The reset signals WR and RR are generated based on the signal Ts.

As described with reference to FIG. 2, the write reset signal WR is at most 1 with respect to the input horizontal synchronizing signal Hsync.
Since there is a clock phase difference, the data error after reading due to the memory write timing error is output in synchronization with the phase difference detection timing of the front and rear edges of the horizontal synchronization signal so that the phase correction circuit 11 in the subsequent stage can correct it. To do. By doing so, as described above, since the data is written in the memory based on the phase corresponding to the time base fluctuation of the horizontal synchronizing signal, the phase error from the standard signal state can be corrected by the phase difference detection value.

In the example shown in FIG. 4, the phase error is detected at the trailing edge of the horizontal sync signal. However, if the phase error is detected using the leading edge of the sync signal, the same phase error is detected. Correction is possible. Further, in the example of FIG. 4, the method of measuring the period of the horizontal synchronizing signal one-dimensionally and obtaining the amount of phase fluctuation thereof is shown. However, in addition to this, the area change of the negative polarity area of the horizontal synchronizing signal Is also applicable to the present invention.

FIG. 5 is a block diagram of a circuit example of the phase correction circuit 11 according to the phase difference detection method shown in FIG.
In FIG. 5, 15 is a burst lock clock signal BC
Input terminal for sample video (Y) signal by K, 16 for horizontal sync signal Hsync, 17 for burst lock clock signal BCK, and 18 for timing signal T
s output terminal, 19 is an average phase difference data calculation circuit, 20
Is an input terminal of the line lock clock signal LCK.
Further, 21 is a cumulative adder, 22 is an OR circuit, 23 is a decoding circuit, 24 is a coefficient generation ROM, 25 is a linear interpolation circuit, and 26 is an output terminal of a video (Y) signal after phase correction.

Next, the operation will be described. As described above, the phase difference data calculation circuit 19 detects the frequency / phase shift of the horizontal synchronizing signal during one period, and calculates the average phase difference data for each sample based on the detected frequency / phase shift. The phase difference data calculation circuit 19 outputs the timing signal Ts for generating the reset signals WR and RR of the memory 7 to the terminal 18. This timing signal Ts is input to the timing signal generation circuits 6 and 10 of FIG.

The average phase difference data Z from the phase data calculation circuit 19 is input to a cumulative adder 21 where the average phase difference data Z is cumulatively added for each sample (clock signal LCK unit). That is, the accumulated phase difference data Z is, as described above, Z = X1 + n × (Y1-910 + X1-X).
l-1) / 910 (n = 0, 1, 2, 3 ...).

The maximum value of this cumulative addition value is when the coefficient value k for linear interpolation, which will be described later, becomes 1, and the decoding circuit 23 detects it. Then, the maximum value decode detection signal and the horizontal synchronizing signal Hsy output from the decoding circuit 23.
With nc, the cumulative adder 21 is reset via the OR circuit 22. This cumulative adder 21 controls the horizontal sync signal Hsync.
When reset by, the cumulative addition is restarted based on the next new phase difference data.

When the cumulative adder 21 is reset by the maximum value decode detection signal from the decoding circuit 23, the cumulative addition is continued again based on the previous phase difference data. The cumulative addition data from the cumulative adder 21 is input to the coefficient generation ROM 24, and the coefficients k, 1- for linear interpolation are input.
k is generated from the coefficient generation ROM 24 for each line lock clock signal. Next, according to the coefficient value generated from the coefficient generation ROM 24, the linear interpolation circuit 25 receives the terminal 27.
The video signal sampled by the line lock clock signal LCK from the
Each K is linearly interpolated and output to the video signal processing circuit 12 via the terminal 26.

FIG. 6 shows an example of the configuration of the linear interpolation circuit 25. In FIG. 6, 28 is a one-sample delay circuit, 29 and 30 are multipliers, and 31 and 32 are coefficient generation R, respectively.
Input terminals for coefficient data k and 1-k from OM24, 3
3 is an adder. The data sampled by the line lock clock signal LCK from the terminal 27 (read data of the memory 7) is multiplied by the coefficient k in the multiplier 29. Further, the data sampled by the line lock clock signal LCK delayed by one sample in the delay circuit 28 is multiplied by the coefficient 1-k in the multiplier 30. Then, the multiplication outputs from these two multipliers 29 and 30 are added by the adder 33 and output to the video signal processing circuit 12 via the terminal 26.

FIG. 7 shows a state of the linear interpolation operation described above. That is, in FIG. 7, a clock signal BCK and a clock signal are generated from two consecutive video signals (In + 1, In + 1, In + 2, ...) At the burst lock clock sample points indicated by black circles. By using the linear interpolation coefficients k and 1-k corresponding to the phase difference from LCK, the sampling points (On, On + 1, On + 2, ...) By the line lock clock signal LCK indicated by white circles are newly determined. Generate interpolation. At this time, On = k × (In + 1) + (1-k)
× In.

FIGS. 8, 9, 10 and 11 are diagrams for supplementarily explaining the operation and effect of the phase correction apparatus according to the present invention. FIG. 8 shows the timing of write data to the memory 7 and the number of data with respect to the synchronization signal Hsync, the non-standard input signal, the burst lock clock signal BCK, and the write reset signal WR. As shown in the figure, the write video data is the synchronization signal Hsync.
On the other hand, the phase is shifted by ΔX.

Furthermore, since the input signal is a non-standard signal,
Here, for example, a case is shown in which the rate of the clock signal BCK is one more (Δy on the time axis) than the standard value 910 (Tn on the time axis) in one horizontal synchronization period. Therefore, when this data is simply read out and reproduced, the image sample points are shifted obliquely with respect to the horizontal direction of the screen as shown in FIG. In order to eliminate such a problem, the phase / frequency shift of the write data in FIG. 8 is corrected as described in FIGS. 4 and 5 above.

FIG. 9 shows image data after phase correction,
The state of the line lock clock signal LCK for the reproduction horizontal synchronizing signal HD and the image data resampled by this clock signal LCK and subjected to phase correction to be 910 pieces in one horizontal period is shown. FIG. 11 shows a reproduced image after the phase correction shown in FIG. 9, and is an image having a uniform phase in the horizontal direction. Note that the above phase correction processing is performed by the circuit 4 for each of the Y signal, the BY signal, and the RY signal.
This is performed by the phase correction circuit in 0, 36 and 37.

[0051]

Since the present invention is configured as described above, it has the following effects. In the television receiver, it is possible to perform signal processing with an optimum clock regardless of the standard / non-standard signal of the input video signal. For example, Y /
Burst lock clock signal required for C separation and color demodulation,
Each processing can be performed by a line lock clock signal necessary for signal processing including scanning line processing such as wide conversion processing, and V
It is possible to realize a video signal phase correction device capable of reproducing high quality video even when a non-standard signal is input as in TR reproduction.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a digital video signal signal device to which a video signal phase correction device according to an embodiment of the present invention is applied.

FIG. 2 is a waveform diagram of a write reset signal of the memory in the example of FIG.

FIG. 3 shows a waveform diagram of a read reset signal of the memory in the example of FIG.

4 is a diagram showing a phase error detection method in the phase correction circuit of the example of FIG.

5 is a diagram showing a configuration example of a phase correction circuit of the example of FIG.

6 is a diagram showing a configuration example of a linear interpolation circuit of the example of FIG.

FIG. 7 is a diagram for explaining the operation of the linear interpolation circuit of the example of FIG.

FIG. 8 is an operation explanatory diagram in the case where phase correction is not performed for a non-standard signal.

FIG. 9 is an operation explanatory diagram when phase correction is performed for a non-standard signal.

FIG. 10 is a diagram illustrating image sample points when phase correction is not performed for non-standard signals.

FIG. 11 is a diagram illustrating image sample points when phase correction is performed on a nonstandard signal.

[Explanation of Codes] 2 A / D Converter 3 Video Signal Processing Circuit 4 Burst Signal Extraction Circuit 5 Burst System PLL Circuit 6 Write Reset Signal Generation Circuit 7 Memory 8 Synchronous Signal Separation Circuit 9 Line System PLL Circuit 10 Read Reset Signal Generation Circuit 11 Phase Correction Circuit 12 Video Signal Processing Circuit 13 D / A Converter 19 Phase Difference Data Calculation Circuit 21 Cumulative Adder 22 OR Circuit 23 Decoding Circuit 24 Coefficient Generation ROM 25 Linear Interpolation Circuit 28 1 Sample Delay Circuit 29, 30 Multiplier 33 Adder 35 Color demodulation circuit 36, 37 Signal processing circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukumi Saeki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Multimedia system development headquarters (72) Inventor Takashi Furuhata Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa 292 Hitachi, Ltd.Multimedia Systems Development Headquarters (72) Inventor Ichio Nakagawa Yoshidacho, Totsuka-ku, Yokohama, Kanagawa 292 Address Hitachi Ltd. Multimedia Systems Development Headquarters (72) Inventor Toshinori Murata 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Multimedia system development headquarters

Claims (6)

[Claims] 1. A means for separating and extracting a horizontal sync signal and a color burst signal included in an input video signal, a first clock signal having a predetermined frequency synchronized with the color burst signal, and a predetermined frequency synchronized with the horizontal sync signal. Means for generating a second clock signal, a means for sampling the input video signal with the first clock signal, a video signal sampled by the sampling means is written with the first clock signal, and Memory means read by the second clock signal, means for resetting the writing of the memory means based on a signal obtained by synchronizing the horizontal synchronizing signal with the first clock signal, and the horizontal synchronizing signal. , The write reset timing is based on the signal synchronized with the second clock signal. Means for performing read reset of the memory means at a memory read reset timing delayed by a fixed time; means for phase correcting read data from the memory means according to the amount of phase fluctuation of the horizontal synchronizing signal; A video signal phase correction device comprising: 2. The video signal phase correction device according to claim 1, wherein the phase correction means detects a phase fluctuation amount of the horizontal synchronizing signal from a standard signal time every horizontal period. A means for calculating an average phase difference in one sampling unit based on the detected phase fluctuation amount, a means for cumulatively adding the calculated average phase difference, and a linear interpolation coefficient is generated based on the cumulatively added data. And a means for linearly interpolating the read data from the memory means in units of the second clock signal by using the generated interpolation coefficient. 3. The video signal phase correction apparatus according to claim 2, wherein the means for resetting the writing of the memory means has the same timing as the phase fluctuation amount detection in the phase fluctuation amount detection means of the phase correction means, And the above first
A video signal phase correction apparatus, which generates a timing signal synchronized with the clock signal. 4. The video signal phase correction apparatus according to claim 2, wherein the phase correction means measures at the cycle of the first clock signal with reference to a predetermined position of the horizontal synchronizing signal.
A video signal phase correction device, characterized in that it detects a period variation amount for each horizontal period to detect a phase variation amount. 5. The video signal phase correction device according to claim 4, wherein the predetermined position of the horizontal synchronization signal is a predetermined position of a front edge portion of the horizontal synchronization signal. 6. The video signal phase correction apparatus according to claim 4, wherein the predetermined position of the horizontal synchronization signal is a predetermined position of the trailing edge of the horizontal synchronization signal.