JPH0991138A - Operation processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten instruction processing time by detecting a pair of instructions to be simultaneously executed by a single computing element and simultaneously executing this instruction pair by the single computing element. SOLUTION: A detection circuit 1 detects the instruction pair, which has data dependency relation and can be simultaneously executed by the single computing element, or the instruction pair which has no data dependency relation and can be simultaneously executed by the single computing element. When the detection circuit 1 provided inside an arithmetic unit detects the instruction pair which can be simultaneously executed by the single computing element, this detected result is reported to a control circuit 2 for controlling a computing element 13. The control circuit 2 controls operand data corresponding to the instruction pair to be simultaneously executed so as to be supplied to the computing element 13 and generates a control signal for controlling the operation of the computing element 13 as well. The computing element 13 simultaneously executes the plural instructions based on the supplied operand data and control signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing method suitable for an arithmetic pipeline type data processing apparatus capable of simultaneously executing a plurality of instructions.

[0002]

2. Description of the Related Art In a data processing apparatus of an arithmetic pipeline processing system capable of executing a plurality of instructions in parallel, one of the factors disturbing the smooth flow of the arithmetic pipeline is
The "data dependency hazard" is well known. This is a pipeline hazard that occurs when the second instruction requires the operation result of the first instruction as an operand.

If this "data dependence hazard" frequently occurs, the hardware resources of the arithmetic pipeline processing device capable of executing a plurality of instructions in parallel will not be effectively used. For this reason, various methods have conventionally been proposed to eliminate the “data dependency hazard”.

For example, in order to eliminate a "data dependency hazard" between a pair of instructions, the pair of instructions is "combined".
There is a parallel execution support device for a plurality of scalar instructions that is processed in a single execution cycle (see Japanese Patent Laid-Open No. 5-73309).

[0005]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
The instruction pair having the data dependency relationship is "combined into an instruction" and a "data dependency elimination ALU" is provided to execute the instruction pair to eliminate the "data dependency hazard". However, this method has a problem that the amount of hardware is significantly increased, and the data dependency is not eliminated for all instruction combinations.

An object of the present invention is to detect an instruction pair that can be simultaneously executed by a single arithmetic unit without requiring a large amount of hardware and to execute the instruction pair at the same time, thereby shortening the instruction processing time. It is to provide the above-mentioned arithmetic processing method.

[0007]

In order to achieve the above-mentioned object, in the present invention, a storage unit storing instructions and data, a plurality of instructions are fetched from the storage unit, and the plurality of instructions are decoded in parallel. A data processing device comprising an instruction unit and an operation unit that receives an instruction code and an operand and executes an operation. An operation processing method of an operation pipeline system for executing a plurality of instructions in parallel, the method comprising: Among them, when an instruction pair having a data dependency relationship and capable of being simultaneously executed by a single arithmetic unit is detected, the instruction pair is simultaneously executed by a single arithmetic unit.

When a pair of instructions among the plurality of instructions that has no data dependency and can be simultaneously executed by a single arithmetic unit is detected, the instruction pair is simultaneously executed by a single arithmetic unit. Is characterized by.

Thus, when the detecting means provided in the arithmetic unit detects an instruction pair that can be simultaneously executed by a single arithmetic unit, the detection result is notified to the control means for controlling the arithmetic unit. The control means controls the operand data corresponding to the pair of instructions to be simultaneously executed to be supplied to the arithmetic unit, and also generates a control signal for controlling the operation of the arithmetic unit. The arithmetic unit executes various operations based on the supplied operand data and control signals.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 2 shows the configuration of an arithmetic pipeline type data processing device capable of executing a plurality of instructions in parallel. In the figure, 21 is an instruction unit that decodes a plurality of instructions in parallel, 22 is a storage unit that stores instructions and data, and 23 is an operation unit that executes an operation (floating point operation). The instruction unit 22 includes an instruction buffer 24 that stores the instruction read from the storage unit 22, and a first instruction register 25 that stores the preceding instruction cut out from the instruction buffer 24.
A second instruction register 26 for storing subsequent instructions cut out from the instruction buffer 24 and first and second decoders 27, 2 for simultaneously decoding the instructions of the first and second instruction registers.
It is composed of 8 and the like. And the arithmetic unit 23
Receives instruction codes, memory operands, etc. to be executed in parallel from the instruction unit 21 and the storage unit 22, and executes an operation.

FIG. 1 shows the configuration of a floating point arithmetic unit according to an embodiment of the present invention. Reference numeral 1 is a detection circuit connected to the decoders 27 and 28 of the instruction unit 21. The detection circuit 1 has either a data dependency and an instruction pair that can be simultaneously executed by a single arithmetic unit, or an instruction pair that has no data dependency and can be simultaneously executed by a single arithmetic unit. To detect. Reference numeral 2 denotes a control circuit for controlling the entire arithmetic unit according to the detection result from the detection circuit 1, 3, 4, 5,
6, 7 are selectors, 8 and 9 are work registers, 10
Is a register for storing an intermediate result, 11 is a register for storing store data, 12 is a register for storing an operation result, and 13 is a single arithmetic unit.

The register group 14 generally has a general-purpose register group and a floating-point register group, and the floating-point register group is used when performing a floating-point operation.
The general-purpose register group is used to perform other operations,
In FIG. 1, one register group is shown for simplicity. Also,
101, 102, 103, 104 are operand buses,
Reference numeral 105 is a data bus.

Here, the arithmetic unit 13 of this embodiment does not have a special configuration for executing a plurality of instructions at the same time. That is, a feature of the present invention is that a plurality of instructions (two instructions in this embodiment) are simultaneously executed by a single arithmetic unit by adding a small amount of hardware, which is a point different from the prior art.

However, when the arithmetic unit configuration shown in FIG. 1 is adopted, the combination of instructions that can be simultaneously executed is as follows for the following reason.
To some extent specified. (1) It has only one set of work registers (8 and 9 in FIG. 1). (2) It has only one computing unit (13 in FIG. 1) that can execute the same computation.

Therefore, according to the above (1), if two instructions decoded in parallel require four operands for convenience, simultaneous execution is impossible, and similarly, if three operands for convenience are required, Concurrent execution is possible only when there is a data dependency. Further, due to the above (2), there is a restriction that the same operation instruction cannot be executed simultaneously. However, these restrictions can be almost eliminated by increasing the amount of hardware such as providing a plurality of arithmetic units capable of executing the same arithmetic operation.

As described above, the present invention is characterized in that a plurality of instructions are simultaneously executed by a single arithmetic unit, and the classification of floating point instructions to which the present invention is applied is shown in FIG.
Instructions are divided into RR format and RX format, and each format instruction is classified into four groups. For example, LER
The group load instruction <LER> is a single-precision load instruction, and <LDR> is a double-precision load instruction. The details of each of the above-mentioned commands are described in, for example, the IBM “Ent
erprise System Architectu
re / 370 Principles of Op
ation ”.

In the above classification, the passage route of the arithmetic unit, the instruction format, and the number of execution cycles are different for each instruction.
It becomes an important factor for determining whether or not the instruction pairs can be executed simultaneously. In the following description, of the instruction pairs to be executed at the same time, the preceding instruction is the X type and the subsequent instruction is the Y type.
Called the system.

FIG. 4 shows the result of judgment as to whether or not each instruction pair can be executed simultaneously by a single arithmetic unit, based on the instruction classification of FIG. 3 and the arithmetic unit configuration of FIG. In the figure, when the crossing point between the X system and the Y system is a circle, the preceding X system instruction and the following Y system instruction are
Indicates an instruction pair that can be executed simultaneously. Further, a triangle mark indicates an instruction pair that can be simultaneously executed only when there is a data dependency relationship, and a x mark indicates an instruction pair that cannot be simultaneously executed. The determination result of FIG. 4 is stored in the detection circuit 1 as a table.

The operation of the present invention will be described below by taking a specific instruction pair as an example. It is assumed that the instruction pair of (Example 1) is issued from the instruction unit 21 shown in FIG. 2 to the arithmetic unit 22. That is, the preceding instruction (LDR 0,2) is stored in the instruction register 25, and the subsequent instruction (ADR 0,4).
Are stored in the instruction register 26, are simultaneously decoded by the decoders 27 and 28 in the next stage, and are sent to the detection circuit 1 of the arithmetic unit 22.

Here, the LDR instruction is an instruction for loading the contents of the register designated by the second operand into the register designated by the first operand, and the ADR instruction is
This is an instruction for adding the contents of the register specified by the second operand and the contents of the register specified by the first operand and storing them in the register specified by the first operand.

[0021] The detection circuit 1 refers to the determination result (table) of FIG. 4 based on the instruction code of the issued instruction and the operand address. In this example 1, the preceding instruction (X type) is LDR and the subsequent instruction (Y type) is ADR, and the register specified by the first operand of the preceding instruction and the register specified by the first operand of the subsequent instruction are equal to each other. However, since there is a data dependency, it is determined that the instruction pair of Example 1 can be simultaneously executed by a single arithmetic unit, and the determination result is notified to the control circuit 2. The control circuit 2 controls the arithmetic unit 13 as follows.

First, the selector 6 selects the second operand data of the X-type instruction (contents of the second register), and at the same time selects the second operand data of the Y-type instruction (contents of the fourth register). Select with. The selected operand data are respectively transferred to the operand bus 10
It is sent to selectors 4 and 3 via 2 and 104. Then, the operand data of the operand bus 104 (that is, the second operand data of the ADR) is stored in the work register 8 through the selector 3, and the operand data of the Peland bus 102 (that is, the second operand data of the ADR) (that is, the second operand data of the ADR) is stored through the selector 4. , LDR second operand data) are stored in the work register 9.

Subsequently, the computing unit 13 calculates (contents of the work register 8) + (work register 9
Content) is stored in the register 10 and the register 12 in order, and the result is stored in the 0th register in the register group 14 designated by the first operand of ADR via the data bus 105. The result is stored, and the processing of the above-described instruction pair ends.

As described above, the X-type instruction (LDR) is the second instruction.
It is not executed just by passing the operand data to the Y instruction (that is, the second operand data is not transferred to the register of the first operand), while the Y instruction (AD
R) is controlled so as to add the second operand data of the X-type instruction and the second operand data of its own instruction. As a result, two instructions are simultaneously executed by a single arithmetic unit, and the instruction processing time is shortened as compared with the conventional processing. When the instruction sequences are not simultaneously executable as described above, the preceding instruction is first processed by the arithmetic unit, and the subsequent instruction is then processed by the arithmetic unit.

It is assumed that the instruction pair of (Example 2-1) is issued from the instruction unit 21 shown in FIG. 2 to the arithmetic unit 22. Here, the STD instruction sets the contents of the register specified by the first operand to the main memory address specified by the second operand (this address is specified by the contents of the index address register specified by the X2 field and the B2 field. Contents of the base address register to be set and D2
(Obtained by adding the contents of the field).

[0026] Similar to (Example 1), the detection circuit 1 refers to the determination result (table) of FIG. 4 based on the instruction code and operand address of the issued instruction. In this Example 2-1, since the preceding instruction (X type) is LDR and the subsequent instruction (Y type) is STD, the instruction pair of Example 2-1 is simultaneously executed by a single arithmetic unit regardless of the data dependency. It is determined to be executable, and the determination result is notified to the control circuit 2. The control circuit 2 controls the arithmetic unit 13 as follows.

First, the second operand data of the X-type instruction (LDR) is selected by the selector 6, and at the same time, the Y-type instruction (S
The selector 7 selects the first operand data of TD). The selected operand data are sent to the selectors 3 to 4 via the operand buses 102 to 103, respectively. Next, the operand data of the operand bus 102 (second operand data of LDR) is stored in the work register 8 via the selector 3, and the operand data of the operand bus 103 is stored via the selector 4.
Work with data (first operand data of STD)
Store in register 9.

Next, the X system instruction (LDR) is issued to the arithmetic unit 13
At (contents of work register 8) +0 is calculated (that is, passed through a calculator), the calculation results are sequentially stored in registers 10 and 12, and data bus 1
The calculation result is stored in the register designated by the first operand in the register group 14 via 05.

The Y-system instruction (STD) stores the contents of the work register 9 in the register 11 via the selector 5. At this time, the control circuit 2 operates to select the content of the work register 9 as the store data. Next, the contents of the register 11 are transferred via a bus (not shown) to
The contents of the register 11 are sent to the storage unit 22 shown in FIG. 2 and stored in the main storage address designated by the second operand, whereby the processing of the instruction pair ends.

Similarly, it is assumed that the instruction pair of (Example 2-2) is issued from the instruction unit 21 shown in FIG. 2 to the arithmetic unit 23.

[0031] The difference from (Example 2-1) is that the selector 7 selects the first Y-type instruction.
Operand data is controlled not to be selected, and
The operand bus selected by the selector 4 is controlled to change from 103 to 102. Therefore, the second operand data of the X instruction system selected by the selector 6 is stored in the work register 9 via the operand bus 102 and the selector 4. Subsequent processing is exactly the same as in (Example 2-1), so description thereof will be omitted.

It is assumed that the instruction combination of (Example 3) is issued from the instruction unit 21 shown in FIG. 2 to the arithmetic unit 23.

[0033] The detection circuit 1 checks the instruction code and the operand address of the issued instruction as in the above example. Since there is a data dependency in this example, the detection circuit 1 determines that they can be executed simultaneously by a single arithmetic unit, and controls Notify circuit 2. The control circuit 2 controls the arithmetic unit as follows.

First, the first operand data of the X-type instruction is selected by the selector 6, and at the same time, the second operand data of the Y-type instruction is selected by the selector 7. The selected operand data are sent to the selectors 4 to 3 via the operand buses 101 to 104, respectively.
Next, the operand data on the operand bus 104 is transferred via the selector 3 to the work register 8 (second register of ADR).
The operand data of the operand bus 101 is stored in the work register 9 (first operand of STD) via the selector 4.

Next, the X-type instruction stores the contents of the work register 9 in the register 11 as store data via the selector 5. Next, the contents of the register 11 are sent to the storage unit shown in FIG. 2 via a bus (not shown).

The Y-system instruction is executed in the arithmetic unit 13 by (contents of work register 8) + (work register 9
Content) is stored in the register 10 and the register 12 sequentially, and the calculation result is stored in the register designated by the first operand in the register group 14 via the data bus 105. This completes the processing of the instruction pair.

Similarly, it is assumed that the instruction combination of (Example 4) is issued from the instruction unit to the arithmetic unit.

[0038] The detection circuit 1 checks the instruction code and operand address of the issued instruction as in the above example. Since this example has a data dependency relationship as in Example 3, it can be executed simultaneously by a single arithmetic unit. Then, the control circuit 2 is notified. The control circuit 2 controls the arithmetic unit as follows.

First, the first and second operands of the X-type instruction
The data is selected by the selector 6. At this time, the operand data of the Y-type instruction is not selected by the selector 7. The operand data of the X-system instruction selected by the selector 6 is sent to the selectors 4 to 3 via the operand buses 101 to 102, respectively. Next, selector 3
The operand data of the operand bus 102 is stored in the work register 8 (second operand of ADR) via the selector register 4, and the operand data of the operand bus 101 is stored in the work register 9 (first register of ADR) via the selector 4.
Operand).

Next, in the arithmetic unit 13, (contents of the work register 8) + (work register 9
The contents of 1) are calculated, the calculation results are sequentially stored in the register 10 and the register 12, and the register group 1 is stored via the data bus 105.
The operation result is stored in the register designated by the first operand in 4.

Here, it should be noted that
This is processing of Y-type instructions in (Example 4). That is, unlike the store instruction of Example 3 described above, the data to be stored in the processing of the Y-type instruction of Example 4 is not the operand data stored in the work register 9 but the data of the operation result of the X-type instruction. is there. Therefore, the store data to be sent to the storage unit is stored in the register 11 one machine cycle later than the store instruction of the above-described example 3.

The processing of Y-related instructions is as follows. An operation result is stored in the register 10 after being calculated by the calculator 13 according to the X-system instruction, and sent to the selector 5. Selector 5
Is controlled by the control circuit 2 to select the operation result of the X-type instruction as the store data of the Y-type instruction. Then
The store data stored in the register 11 is sent to the storage unit shown in FIG. 2 via a bus (not shown), and the process ends.

Although one embodiment of the present invention has been described above by taking several instruction pairs as an example, the operation of other simultaneously executable instruction pairs shown in FIG. 4 will be described in exactly the same manner. It will be easily understood. By the processing described above, it is possible to execute a plurality of instructions simultaneously without increasing the amount of hardware with a single arithmetic unit, and it is possible to shorten the instruction processing time.

Although the present invention is effective in improving the processing performance even when there is a single arithmetic unit, when it is applied to a data processing apparatus having a plurality of arithmetic units, a more remarkable effect can be obtained. It will be obvious.

[0045]

As described above, according to the present invention, there is a data dependency and a pair of instructions that can be simultaneously executed by a single arithmetic unit, or there is no data dependency and a single instruction pair. Since any one of the instruction pairs that can be executed simultaneously by the arithmetic unit is detected and the detected instruction pair is executed by the single arithmetic unit at the same time, the instruction processing time can be shortened without increasing the hardware amount. be able to.

[Brief description of drawings]

FIG. 1 shows a configuration of a floating point arithmetic unit according to an embodiment of the present invention.

FIG. 2 shows the configuration of an arithmetic pipeline type data processing device capable of executing a plurality of instructions in parallel.

FIG. 3 shows a classification of floating-point instructions targeted by the present invention.

FIG. 4 shows a determination result of whether or not an instruction pair can be simultaneously executed by a single arithmetic unit.

[Explanation of symbols]

 1 Detection Circuit 2 Control Circuit 3, 4, 5, 6, 7 Selector 8, 9 Work Register 10 Intermediate Result Register 11 Store Data Register 12 Operation Result Register 13 Operation Unit 14 Register Group 101, 102, 103, 104 Operand Bus 105 Data bus

Claims (2)

[Claims] 1. A storage unit for storing instructions and data, an instruction unit for extracting a plurality of instructions from the storage unit and decoding the plurality of instructions in parallel, an operation for receiving an instruction code and an operand, and executing an operation. A data processing device including a unit, which is an operation processing method of an operation pipeline method for executing a plurality of instructions in parallel, wherein the plurality of instructions have a data dependency relationship and a single operation unit An arithmetic processing method characterized in that, when an instruction pair that can be executed simultaneously is detected, the instruction pair is executed simultaneously by a single arithmetic unit. 2. When a pair of instructions among the plurality of instructions that has no data dependency and can be simultaneously executed by a single arithmetic unit is detected, the instruction pair is simultaneously executed by a single arithmetic unit. The arithmetic processing method according to claim 1, wherein: