JPH098621A - Fet switch circuit - Google Patents
Fet switch circuitInfo
- Publication number
- JPH098621A JPH098621A JP15026895A JP15026895A JPH098621A JP H098621 A JPH098621 A JP H098621A JP 15026895 A JP15026895 A JP 15026895A JP 15026895 A JP15026895 A JP 15026895A JP H098621 A JPH098621 A JP H098621A
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- switch circuit
- input
- fet
- fets
- gate
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＦＥＴスイッチ回路に
関し、特に、高周波、大電力用のＦＥＴスイッチ回路に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FET switch circuit, and more particularly to a high frequency and large power FET switch circuit.
【０００２】[0002]
【従来の技術】従来のＦＥＴスイッチ回路は、図６に示
すように、入力端子６１と出力端子６２との間で直列接
続され信号経路を形成する複数（ここでは３個）のＦＥ
Ｔ（電界効果トランジスタ）６３ａ、６３ｂ、及び６３
ｃと、出力端子６２と接地との間に直列接続された複数
（ここでは３個）のＦＥＴ６４ａ、６４ｂ、及び６４ｃ
とを有している。各ＦＥＴのゲートには、それぞれ保護
抵抗器６５ａ、６５ｂ、６５ｃ、６５ｄ、６５ｅ、及び
６５ｆが接続され、制御端子６６及び６７に接続されて
いる。なお、上記ＦＥＴは全て同一特性で、また保護抵
抗器も同一抵抗値を有するものとする。2. Description of the Related Art In a conventional FET switch circuit, as shown in FIG. 6, a plurality of (here, three) FEs are connected in series between an input terminal 61 and an output terminal 62 to form a signal path.
T (field effect transistor) 63a, 63b, and 63
c, and a plurality of (here, three) FETs 64a, 64b, and 64c connected in series between the output terminal 62 and the ground.
And Protective resistors 65a, 65b, 65c, 65d, 65e, and 65f are connected to the gates of the respective FETs, and are connected to control terminals 66 and 67. All the FETs have the same characteristics, and the protection resistors have the same resistance value.
【０００３】このスイッチ回路では、制御端子６６に印
加される制御電圧をＶc1としたとき、制御端子６７に
は、数式１で表わされる制御電圧Ｖc2が印加される。In this switch circuit, when the control voltage applied to the control terminal 66 is Vc1, the control voltage Vc2 expressed by the equation 1 is applied to the control terminal 67.
【０００４】[0004]
【数１】 これにより、このスイッチ回路がオンしたとき（ＦＥＴ
６３ａ、６３ｂ、及び６３ｃがオンしたとき）に、ＦＥ
Ｔ６４ａ、６４ｂ、及び６４ｃはオフし、逆にこのスイ
ッチ回路がオフしたときに、ＦＥＴ６４ａ、６４ｂ、及
び６４ｃはオンする。この結果、スイッチ回路がオン状
態にあるとき、入力端子に入力された高周波信号（例え
ば、１〜２ＧＨｚ）は出力端子へ供給される。また、ス
イッチ回路がオフ状態にあるときは、入力端子に入力さ
れる高周波信号が、ＦＥＴ６３ａ、６３ｂ、及び６３ｃ
を通り出力端子側にリークしても、その高周波成分はＦ
ＥＴ６４ａ、６４ｂ、及び６４ｃを介して接地される。
従って、スイッチ回路がオフ状態にあるとき、入力端子
に入力される高周波信号は出力端子に供給されることが
無い。このように、ＦＥＴ６４ａ、６４ｂ、及び６４ｃ
を設けることにより、このスイッチ回路のアイソレーシ
ョン特性は改善される。[Equation 1] As a result, when this switch circuit is turned on (FET
63a, 63b, and 63c are turned on), FE
T64a, 64b, and 64c turn off, and conversely, when this switch circuit turns off, the FETs 64a, 64b, and 64c turn on. As a result, when the switch circuit is in the ON state, the high frequency signal (for example, 1 to 2 GHz) input to the input terminal is supplied to the output terminal. Further, when the switch circuit is in the off state, the high frequency signal input to the input terminal is the FETs 63a, 63b and 63c.
Even if it leaks to the output terminal side through
Grounded through ETs 64a, 64b, and 64c.
Therefore, when the switch circuit is in the off state, the high frequency signal input to the input terminal is not supplied to the output terminal. Thus, FETs 64a, 64b, and 64c
By providing, the isolation characteristic of this switch circuit is improved.
【０００５】このスイッチ回路のように、複数のＦＥＴ
を直列に接続すると、その直列接続されたＦＥＴがオフ
状態のときのドレイン−ソース間の高周波信号に対する
耐圧を改善することができる。以下、詳述する。Like this switch circuit, a plurality of FETs
Is connected in series, it is possible to improve the withstand voltage against a high-frequency signal between the drain and the source when the FETs connected in series are in the off state. The details will be described below.
【０００６】図７に示すように、２つのＦＥＴ７１及び
７２が直列接続され、かつ入力端子７３（出力端子７
４）と接地との間に接続されているものとする。また、
これらのＦＥＴ７１、７２は、同一の特性を有し、ゲー
ト・ソース間容量とゲート・ドレイン間容量とが等しい
（＝Ｃg ）ものとする。更に、各ゲートは、高抵抗を介
してバイアスされており、バイアス回路は高周波に対し
て高インピーダンスと見なすことができるものとする。As shown in FIG. 7, two FETs 71 and 72 are connected in series and an input terminal 73 (output terminal 7
It shall be connected between 4) and ground. Also,
These FETs 71 and 72 have the same characteristics, and the gate-source capacitance and the gate-drain capacitance are equal (= C g ). Further, each gate is biased through a high resistance, and the bias circuit can be regarded as a high impedance with respect to a high frequency.
【０００７】このようなスイッチ回路に、各ＦＥＴがオ
フとなる様なゲート電圧ＶG を印加し、入力端子に振幅
ｖinの高周波信号入力すると、ゲート・ソース間容量及
びゲート・ドレイン間容量の働きにより、点Ａ、Ｂ、
Ｃ、及びＤにおける電位変動は図８（ａ）、（ｂ）、
（ｃ）、及び（ｄ）に示すようになる。このとき、各Ｆ
ＥＴ７１、７２のゲート・ソース間電圧ＶGS（ゲート・
ドレイン間電圧ＶGD）の最大値は、直列接続されたＦＥ
Ｔの数をｎとすると、（ＶG ＋ｖin／２ｎ）となる。こ
の最大値が各ＦＥＴのしきい値電圧ＶP を越えると、Ｆ
ＥＴはオン状態に変化し、点Ａにおいて入力信号がクリ
ッピングされ、出力端子７４の出力信号波形に歪みが発
生する。すなわち、出力信号の最大振幅ｖmax は、ゲー
ト・ソース間電圧ＶGSの最大値が、しきい値電圧ＶP に
等しいときと同じで、ｖmax ＝２ｎ（ＶP −ＶG ）で表
わされる。このように最大振幅ｖmax は、ＦＥＴの数ｎ
に比例し、ＦＥＴの数を増やせば最大振幅ｖmax は大き
くなる。すなわち、ＦＥＴの数ｎを増やせば、耐圧（歪
みを発生させるなく信号を伝送できる入力信号電圧）を
高めることができる。When a gate voltage V G for turning off each FET is applied to such a switch circuit and a high frequency signal of amplitude v in is input to the input terminal, the gate-source capacitance and the gate-drain capacitance are changed. Depending on the function, points A, B,
The potential fluctuations in C and D are shown in FIGS.
As shown in (c) and (d). At this time, each F
ET71, 72 gate-source voltage V GS (gate
The maximum value of the drain-to-drain voltage V GD ) is the FE connected in series.
If the number of T is n, then (V G + v in / 2n). When this maximum value exceeds the threshold voltage V P of each FET, F
ET changes to the ON state, the input signal is clipped at the point A, and the output signal waveform at the output terminal 74 is distorted. That is, the maximum amplitude v max of the output signal is the same as when the maximum value of the gate-source voltage V GS is equal to the threshold voltage V P , and is represented by v max = 2n (V P −V G ). . Thus, the maximum amplitude v max is the number of FETs n
The maximum amplitude v max increases as the number of FETs increases. That is, if the number n of FETs is increased, the breakdown voltage (input signal voltage capable of transmitting a signal without causing distortion) can be increased.
【０００８】[0008]
【発明が解決しようとする課題】従来のスイッチ回路
は、上述したように、複数のＦＥＴを直列接続して耐圧
改善（耐入力レベルの向上）を行うが、このように複数
のＦＥＴを直列接続すると、ＦＥＴの数に比例してオン
抵抗が大きくなるという問題点がある。この問題を解決
するには、各ＦＥＴのゲート幅を大きくすればよいが
（直列接続されるＦＥＴがｎ個ならばｎ倍）、レイアウ
ト面積はｎ2 に比例して大きくなるという新たな問題を
引き起こす。As described above, in the conventional switch circuit, a plurality of FETs are connected in series to improve the withstand voltage (improve the withstand input level). In this way, a plurality of FETs are connected in series. Then, there is a problem that the on-resistance increases in proportion to the number of FETs. To solve this problem, the gate width of each FET may be increased (n times the number of FETs connected in series is n times), but there is a new problem that the layout area increases in proportion to n 2. cause.
【０００９】また、従来のスイッチ回路は、耐圧が、Ｆ
ＥＴのしきい値電圧ＶP に依存するため、製造プロセス
において、Ｖp のばらつきを抑える必要がある。ところ
が、近年のゲート電圧ＶG の低電圧化（ＶG がＶp に近
付く）に伴って、Ｖp に対する依存性が更に高まり（非
常に敏感となり）、プロセスにおける制御が困難で歩留
まりが低下するという問題点がある。Further, the withstand voltage of the conventional switch circuit is F
Since it depends on the threshold voltage V P of ET, it is necessary to suppress the variation of V p in the manufacturing process. However, with the recent decrease in the gate voltage V G (V G approaches V p ), the dependency on V p further increases (becomes very sensitive), and it is difficult to control in the process and the yield decreases. There is a problem.
【００１０】本願発明は、直列接続されたＦＥＴの数を
増やすことなく耐入力レベルの向上を図り、以てレイア
ウト面積が小さく、歩留まりの良いスイッチ回路を提供
することを目的とする。An object of the present invention is to provide a switch circuit which has a small layout area and a high yield by improving the input withstand level without increasing the number of FETs connected in series.
【００１１】なお、構成が簡単な高耐圧スイッチ回路と
して図９に示す様な回路が特開昭５７−７５０３０号公
報に開示されているが、この回路では、寄生容量が無視
され、また、ＦＥＴ９１がソース接地インバーターとし
て用いられているため、ドレイン・ソース間電圧が反転
する場合は考慮されていない。したがって、この回路
は、高周波信号用の切り替えスイッチとして使用するこ
とはできない。A circuit as shown in FIG. 9 is disclosed as a high withstand voltage switch circuit having a simple structure in Japanese Patent Application Laid-Open No. 57-75030. However, in this circuit, the parasitic capacitance is ignored and the FET 91 is used. Since it is used as a source-grounded inverter, it is not considered when the drain-source voltage is inverted. Therefore, this circuit cannot be used as a changeover switch for high frequency signals.
【００１２】[0012]
【課題を解決するための手段】本発明によれば、２つの
入出力端子の間に複数の第１の電界効果トランジスタを
直列に接続したＦＥＴスイッチ回路において、前記２つ
の入出力端子と該２つの入出力端子にそれぞれ接続され
た電界効果トランジスタのゲートとの間に、それぞれキ
ャパシタを接続したことを特徴とするＦＥＴスイッチ回
路が得られる。According to the present invention, in an FET switch circuit in which a plurality of first field effect transistors are connected in series between two input / output terminals, the two input / output terminals and the two An FET switch circuit is obtained in which capacitors are respectively connected between the gates of field effect transistors connected to one input / output terminal.
【００１３】[0013]
【実施例】以下、図面を参照して本発明の実施例を説明
する。図１に本発明の第１の実施例を示す。本実施例の
スイッチ回路は、入力端子１１と出力端子１２との間に
直列に接続された２つのＦＥＴ１３ａ、１３ｂと、出力
端子１２と接地との間に直列に接続された２つのＦＥＴ
１４ａ、１４ｂと、ＦＥＴ１３ａ、１３ｂの各ゲートと
制御端子１５との間にそれぞれ接続された高抵抗１６
ａ、１６ｂと、ＦＥＴ１４ａ、１４ｂの各ゲートと制御
端子１７との間にそれぞれ接続された高抵抗１８ａ、１
８ｂとを有している。また、直列接続された両端のＦＥ
Ｔ（本実施例の場合、直列接続された２個のＦＥＴが２
組なので全てのＦＥＴ）のゲートと入力端子、出力端
子、あるいは、接地との間にはキャパシタが接続されて
いる。具体的には、ＦＥＴ１３ａのゲートと入力端子１
１との間にキャパシタ１９ａが、ＦＥＴ１３ｂのゲート
と出力端子１２との間にキャパシタ１９ｂが、ＦＥＴ１
４ａのゲートと出力端子１２との間にキャパシタ１９ｃ
が、ＦＥＴ１４ｂのゲートと接地との間にキャパシタ１
９ｄが、それぞれ接続されている。なお、ＦＥＴ、高抵
抗、キャパシタは、それぞれ同一特性を有するものとす
る。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. The switch circuit of this embodiment includes two FETs 13a and 13b connected in series between the input terminal 11 and the output terminal 12, and two FETs connected in series between the output terminal 12 and the ground.
14a, 14b, a high resistance 16 connected between each gate of the FETs 13a, 13b and the control terminal 15, respectively.
a, 16b, high resistances 18a, 1 connected between the gates of the FETs 14a, 14b and the control terminal 17, respectively.
8b and. In addition, FEs at both ends connected in series
T (in the case of this embodiment, two FETs connected in series have two
Since it is a set, capacitors are connected between the gates of all the FETs) and the input terminals, output terminals, or ground. Specifically, the gate of the FET 13a and the input terminal 1
1 is connected to the capacitor 19a, and between the gate of the FET 13b and the output terminal 12, the capacitor 19b is connected to the FET1.
A capacitor 19c is provided between the gate of 4a and the output terminal 12.
However, there is a capacitor 1 between the gate of the FET 14b and the ground.
9d are respectively connected. The FET, the high resistance, and the capacitor have the same characteristics.
【００１４】従来のスイッチ回路と同様に、本実施例の
スイッチ回路でも、制御端子１５に印加される制御電圧
をＶc1としたとき、制御端子１７には、数式２で表わさ
れる制御電圧Ｖc2が印加される。Similar to the conventional switch circuit, also in the switch circuit of this embodiment, when the control voltage applied to the control terminal 15 is Vc1, the control voltage Vc2 expressed by the equation 2 is applied to the control terminal 17. To be done.
【００１５】[0015]
【数２】 これにより、ＦＥＴ１３ａ、１３ｂがオンのとき、ＦＥ
Ｔ１４ａ、１４ｂはオフとなり、入力端子１１に入力さ
れた高周波信号は出力端子１２へ供給される。また、Ｆ
ＥＴ１３ａ、１３ｂがオフのとき、ＦＥＴ１４ａ、１４
ｂはオンとなり、例え、入力端子に入力された高周波信
号が出力端子側へとリークしても、リークした高周波信
号は、ＦＥＴ１４ａ、１４ｂにより接地される。[Equation 2] As a result, when the FETs 13a and 13b are turned on, the FE
T14a and T14b are turned off, and the high frequency signal input to the input terminal 11 is supplied to the output terminal 12. Also, F
When the ETs 13a and 13b are off, the FETs 14a and 14 are
Even when the high frequency signal input to the input terminal leaks to the output terminal side, the leaked high frequency signal is grounded by the FETs 14a and 14b.
【００１６】以下、本発明のスイッチ回路の動作を図２
を参照して詳述する。ここでは、ＦＥＴ１３ａ、１３ｂ
がオン状態の場合（入力端子１１と出力端子１２とが直
接接続されていると想定した場合）に付いて説明する。
即ち、ＦＥＴ１３ａ、１３ｂのゲートに、これらＦＥＴ
をオフさせるゲート電圧ＶG が与えられている場合に付
いて説明する。なお、各キャパシタ１９ｃ、１９ｄの静
電容量Ｃ0 は、ＦＥＴ１４ａ、１４ｂのオフ時のゲート
・ソース（ドレイン）容量Ｃg よりも大きいものとす
る。The operation of the switch circuit of the present invention will be described below with reference to FIG.
Will be described in detail. Here, FETs 13a and 13b
Will be described (when it is assumed that the input terminal 11 and the output terminal 12 are directly connected).
That is, the FETs 13a and 13b are connected to the gates of these FETs.
The case where the gate voltage V G for turning off is given will be described. The capacitance C 0 of each of the capacitors 19c and 19d is larger than the gate-source (drain) capacitance C g of the FETs 14a and 14b when the FETs 14a and 14b are off.
【００１７】図２の入力端子１１に振幅ｖinの入力信号
が入力されたとすると、点Ａにおける電位変動は、従来
同様、図３（ａ）に示すようになる。このとき、点Ｂに
おける電位変動は、キャパシタ１９ｃの働きにより、図
３（ｂ）に示す通り、振幅ｖinで変動する。また、点Ｄ
における電位変動は、キャパシタ１９ｄの働きによりほ
とんど無くなる。つまり、点Ｄの電位はＶG で一定と考
えられる。Assuming that an input signal having the amplitude v in is input to the input terminal 11 of FIG. 2, the potential fluctuation at the point A is as shown in FIG. At this time, the potential fluctuation at the point B varies with the amplitude v in as shown in FIG. 3B due to the function of the capacitor 19c. Also, point D
The potential fluctuation at is almost eliminated by the action of the capacitor 19d. That is, the potential at the point D is considered to be constant at V G.
【００１８】点Ａにおける電位が正に振れ、点ＢＣ間の
電位差がしきい値ＶP 以上になると、ＦＥＴ１４ａはオ
ン状態に変化する。このとき、ＦＥＴ１４ｂはオフのま
まである。逆に点Ａおける電位が負に振れ、点ＤＣ間の
電位差がしきい値ＶP 以上になると、ＦＥＴ１４ｂはオ
ン状態に変化する。このとき、ＦＥＴ１４ａはオフのま
まである。このとき、Ｃ点の電位変動は、図３（ｃ）に
示すように、点Ａでの電位が正の時は、ほぼ点Ａの電位
と等しく、点Ａ出の電位が負の時は、ほぼ接地電位（０
Ｖ）になる。ここで、Ｃ0 ＝∞、と仮定すると、本実施
例のスイッチ回路では、入力振幅ｖinに無関係に、ＦＥ
Ｔ１４ａ及び１４ｂのうち少なくとも一方は常にオフ状
態にある。つまり、ＦＥＴ１４ａ及び１４ｂがオフ状態
にある場合、どの様な信号が入力されようとも、オン状
態に反転して信号をリークさせることがない。したがっ
て、本実施例のスイッチ回路では、理論上、最大入力振
幅ｖmax は無限大である。実際のスイッチ回路では、ゲ
ート耐圧ＢＶGDが有限なので、ｖmax は、ほぼＢＶGDに
等しい。When the potential at the point A swings positively and the potential difference between the points BC exceeds the threshold value V P , the FET 14a changes to the ON state. At this time, the FET 14b remains off. Conversely, when the potential at the point A swings negatively and the potential difference between the points DC becomes equal to or greater than the threshold value VP, the FET 14b changes to the ON state. At this time, the FET 14a remains off. At this time, the potential fluctuation at the point C is substantially equal to the potential at the point A when the potential at the point A is positive, and when the potential at the point A is negative, as shown in FIG. Near ground potential (0
V). Here, assuming that C 0 = ∞, in the switch circuit of the present embodiment, the FE is irrespective of the input amplitude v in.
At least one of T14a and T14b is always in the off state. That is, when the FETs 14a and 14b are in the off state, no matter what signal is input, the signal is not inverted to the on state to leak the signal. Therefore, in the switch circuit of this embodiment, theoretically, the maximum input amplitude v max is infinite. In an actual switch circuit, since the gate breakdown voltage BV GD is finite, v max is almost equal to BV GD .
【００１９】図４に、従来のスイッチ回路と本実施例に
よるスイッチ回路との特性を測定した結果を示す。ここ
で、使用したＦＥＴは、ＶP ＝−２．０Ｖ，ＢＶGD＝２
０Ｖである。また、図４において、◎は、従来のＦＥＴ
を２段接続したスイッチ回路、□は従来のＦＥＴを３段
接続したスイッチ回路（図６参照）、△は、Ｃ0 ＝２ｐ
Ｆとした図１のスイッチ回路、○は、Ｃ0 ＝１０ｐＦと
した図１のスイッチ回路の耐入力レベルの測定結果を表
わす。なお、ここでいう耐入力レベルとは、入力信号に
対する出力信号の歪みが−１ｄＢの時の最大入力振幅を
表わします。FIG. 4 shows the results of measuring the characteristics of the conventional switch circuit and the switch circuit according to this embodiment. The FET used here has V P = -2.0 V, BV GD = 2
0V. Further, in FIG. 4, ◎ indicates a conventional FET
Is a switch circuit in which two stages are connected, □ is a switch circuit in which a conventional FET is connected in three stages (see FIG. 6), and Δ is C 0 = 2p
The switch circuit of FIG. 1 set to F, and the open circles represent the measurement result of the withstand input level of the switch circuit of FIG. 1 set to C 0 = 10 pF. The withstand input level here refers to the maximum input amplitude when the distortion of the output signal with respect to the input signal is -1 dB.
【００２０】図４から明らかな通り、本実施例によるス
イッチ回路（Ｃ0 ＝１０ｐＦ）では、従来のＦＥＴ３段
の回路をＶG ＝−５Ｖで使用したときと同程度の耐入力
レベルを得ることができる。また、本実施例によるスイ
ッチ回路（Ｃ0 ＝１０ｐＦ）では、ＶG ＝−２．５〜−
５Ｖの広範囲に渡り、ＢＶGDできまる一定の耐入力レベ
ルが得られる。これは、ＶP のばらつきに影響されず、
ほぼ一定の耐入力レベルが得られることを意味する。As is apparent from FIG. 4, in the switch circuit (C 0 = 10 pF) according to this embodiment, an input withstand level similar to that when a conventional 3-stage FET circuit is used at V G = -5V is obtained. You can In addition, in the switch circuit (C 0 = 10 pF) according to this embodiment, V G = −2.5 to −
Over a wide range of 5V, a constant input withstand level that can be achieved by BV GD can be obtained. This is not affected by the variation of V P ,
This means that a nearly constant input withstand level can be obtained.
【００２１】このように本実施例によれば、ＦＥＴの段
数を増やすことなく、つまり、レイアウト面積を拡大す
ることなく、耐入力レベルの改善を実現できる。また、
各ＦＥＴのＶP のばらつきによる影響を抑制することが
できる。As described above, according to this embodiment, it is possible to improve the input withstand level without increasing the number of FET stages, that is, without increasing the layout area. Also,
It is possible to suppress the influence of variations in V P of each FET.
【００２２】図５に、本発明の第２の実施例を示す。本
実施例では、ＦＥＴ５１ａ、５１ｂ、及び５１ｃと、Ｆ
ＥＴ５２ａ、５２ｂ、及び５２ｃとがそれぞれ直列接続
されており、両端のＦＥＴのゲート５１ａ、５１ｃ、５
２ａ、及び５２ｃにはキャパシタ５３ａ、５３ｂ、５３
ｃ、及び５３ｄが接続されている。本実施例のスイッチ
回路の動作も、ほぼ第１の実施例と同じであるが、ＦＥ
Ｔの接続段数を増やしたことにより、第１の実施例より
も、ＢＶGDへの依存性が若干抑えられるため、耐入力レ
ベルは、第１の実施例よりも更に改善される。また、Ｖ
P のばらつきによる影響についても同様に第１の実施例
よりも改善される。FIG. 5 shows a second embodiment of the present invention. In this embodiment, the FETs 51a, 51b and 51c, and F
ETs 52a, 52b, and 52c are respectively connected in series, and gates 51a, 51c, and 5 of the FETs at both ends are connected.
2a and 52c have capacitors 53a, 53b, 53
c and 53d are connected. The operation of the switch circuit of this embodiment is almost the same as that of the first embodiment, but the FE
By increasing the number of connection stages of T, the dependence on BV GD is slightly suppressed as compared with the first embodiment, so the input withstand level is further improved as compared with the first embodiment. Also, V
The influence of the variation of P is similarly improved as compared with the first embodiment.
【００２３】[0023]
【発明の効果】本発明によれば、複数のＦＥＴを直列接
続し、その両端の端子とその端子に接続されているＦＥ
Ｔのゲートとの間にキャパシタを接続したことで、ＦＥ
Ｔの段数を増やすことなく、耐入力レベルを改善するこ
とができる。また、ＦＥＴの段数を増やす必要がないの
で、レイアウト面積を小さくすることもできる。According to the present invention, a plurality of FETs are connected in series and terminals at both ends thereof and FEs connected to the terminals are connected.
By connecting a capacitor between the gate of T and FE,
The input withstand level can be improved without increasing the number of T stages. Further, since it is not necessary to increase the number of FET stages, the layout area can be reduced.
【００２４】また、キャパシタを設けたことにより、耐
入力レベルが、ゲート耐圧ＢＶGDによって決まり、制御
電圧ＶG やしきい値電圧ＶP に依存しなくなるため、使
用可能な制御電圧の範囲が広がると共に、製造プロセス
において、しきい値電圧ＶPのばらつきの許容範囲が広
がり、歩留まりが向上するという効果もある。Further, by providing the capacitor, the withstand input level is determined by the gate breakdown voltage BV GD and does not depend on the control voltage V G or the threshold voltage V P , so that the usable control voltage range is expanded. At the same time, in the manufacturing process, the allowable range of variations in the threshold voltage V P is widened, and the yield is improved.
【図１】本発明の第１の実施例の回路図である。FIG. 1 is a circuit diagram of a first embodiment of the present invention.
【図２】図１のスイッチ回路の動作を説明するための回
路図である。FIG. 2 is a circuit diagram for explaining the operation of the switch circuit of FIG.
【図３】（ａ）、（ｂ）、（ｃ）、及び（ｄ）は、それ
ぞれ図２の回路の点Ａ、Ｂ、Ｃ、及びＤにおける電位変
動を示すグラフである。3 (a), (b), (c), and (d) are graphs showing potential fluctuations at points A, B, C, and D of the circuit of FIG. 2, respectively.
【図４】第１の実施例によるスイッチ回路と従来のスイ
ッチ回路の、ゲート電圧に対すする耐入力レベルを示す
グラフである。FIG. 4 is a graph showing the withstand input level with respect to the gate voltage of the switch circuit according to the first embodiment and the conventional switch circuit.
【図５】本発明の第２の実施例のスイッチ回路の回路図
である。FIG. 5 is a circuit diagram of a switch circuit according to a second embodiment of the present invention.
【図６】従来のスイッチ回路の回路図である。FIG. 6 is a circuit diagram of a conventional switch circuit.
【図７】従来のスイッチ回路の動作を説明するための図
である。FIG. 7 is a diagram for explaining the operation of a conventional switch circuit.
【図８】（ａ）、（ｂ）、（ｃ）、及び（ｄ）は、それ
ぞれ図７の回路の点Ａ、Ｂ、Ｃ、及びＤにおける電位変
動を示すグラフである。8A, 8B, 8C, and 8D are graphs showing potential fluctuations at points A, B, C, and D in the circuit of FIG. 7, respectively.
【図９】他の従来のスイッチ回路の回路図である。FIG. 9 is a circuit diagram of another conventional switch circuit.
１１ 入力端子 １２ 出力端子 １３ａ，１３ｂ ＦＥＴ １４ａ，１４ｂ ＦＥＴ １６ａ，１６ｂ 高抵抗 １７ 制御端子 １８ａ，１８ｂ 高抵抗 １９ａ，１９ｂ，１９ｃ，１９ｄ キャパシタ ５１ａ，５１ｂ，５１ｃ ＦＥＴ ５２ａ，５２ｂ，５２ｃ ＦＥＴ ５３ａ，５３ｂ，５３ｃ，５３ｄ キャパシタ ６１ 入力端子 ６２ 出力端子 ６３ａ，６３ｂ，６３ｃ ＦＥＴ ６４ａ，６４ｂ，６４ｃ ＦＥＴ ６５ａ，６５ｂ，６５ｃ，６５ｄ，６５ｅ，６５ｆ
保護抵抗器 ６６，６７ 制御端子 ７１，７２ ＦＥＴ ７３ 入力端子 ７４ 出力端子11 Input terminal 12 Output terminal 13a, 13b FET 14a, 14b FET 16a, 16b High resistance 17 Control terminal 18a, 18b High resistance 19a, 19b, 19c, 19d Capacitor 51a, 51b, 51c FET 52a, 52b, 52c FET 53a, 53b , 53c, 53d Capacitor 61 Input terminal 62 Output terminal 63a, 63b, 63c FET 64a, 64b, 64c FET 65a, 65b, 65c, 65d, 65e, 65f
Protection resistor 66,67 Control terminal 71,72 FET 73 Input terminal 74 Output terminal
Claims (3)
界効果トランジスタを直列に接続したＦＥＴスイッチ回
路において、前記２つの入出力端子と該２つの入出力端
子にそれぞれ接続された電界効果トランジスタのゲート
との間に、それぞれキャパシタを接続したことを特徴と
するＦＥＴスイッチ回路。1. In an FET switch circuit in which a plurality of first field effect transistors are connected in series between two input / output terminals, the two input / output terminals and the electric fields connected to the two input / output terminals, respectively. A FET switch circuit characterized in that a capacitor is connected between the gate of the effect transistor and the gate of the effect transistor.
間に、前記第１の電界効果トランジスタと同数の第２の
電界効果トランジスタを直列接続し、前記２つの入出力
端子の一方と該２つの入出力端子の一方に接続された前
記第２の電界効果トランジスタのゲートとの間と、前記
接地と該接地に接続された前記第２の電界効果トランジ
スタのゲートとの間とに、それぞれキャパシタを接続し
たことを特徴とする請求項１のＦＥＴスイッチ回路。2. The same number of second field effect transistors as the first field effect transistors are connected in series between one of the two input / output terminals and the ground, and one of the two input / output terminals is connected to one of the two input / output terminals. Between the gate of the second field effect transistor connected to one of the two input / output terminals and between the ground and the gate of the second field effect transistor connected to the ground, 2. The FET switch circuit according to claim 1, wherein capacitors are connected to each other.
続された電界効果トランジスタのオフ状態における端子
・ゲート間の寄生容量よりも、大きい容量を有すること
を特徴とする請求項１または２のＦＥＴスイッチ回路。3. The FET switch circuit according to claim 1, wherein the capacitor has a capacitance larger than a parasitic capacitance between a terminal and a gate in a turned-off state of a field effect transistor to which the capacitor is connected. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15026895A JP2770846B2 (en) | 1995-06-16 | 1995-06-16 | FET switch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15026895A JP2770846B2 (en) | 1995-06-16 | 1995-06-16 | FET switch circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH098621A true JPH098621A (en) | 1997-01-10 |
| JP2770846B2 JP2770846B2 (en) | 1998-07-02 |
Family
ID=15493236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15026895A Expired - Fee Related JP2770846B2 (en) | 1995-06-16 | 1995-06-16 | FET switch circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2770846B2 (en) |
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|---|---|
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