JPH0984047A - Jitter elimination circuit, comb-line filter and video signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate jitter on a horizontal synchronizing signal in a composite video signal. SOLUTION: A phase comparator circuit 82 compares a phase of a horizontal synchronizing signal (input signal) with a phase of a pulse with the same period as the horizontal synchronizing signal generated by a timing generating circuit 81 and a discrimination circuit 83 discriminates whether or not the period of the horizontal synchronizing signal is stable based on the comparison result. A switch 84 selects a terminal 84a or 84b based on the discrimination result and either of the pulse generated by the timing generating circuit 81 or the horizontal synchronizing signal is outputted thereby. Then the timing generating circuit 81 controls a phase of the pulse generated by itself corresponding to the signal outputted from the switch 84.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a jitter removing circuit,
The present invention relates to a comb filter and a video signal processing device. In particular, the present invention relates to a jitter removing circuit, a comb filter, and a video signal processing device capable of removing jitter included in a periodic input signal such as a horizontal synchronizing signal of a composite video signal.

[0002]

2. Description of the Related Art FIG. 7 shows an example of the structure of a conventional three-dimensional comb filter for separating a luminance signal (Y) and a color signal (C) (Y / C separation) from a color composite video signal. There is. For example, NTSC (National Television System)
Committee) system color composite video signal,
It is sampled at a timing of a predetermined sampling clock and supplied to the frame buffer 106. The frame buffer 106 stores the supplied composite video signal for one frame, and delays the composite video signal by a time corresponding to one frame (the composite video signal delayed by this one frame is referred to as It is appropriately called a delayed video signal) and is output to the calculator 67. In addition to the delayed video signal, the composite video signal is also supplied to the calculator 67, in which the color signal is calculated by calculating the difference between the delay signal and the composite video signal. .

This color signal is a BPF (Band Pass Filte).
r) 68, noise components in the surroundings are removed and output.

The composite video signal is sent to the frame buffer 106.
It is also supplied to the DL (Delay Line) 69 in addition to the calculator 67. In the DL69, the arithmetic unit 67 and the BPF
The composite video signal is delayed by the processing time at 68,
It is supplied to the arithmetic unit 70. The arithmetic unit 70 is supplied with a composite video signal from the DL 67 and a color signal from the BPF 68. In the computing unit 70, D
By calculating the difference between the composite video signal from L69 and the color signal from BPF 68, the luminance signal is calculated and output.

In the above-described comb filter, Y / C separation is performed based on the following principle. That is, as shown in FIG. 8, the data obtained by sampling the composite video signal at the clock synchronized with the color subcarrier (hereinafter, appropriately referred to as sampling data) is the sampling data of one frame before when the color signal is focused. And has the property of being in the opposite phase. Therefore, the sampling data
If the difference between the delayed sampling data obtained as a result of delaying by the frame and the sampling data (not delayed) is obtained, the difference becomes the color signal. Then, if the color signal is subtracted from the sampling data, the subtracted value becomes a luminance signal.

[0006]

By the way, the above-described property holds true for delayed sampling data obtained by delaying sampling data by exactly one frame, and does not hold if the delay amount deviates by one clock.
Therefore, the delayed sampling data needs to be obtained by delaying the sampling data by exactly one frame.

In the NTSC system, a sampling clock for obtaining sampling data is Y /
C separation, ease or synthesis, while the line (horizontal scanning lines), in consideration of ease of processing between frames, usually color clock (color 4 times the frequency 4f _SC subcarrier frequency f _SC sub A clock synchronized with the carrier wave) is used. In this case, when the frequency of the horizontal synchronizing signal is represented by f _H , in the NTSC system, f _SC is 455/2 times f _H , so that the sampling clock and the horizontal synchronizing signal (hereinafter, appropriately referred to as H ( Horizontal) pulse) and the equation 4
The relationship represented by f _SC = 910f _H is established.

Since the number of lines in one frame is 525, when a 4f _SC clock is used, the delay time of one frame corresponds to 910 × 525 clocks.
Therefore, in the conventional comb filter, the 4f _SC clock is counted by 910 × 525, and the sampling data is read / written from / to the frame buffer 106 at that timing, so that the sampling data is delayed exactly by one frame. It was designed to do.

Therefore, if the quantization accuracy of the sampling data is set to 8 bits, for example, the frame buffer 1
6 is 8 × 525 × 910 bits, that is, about 3.
A memory having a capacity as large as 6 M (mega) bits was required.

Further, in this case, since the device is actually constructed by using two 2M-bit memories, the use of the memory is wasteful.

Therefore, there is a method of delaying the sampling data by storing only the video section of the composite video signal in the frame buffer 106 among the sampling data. That is, in order to perform Y / C separation, as shown in FIG.
As shown in, the entire composite video signal including a synchronization section such as H pulse and color burst is not required, and only a video section (effective video image section) excluding the synchronization section is sufficient.
Therefore, as shown in FIG. 9B, if only the video section of the composite video signal of the sampling data is stored in the frame buffer 106, the frame buffer 106 has a capacity of about 3 Mbits. Memory can be used.

However, when the entire composite video signal is stored in the frame buffer 106, the position (timing) at which the writing is started is arbitrary and 910 × 5.
While it suffices to delay by 25 clocks, as described above, when only the video section of the composite video signal is stored in the frame buffer 106, the start position of the video section of the sampled composite video signal And it is necessary to recognize the end position.

The start position and end position of this video section can be recognized, for example, based on the H pulse of the composite video signal, and the H pulse can be recognized by using a conventional sync separation circuit (analog circuit). , Can be obtained from the composite video signal. However, since the H pulse output from the sync separation circuit is asynchronous with the 4f _SC clock for sampling the composite video signal, the H pulse is used as a start point and an end position of the video section in a comb filter which is a digital circuit. To use it for recognition,
The H pulse must be synchronized with the 4f _SC clock. That is, for example, as shown in FIG. 10, an HD (Horizont) obtained by latching an H pulse according to a 4f _SC clock by a D-flip-flop.
al Drive) Must be a pulse.

In this case, as shown in FIG. 11, if the H pulse (FIG. 11 (A)) has no jitter and its period is always constant, the 4f _SC clock (FIG. 11 (B)) is set to 910.
An HD pulse (FIG. 11C) can be obtained each time counting is performed. However, in practice, there is always some jitter in the output of any high-performance sync separation circuit, so the timing of the rising edge of the H pulse and the 4f _SC clock (hereinafter, simply referred to as a clock) When the rising timing is very close to each other, the HD pulse has a jitter of ± 1 clock even if the H pulse has a small amount of jitter (for example, several nanoseconds). (In the NTSC system, f _SC is 3.579545 MHz, so ± 1 clock is ± 1 / (4 × 3.579545 ×
10 ⁶ ), that is, approximately ± 70 ns).

That is, as shown in FIG. 12, when the H pulse (FIG. 12 (A)) has jitter, its period is not always constant, and therefore the 4f _SC clock (FIG. 12 (B)) is set to 910. Not only when counting the number of times, but when counting 911 times or 909 times, for example, the HD pulse (see FIG.
(C)) may be obtained.

Therefore, although the period of 1H is 910 clocks, the period of HD pulses may be 909 clocks or 911 clocks. Then, based on such an HD pulse, the start position and end position of the video section are detected, the sampling data of the section is stored in the frame buffer 106, and the sampling data is read after 910 × 525 clocks have elapsed. However, the delay time is not the time for one frame. That is, in this case, the sampling data is exactly 1
It was difficult to delay the frame.

When the delay time of the sampling data is deviated from one frame by one clock, the three-dimensional comb filter cannot perform accurate Y / C separation, and as a result, the image resolution is reduced. Deterioration or color bleeding occurs.

Therefore, in order to avoid such deterioration of image quality, conventionally, as described above, a frame buffer capable of storing at least one frame of sampling data including not only a video section but also a synchronization section. 1
06 had to be used as a delay line.

The present invention has been made in view of such a situation, and makes it possible to eliminate the jitter contained in a periodic signal such as an H pulse.

[0020]

According to another aspect of the present invention, there is provided a jitter removing circuit for comparing the phases of a generating means for generating a pulse having a predetermined constant period, a pulse generated by the generating means and an input signal. A comparing means and a judging means for judging whether or not the cycle of the input signal is stable based on the comparison result of the comparing means; and a pulse or an input signal generated by the generating means based on the judgment result of the judging means. And a selecting means for selecting one of the
The phase of the pulse is controlled according to the output of the selecting means.

In the comb filter according to the third aspect, the removing means counts in synchronization with the clock, and when a predetermined clear signal is input, the count value is reset to generate a pulse. Counting means for outputting as a horizontal synchronizing signal from which jitter has been removed, detecting means for detecting a predetermined period including a timing at which the count value of the counting means becomes a value corresponding to the cycle of the horizontal synchronizing signal, and detection by the detecting means Whether the horizontal synchronizing signal timing is included in the predetermined period detected by the detecting means based on the comparison result of the comparing means and the comparing means for comparing the predetermined predetermined period with the timing of the horizontal synchronizing signal. The pulse output from the counting means when the timing of the determining means and the timing of the horizontal synchronizing signal are included in the predetermined period detected by the detecting means. When the timing of the selected horizontal synchronizing signal is not included in the predetermined period detected by the detecting means, the horizontal synchronizing signal is selected, and the selected signal is supplied to the counting means as a predetermined clear signal. And having.

In the video signal processing device according to the present invention, the removing means compares the phases of the generating means for generating a pulse having a predetermined constant period, the pulse generated by the generating means, and the synchronizing signal. Means and a comparing means based on the comparison result of the comparing means, a judging means for judging whether or not the cycle of the synchronizing signal is stable, and based on the judging result of the judging means, the pulse or the synchronizing signal generated by the generating means. Selecting means for selecting either one of the above, and the generating means controls the phase of the pulse in accordance with the output of the selecting means.

In the jitter removing circuit according to the first aspect, the generating means generates a pulse having a predetermined constant period, and the comparing means compares the phase of the pulse generated by the generating means with the phase of the input signal. It is done like this. The judging means judges whether the cycle of the input signal is stable based on the comparison result of the comparing means, and the selecting means judges the pulse or the input signal generated by the generating means based on the judgment result of the judging means. It is designed to select either one of them. In this case, the generating means controls the phase of the pulse in response to the output of the selecting means.

In the comb filter according to the third aspect of the present invention, the counting means counts in synchronization with the clock, and when a predetermined clear signal is input, the count value is reset to generate a pulse. , The horizontal synchronizing signal from which the jitter has been removed is output, and the detecting means detects a predetermined period including the timing at which the count value of the counting means becomes a value corresponding to the cycle of the horizontal synchronizing signal. The comparing means compares the predetermined period detected by the detecting means with the timing of the horizontal synchronizing signal, and the judging means detects the timing of the horizontal synchronizing signal by the detecting means based on the comparison result of the comparing means. It is designed to determine whether it is included in a predetermined period. The selecting means selects the pulse output by the counting means when the timing of the horizontal synchronizing signal is included in the predetermined period detected by the detecting means, and the timing of the horizontal synchronizing signal is the predetermined timing detected by the detecting means. When it is not included in the period, the horizontal synchronizing signal is selected, and the selected signal is supplied to the counting means as a predetermined clear signal.

In the video signal processing device according to the fourth aspect, the generating means generates a pulse having a predetermined constant period,
The comparing means is adapted to compare the phase of the pulse generated by the generating means with the phase of the synchronizing signal. The judging means judges whether or not the cycle of the synchronizing signal is stable based on the comparison result of the comparing means, and the selecting means judges the pulse or the synchronizing signal generated by the generating means based on the judgment result of the judging means. It is designed to select either one of them. In this case, the generating means controls the phase of the pulse in response to the output of the selecting means.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below, but before that, in order to clarify the correspondence between each means of the invention described in the claims and the following embodiments. The features of the present invention are described as follows by adding a corresponding embodiment (however, an example) in parentheses after each means.

That is, the jitter removing circuit according to claim 1 is a jitter removing circuit for removing the jitter contained in the periodic input signal, and is a generating means for generating a pulse of a predetermined constant period (for example, FIG. Timing generation circuit 2 shown in FIG.
Alternatively, the timing generation circuit 81 and the like shown in FIG. 6) and a comparison means (for example, the phase comparison circuit 3 shown in FIG. 1) for comparing the phases of the pulse generated by the generation means and the input signal.
Alternatively, the determination means (for example, the determination circuit 4 shown in FIG. 1 or the determination circuit 4 shown in FIG. 1, or 6) and a selection means (for example, the selection circuit shown in FIG. 1) for selecting either the pulse generated by the generation means or the input signal based on the determination result of the determination means. 5 and the switch 84 shown in FIG. 6), and the generating means controls the phase of the pulse in accordance with the output of the selecting means.

In the jitter removing circuit according to the second aspect, the input signal is a horizontal synchronizing signal of the composite video signal, and the generating means counts in synchronization with the color subcarrier of the composite video signal, and the predetermined clearing is performed. Counting means for resetting the count value and outputting a pulse when a signal is input (for example, a 10-bit counter 21 shown in FIG. 1)
And a detection means (for example, 906 to 910 detection circuit 23 shown in FIG. 1) for detecting a predetermined period including a timing when the count value of the counting means becomes a value corresponding to the cycle of the horizontal synchronizing signal. The comparing means compares the predetermined period detected by the detecting means with the timing of the horizontal synchronizing signal, and the determining means determines that the timing of the horizontal synchronizing signal is
Whether the period of the horizontal synchronizing signal is stable or not is determined depending on whether it is included in the predetermined period detected by the detecting unit, and the selecting unit determines the timing of the horizontal synchronizing signal by the predetermined period detected by the detecting unit. When included in the period, the pulse output by the counting unit is selected, and when the timing of the horizontal synchronizing signal is not included in the predetermined period detected by the detecting unit, the horizontal synchronizing signal is selected and the selected signal is It is characterized in that it is supplied to the counting means as a predetermined clear signal.

A comb filter according to claim 3 is a comb filter for separating a luminance signal and a chrominance signal from a composite video signal, wherein the composite video signal is clocked in synchronization with its color subcarrier. Sampling means for sampling (for example, the sampling circuit 63 shown in FIG. 5).
Etc.) and a horizontal sync signal detecting means for detecting the horizontal sync signal of the composite video signal (for example, the sync separation circuit 6 shown in FIG.
1), removing means for removing the jitter contained in the horizontal synchronizing signal detected by the horizontal synchronizing signal detecting means (for example, the jitter removing circuit 64 shown in FIG. 5), and the horizontal for which the jitter is removed by the removing means. Video signal section detection means for detecting the video signal section of the composite video signal in response to the synchronization signal (for example, the video section detection circuit 65 shown in FIG. 5).
A delay means (for example, the frame buffer 66 shown in FIG. 5) that delays the signal in the video signal section detected by the video signal section detecting means by one frame; and the output of the delay means and the signal in the video signal section. Calculation means for calculating the luminance signal and the color signal based on the above (for example, the calculator 67, the BPF 68, the DL 69, and the calculator 7 shown in FIG. 5).
0, etc.), the removing means counts in synchronization with the clock, and when a predetermined clear signal is input, the count value is reset and the pulse is subjected to horizontal synchronization with jitter removed. Counting means for outputting as a signal (for example, 10-bit counter 21 shown in FIG. 1)
And a detection unit (for example, 906 to 910 detection circuit 23 shown in FIG. 1) that detects a predetermined period including the timing when the count value of the counting unit becomes a value corresponding to the cycle of the horizontal synchronizing signal, and the detection unit. Comparing means for comparing the predetermined period detected by the signal with the timing of the horizontal synchronizing signal (for example, the D-flip-flop 31 shown in FIG. 1).
And a judgment means for judging whether the timing of the horizontal synchronizing signal is included in the predetermined period detected by the detection means based on the comparison result of the comparison means (for example, the 4-bit U / D counter 41 shown in FIG. 1). ) And the timing of the horizontal synchronizing signal are included in the predetermined period detected by the detecting means, the pulse output by the counting means is selected, and the timing of the horizontal synchronizing signal is detected in the predetermined period detected by the detecting means. If it is not included in the above, a horizontal synchronizing signal is selected, and the selecting signal is provided as a predetermined clear signal to the counting means (for example, the switch 51 shown in FIG. 1). .

A video signal processing device according to a fourth aspect is a video signal processing device for processing a composite video signal, and a removing means for removing a jitter of a synchronization signal included in the composite video signal (for example, in FIG. 5). The jitter removing circuit 64 shown in FIG. 2) is provided, and the removing means synchronizes the generating means (for example, the timing generating circuit 2 shown in FIG. 1) that generates a pulse of a predetermined constant period with the pulse generated by the generating means. Comparison means for comparing the phase with the signal (for example, the phase comparison circuit 31 shown in FIG. 1) and determination means for determining whether or not the cycle of the synchronization signal is stable based on the comparison result of the comparison means (for example, , And the selecting means (for example, the discriminating circuit 4 shown in FIG. 1) for selecting one of the pulse and the synchronizing signal generated by the generating means based on the determination result of the determining means. And a selection such as a circuit 5) shown in 1, generating means, in response to the output of the selection means, and controls the pulse phase.

Of course, this description does not mean that each means is limited to the above.

FIG. 1 shows a configuration example of a jitter removal circuit to which the present invention is applied. The jitter removing circuit is composed of an input unit 1, a timing generating circuit 2, a phase comparing circuit 3, a discriminating circuit 4, and a selecting circuit 5, and is, for example, an H pulse (H _in H of a composite video signal as a periodic input signal. ) From which the jitter is removed, and the pulse fh synchronized with the color subcarrier of the composite video signal (carrier whose frequency is f _SC ) is output.

That is, the input unit 1 includes D-flip-flops (hereinafter, appropriately referred to as D-FFs) 11 to 14 and AND.
It is composed of gates 15 and 16. D-FF
11 to 14 are connected in series by connecting the output terminal Q to the input terminal D in the subsequent stage,
From its output terminal Q, H input to its input terminal D
(High) or L (Low) level is clock terminal CK
For example, the clock input to the above is latched and output at the rising edge timing. The inverted output terminal XQ of each of the D-FFs 11 to 14 (indicated by a bar (-) above Q in FIG. 1) outputs the inverted level of the output terminal Q. It is designed to be done. Further, an H pulse (in this embodiment, an H level pulse, for example) is input to the input terminal D of the D-FF 11 in the first stage, and clocks of the D-FFs 11 to 14 are supplied. A clock having a frequency 4f _SC , which is four times as high as the color subcarrier, is input to the terminal CK.

The AND gates 15 and 16 are both 2-input 1-output AND gates, and one input terminal of the AND gate 15 is the inverting output terminal XQ of the D-FF 12,
The other input terminal is the output terminal Q of the D-FF 11,
Each is connected. Therefore, when the H pulse is input to the input section 1 from the output terminal of the AND gate 15, the timing of the rising edge of the H pulse (to be precise, after the H pulse becomes the H level, 4 f _SC From the timing when the clock first goes to the H level), a pulse that goes to the H level for a period of one clock (time to count the clock of 4f _SC once) is output. Also, AN
The output terminal of the D gate 15 is connected to the clock terminal CK of the D-FF 31 which constitutes the phase comparison circuit 3 described later.

One input terminal of the AND gate 16 is D
-The output terminal Q of the FF13 and the other input terminal are D
Each of them is connected to the inverting output terminal XQ of the -FF14. Therefore, from the output terminal of the AND gate 16, A
A pulse obtained by delaying the pulse output from the ND gate 15 by 2 clocks is output. Also, the AND gate 16
The output terminal of is connected to the terminal a of the switch 51 which constitutes the selection circuit 5 described later.

The timing generation circuit 2 includes a 10-bit counter (hereinafter, simply referred to as a counter) 21, 91.
0 detection circuit (hereinafter, simply referred to as a detection circuit) 2
2, 906 to 910 detection circuits (hereinafter, appropriately, simply referred to as detection circuits) 23, and a period corresponding to a time of counting 910 times, for example, a 4f _SC clock as a pulse having a predetermined constant period, that is, A pulse having a period of H pulse without jitter (a pulse having a period of 1H accurately) is generated.

That is, the counter 21 is a 10-bit counter having an input terminal IN, an output terminal OUT, a pulse output terminal POUT, and a clear terminal CLR, and the input terminal IN has the D constituting the input section 1 described above. -FF1
4f _SC input to 1 to 14 clock terminals CK
The same clock as the clock is input. Then, the counter 21 is, for example, at the rising edge timing of the 4f _SC clock input to its input terminal IN (hence, in synchronization with the color subcarrier),
The count value is incremented by 1, and the count value is output from the output terminal OUT.
It is adapted to be output to the detection circuits 22 and 23. Further, the counter 21 has its clear terminal CLR.
When, for example, an H level (a predetermined clear signal) is input, the count value is reset to 0 and a predetermined pulse width (for example, 1) is output from the pulse output terminal POUT.
A pulse fh of a clock (such as a pulse width corresponding to the clock period of 4f _SC ) is output.

The signal (output of the AND gate 16 or the detection circuit 22) supplied to the terminal a or b selected by the switch 51 is input to the clear terminal CLR of the counter 21. .

The detection circuit 22 detects the timing when the count value of the counter 21 reaches 910. In this case, for example, the output normally at the L level is output for a predetermined period (for example, The H level is set only for one clock (a period corresponding to a 4f _SC clock). The output of the detection circuit 22 is supplied to the terminal b of the switch 51, so that when the switch 51 selects the terminal b, the clear value CLR of the counter 21 has a count value of 910.
Since the H level is input every time, the pulse fh is output from the pulse output terminal POUT every time the 4f _SC clock is counted 910 times. That is, the pulse fh having a period of 1H is accurately output.

The detection circuit 23 is adapted to detect a predetermined period including the timing when the count value of the counter 21 becomes 910 which is a value corresponding to the period of the H pulse having no jitter. That is, in this embodiment, the detection circuit 23
Is, for example, the count value of the counter 21 is 90
The period from 6 to 910 is detected, and during this period, for example, the output that is normally L level is set to H level. Detection circuit 23
The output of is supplied to the input terminal D of the D-FF 31.

The phase comparison circuit 3 is composed of a D-FF 31, and compares the phase of the pulse fh generated by the timing generation circuit 2 with the phase of the H pulse, and when the phases of both are substantially the same (described later). As described above, in the present embodiment, when the phase shift between the two is within ± 2 clocks), for example, H
When the phase difference between the two is large (in the present embodiment, the phase difference between the two is larger than ± 2 clocks, for example), the L level is output.

That is, the output of the detection circuit 23 or the AND gate 15 is supplied to the input terminal D or the clock terminal CK of the D-FF 31, respectively. The output level of the detection circuit 23 is latched and output from the output terminal Q of the AND gate 15 when the output of the AND gate 15 reaches the H level. Therefore,
The output level of the output terminal Q of the D-FF 31 is detected at the timing of the rising edge of the H pulse (more accurately, the timing at which the 4f _SC clock first becomes the H level after the H pulse becomes the H level). When it is included in the period detected by the circuit 23, it becomes H level, and when it is not included, it becomes L level.

The output from the output terminal Q of the D-FF 31 is a 4-bit U / D constituting the discrimination circuit 4 described below.
It is adapted to be supplied to an (Up / Down) counter (hereinafter simply referred to as a counter) 41.

The discriminating circuit 4 is composed of a counter 41, and judges whether or not the period of the H pulse is stable based on the output of the phase comparing circuit 3. That is, the clock terminal CK of the counter 41 has D-
The output terminal Q of the FF11 is connected to the counter 41
When the input level of the input terminal is H or L level, the count value is incremented or decremented by 1 at the timing when the input level of the clock terminal CK becomes H level.

Therefore, in the counter 41, when the timing of the rising edge of the H pulse is included in the period detected by the detection circuit 23, the count value is incremented by 1 at the timing of the H pulse, and When the timing of the rising edge of the H pulse is not included in the period detected by the detection circuit 23,
The count value is deincremented by 1 at the timing of the H pulse.

The counter 41 is, for example, a 4-bit counter, which resets the count value to 0 when the input level to its input terminal changes from the L level to the H level, and also changes the input level to the H level. When the level changes from the L level to the L level, the count value is reset to 15. Then, the counter 41 sets the output level to H level when carry or borrow occurs.
Alternatively, it is set to L level.

Therefore, the output level of the counter 41 is H
The timing of the rising edge of the pulse is the detection circuit 23.
When the state included or not included in the period detected by is continued for a time corresponding to 16 H pulses, the state becomes H level or L level.

Here, the state where the timing of the rising edge of the H pulse is included in the period detected by the detection circuit 23 means that the count value of the counter 21 is 90.
When it is in the range of 6 to 910, there is an H pulse, and therefore, when such a state lasts for a time corresponding to 16 H pulses, the period of the H pulse becomes stable. It can be said that

The output of the counter 41 is supplied to the switch 51.

The selection circuit 5 includes the switch 5 as described above.
The switch 51 is configured to select the terminal a or b when the output of the counter 41 is at L or H level. Therefore, when the state in which the timing of the rising edge of the H pulse is included in the period detected by the detection circuit 23 continues for a time corresponding to 16 H pulses, the terminal 51 is selected by the switch 51, which causes , Pulse fh output by the counter 21
Then, basically at the same timing, the pulse output from the detection circuit 22 (when the switch 51 selects the terminal b, the pulse is output from the detection circuit 22 as described above, and the pulse fh is Since it is output, strictly speaking,
The pulse fh is output slightly later than the pulse output from the detection circuit 22), but is supplied to the clear terminal CLR of the counter 21.

Further, when the timing of the rising edge of the H pulse is not included in the period detected by the detection circuit 23 for a time corresponding to 16 H pulses, the terminal 51 is selected by the switch 51. As a result, the pulse output from the AND gate 16 is supplied to the clear terminal CLR of the counter 21 at a timing delayed by about 4 clocks from the timing of the H pulse.

Next, the operation will be described with reference to the timing charts of FIGS. Now, FIG.
As shown in the lower part of FIG. 2B, the clock of 4f _SC as shown in FIG. 2B is input, and the H pulse (to the H level at the timing immediately before the count value reaches 908) ( 2 (A)) is input. In this case, the level of the output terminal Q of the D-FF 11 changes from the L level to the H level when the count value of the counter 21 reaches 908, and the level of the inverting output terminal XQ of the D-FF 12 changes to the counter 21. Count value of 9
Since the H level is changed to the L level at the timing of becoming 09, the AND gate 15 outputs a pulse whose H level is kept only during the period from 908 to 909 as shown in FIG. 2C. To be done.

As described above, the AND gate 16 outputs a pulse delayed from the output pulse of the AND gate 15 by 2 clocks, so that its output is as shown in FIG.
As shown in (D), the count value of the counter 21 is 91.
It becomes H level for only one clock after it becomes 0.

When the count value of the counter 21 reaches 910, the detection circuit 22 outputs a pulse having a pulse width of 1 clock. Therefore, in this case, the detection circuit 22 outputs a pulse having the same phase as the pulse output from the AND gate 16 (FIG. 2 (E)).

On the other hand, the output of the detection circuit 23 is the counter 2
While the count value of 1 (FIG. 2 (B)) is 906 to 910, it becomes H level as shown in FIG. 2 (F). Therefore, in this case, the output pulse of the AND gate 15 (FIG. 2C) is the output pulse of the detection circuit 23 (FIG. 2C).
It is located at the center of (F).

Output of the detection circuit 23, that is, the D-FF 31
While the level of the input terminal D of is at H level,
When the output of the AND gate 15, that is, the level of the clock terminal CK of the D-FF 31 becomes the H level, the D-FF 3
The level of the output terminal Q of No. 1 is, as shown in FIG.
Since it becomes H level, if this state continues for a time corresponding to 16 H pulses, carry occurs in the counter 41, and as a result, H level is supplied from the counter 41 to the switch 51. .

The output of the counter 41 of the switch 51 is H level.
When it is at the level, since the terminal b is selected, the output of the detection circuit 22 is supplied to the clear terminal C of the counter 21. As a result, the pulse output terminal P of the counter 21
As shown in FIG. 2H, a pulse fh is output from OUT every time the count value reaches 910.

In this case, as described above, since the output of the AND gate 16 and the output of the detection circuit 22 are in phase, whichever output is supplied to the clear terminal C of the counter 21, The pulse fh is synchronized with the H pulse. Therefore, by clearing (resetting) the count value of the counter 21 with the output of the detection circuit 22 (in this case, the output of the detection circuit 22 is equivalent to the pulse fh), the pulse fh is accurately measured. It has a period of 1H in synchronization with the H pulse.

Next, jitter occurs in the H pulse, and as a result, as shown in FIG. 3A, an H pulse whose rising edge timing is delayed by, for example, one clock from that in the case of FIG. 2A is generated. It is assumed that the input has been made. In this case, the level of the output terminal Q of the D-FF 11 is the counter 2
When the count value of 1 (FIG. 3B) becomes 909, the L level changes to the H level, and the D-FF1
The level of the second inverting output terminal XQ changes from the H level to the L level at the timing when the count value of the counter 21 reaches 910.
As shown in, a pulse that outputs a H-level signal only when the count value of the counter 21 is between 909 and 910 is output. That is, the AND gate 15 outputs a pulse at a timing delayed by one clock as compared with the case of FIG.

Therefore, from the AND gate 16 as shown in FIG.
A pulse is output at a timing delayed by one clock from the case in (D) (FIG. 3D).

Then, the count value of the counter 21 is 91
When it becomes 0, the detection circuit 22 outputs a pulse having a pulse width of 1 clock. Therefore, in this case, the detection circuit 22 outputs a pulse whose phase is advanced by one clock from the pulse output from the AND gate 16 (FIG. 3 (E)).

On the other hand, the output of the detection circuit 23 is the counter 2
While the count value of 1 (FIG. 3B) is between 906 and 910, the same FIG.
As shown in (F), it becomes H level. Therefore, in this case, the output pulse of the AND gate 15 (FIG. 3C) is
From the center of the output pulse (FIG. 3 (F)) of the detection circuit 23,
Although it is positioned to the right by one clock, the timing of the rising edge of the output pulse of the AND gate 15 is included in the range of the output pulse of the detection circuit 23 (the period when the detection circuit 23 is at the H level). (This is because the timing of the rising edge of the H pulse is
(Corresponding to being included in the period detected by the above), the level of the output terminal Q of the D-FF 31 (FIG. 3 (G))
Becomes H level, as in the case of FIG.

Since the output level of the D-FF 31 remains at the H level, the output level of the discrimination circuit 4 does not change at the H level, and therefore the switch 51 also remains in the state in which the terminal b is selected. As a result, since the output of the detection circuit 22 is continuously supplied to the clear terminal C of the counter 21,
The pulse fh described in FIG. 2 continues to be output also from the pulse output terminal POUT of the counter 21 (FIG. 3).
(H)).

In this case, as described above, the output of the AND gate 16 and the output of the detection circuit 22 are substantially in phase with each other (due to the jitter included in the H pulse,
Even if either output is supplied to the clear terminal C of the counter 21 by only 1 clock (since it is shifted by about 70 ns as described above in this embodiment), the pulse fh becomes H It is synchronized with the pulse. Therefore,
By clearing (resetting) the count value of the counter 21 by the output of the detection circuit 22, the pulse fh is accurately 1H.
It has a period of, and is synchronized with the H pulse. That is, even if jitter occurs in the H pulse, the pulse fh is
It is possible to obtain the one with the jitter removed.

As described above, the output pulse of the AND gate 16 is delayed in phase by two clocks from the output pulse of the AND gate 15, and the phase of the output of the AND gate 16 and the output of the detection circuit 22 is further increased. , The output pulse of the AND gate 15 is
The output pulse timing of the AND gate 15 is set to the center of the output pulse of the detection circuit 23 because it is positioned at the center of the output pulse of the detection circuit 23 which becomes H level when the count value of is 906 to 910. From ± 2 in the range of ± 2 clocks (even if the H pulse has jitter in the range of ± 2 clocks), the pulse fh has no jitter (exactly has a period of 1H) and is synchronized with the H pulse. You can get things. That is, since the H pulse contains a slight amount of jitter, the H pulse is changed to D-FF.
It is possible to remove ± 1 clock jitter that occurs when the data is latched (sampled) in 11.

In order to remove the jitter in a wider range, the range of the count value of the counter 21 detected by the detection circuit 23 is widened and the D-F constituting the input section 1 is formed.
A D-FF may be added between F12 and F13.

Next, for example, when the input of the H pulse is started, or in place of the H pulse input so far,
When the input of the H pulse of the composite video signal of different channels is started, the H pulse rarely exists in the range of ± 2 clocks around the timing shown in FIG. Lies outside such a range. Therefore, the operation of the jitter removal circuit when an H pulse is input at a timing outside the range of ± 2 clocks around the timing shown in FIG. 2A will be described with reference to the timing chart of FIG. To do.

Now, when the terminal b is selected by the switch 51, the timing of the rising edge is as shown in FIG.
As shown in (A), it is assumed that an H pulse that is delayed by, for example, 4 clocks from the case in FIG. 2A is input. In this case, the level of the output terminal Q of the D-FF 11 is
Assuming that the counter 21 is not reset, at the timing when the count value (FIG. 4B) becomes 912,
From the L level to the H level, and the level of the inverting output terminal XQ of the D-FF 12 changes from the H level to the L level at the timing when the count value of the counter 21 becomes 913. As shown in FIG. 4C, the count value of the counter 21 is 912 to 913.
A pulse that is at the H level is output only during the period. That is, A
From the ND gate 15, as compared with the case in FIG.
A pulse is output at a timing delayed by 4 clocks.

Therefore, from the AND gate 16 as well, FIG.
Pulses are output at a timing delayed by 4 clocks from the case in (D) (FIG. 4 (D)).

When the count value of the counter 21 reaches 910, the detection circuit 22 outputs a pulse having a pulse width of 1 clock. Therefore, in this case, the detection circuit 22 outputs a pulse whose phase is advanced by 4 clocks from the pulse output from the AND gate 16 (FIG. 4 (E)).

On the other hand, the output of the detection circuit 23 is the counter 2
While the count value of 1 (FIG. 4 (B)) is 906 to 910, FIG. 4 similar to the case in FIG. 2 (F).
As shown in (F), it becomes H level. Therefore, in this case, the output pulse of the AND gate 15 (FIG. 4C) is
From the center of the output pulse (FIG. 2 (F)) of the detection circuit 23,
The timing of the rising edge of the output pulse of the AND gate 15 is not included in the range of the output pulse of the detection circuit 23 (this means that the timing of the rising edge of the H pulse is detected). This is equivalent to being not included in the period detected by the circuit 23), so the level of the output terminal Q of the D-FF 31 (FIG. 4 (G)) changes from H level to L level.

When this state continues for a time corresponding to 16 H pulses, a borrow occurs in the counter 41,
As a result, from the counter 41 to the switch 51,
L level is supplied.

In the switch 51, the output of the counter 41 is L
When the level becomes the level, the terminal a is selected, so that the output of the AND gate 16 is supplied to the clear terminal C of the counter 21. As a result, the counter 21 is reset not at the timing of 910 clocks, but at the timing delayed by 4 clocks from this, and by this,
From the pulse output terminal POUT of the counter 21, as shown in FIG.
As indicated by the dotted line in (H), the pulse fh is output when the count value reaches 914.

That is, when the phase of the output of the AND gate 16 and the output of the detection circuit 22 are greatly deviated (in the embodiment of FIG. 1, they are deviated by ± 3 clocks or more), the output of the detection circuit 22 is changed. , Is supplied to the clear terminal C of the counter 21 and the pulse fh is output at that timing, the pulse fh is asynchronous with the H pulse (the phase is greatly deviated).

Therefore, in this case, by supplying the output of the AND gate 16 to the clear terminal C of the counter 21 and outputting the pulse fh at that timing,
It controls the phase of pulse fh, which causes pulse fh
Are synchronized with the H pulse (the phases are (substantially) matched).

When the counter 21 is reset at the timing of the output pulse of the AND gate 16, the relationship between the timing of the next H pulse and the count value of the counter 21 is almost as shown in FIG. , The phase of the output of the AND gate 16 and the phase of the output of the detection circuit 22 become substantially the same as shown in FIG. 2 or FIG.

Therefore, in this case, the level of the output terminal Q of the D-FF 31 (FIG. 4 (G)) changes from the L level to the H level. When this state continues for a time corresponding to 16 H pulses, a carry occurs in the counter 41, and as a result, the counter 41 sends an H pulse to the switch 51.
Levels will be supplied.

Therefore, thereafter, as described with reference to FIG. 2 or 3, for example, it is possible to obtain the pulse fh that is jitter-free (having a cycle of 1H accurately) and is synchronized with the H pulse. become.

Next, FIG. 5 shows the configuration of an embodiment of a television receiver to which the present invention is applied. In addition, in the figure, among the blocks constituting the television receiver, a portion relating to a three-dimensional comb filter for performing Y / C separation of a composite video signal is shown, and other blocks are known ones. Since it is configured in the same way as
The illustration is omitted. Further, in the figure, parts corresponding to those in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted below as appropriate.

A composite video signal of a predetermined channel, which is detected and demodulated by a detection circuit (not shown), is input to the sync separation circuit 61. Then, the sync separation circuit 61 separates (detects) an H pulse as a sync signal from the input composite video signal and outputs it to the jitter removal circuit 64. The clock generation circuit 62 is
A clock having a frequency 4f _{SC which is} four times as high as the color subcarrier of a television broadcast signal conforming to the NTSC system is generated and supplied to the sampling circuit 63 and the jitter removing circuit 64.

The sampling circuit 63 receives the 4f _SC clock from the clock generation circuit 62 and also receives the same signal as the composite video signal input to the sync separation circuit 61. Then, the sampling circuit 63 uses, for example, a clock generation circuit 62 as a clock that synchronizes the input composite video signal with the color subcarrier.
The sampling data obtained as a result of sampling is output to the video section detection circuit 65 at the timing of the clock of 4f _SC supplied from.

The jitter removing circuit 64 is configured as shown in FIG. 1 and removes the jitter contained in the H pulse from the sync separating circuit 61 and outputs it to the video section detecting circuit 65. That is, the jitter removal circuit 64 has a pulse fh synchronized with the H pulse and having a period of exactly 1H.
Is output to the video section detection circuit 65. The video section detection circuit 65 responds to the pulse fh supplied from the jitter removal circuit 64 by the sampling circuit 6
From the sampling data supplied from No. 3, only the portion corresponding to the video section of the composite video signal is detected and supplied to the frame buffer 66, the arithmetic unit 67, and the DL 69. The frame buffer 66 stores the sampling data from the video section detecting circuit 65, delays the sampling data by a time corresponding to one frame, and outputs the delayed sampling data to the calculator 67.

In the comb filter constructed as described above, the sync separation circuit 61 and the sampling circuit 6
3, the composite video signal of a predetermined channel is supplied from the detection circuit. In the sync separation circuit 61, an H pulse is detected from the input composite video signal, and the jitter removal circuit 6
4 is output. In the jitter removing circuit 64, the jitter of ± 1 clock generated in principle by sampling (latching) the H pulse from the sync separation circuit 61 with the clock of 4f _SC generated by the clock generation circuit 62,
Removed as described with reference to FIGS.
As a result, a pulse fh having a period of 1H and synchronized with the H pulse is accurately output to the video section detection circuit 65.

On the other hand, in the sampling circuit 63, the input composite video signal is sampled at the timing of the clock of 4f _SC supplied from the clock generation circuit 62, and the resulting sampling data is the video section detection circuit 65. Is output to. In the video section detection circuit 65, only the portion corresponding to the video section of the composite video signal is detected from the sampling data supplied from the sampling circuit 63 in response to the pulse fh supplied from the jitter removal circuit 64, and the frame buffer is detected. 66, calculator 6
7 and DL69. Frame buffer 6
6, the sampling data from the video section detection circuit 65 is temporarily stored and read out after the elapse of a predetermined time (in the NTSC system, 910 × 525 clocks as described above), the time corresponding to one frame. The delayed sampling data is delayed by only 1 and is output to the calculator 67. Hereinafter, as described in FIG. 7, the brightness signal or the color signal is output from the computing unit 70 or the BPF 68, respectively.

As described above, since the pulse fh is synchronized with the H pulse and has a cycle of 1H, that is, 910 clock cycles, the sampling data of the video section stored in the frame buffer 66 is 910. The delay time can be accurately set to the time for one frame by reading after the elapse of only x525 clocks. Therefore, in the case where only the sampling data of the video section is stored in the frame buffer 66, Accurate Y / C
Separation can be performed. Further, as a result, it is possible to use the frame buffer 66 having a smaller capacity than that of the conventional one (about 3 Mbits as described above).

Since the jitter removing circuit 64 can also remove the jitter of the sync separation circuit 61 itself, it is also possible to remove the jitter generated in the medium electric field or the weak electric field, for example.

Next, FIG. 6 shows another example of the configuration of the jitter removing circuit to which the present invention is applied. The jitter removal circuit of FIG. 1 is designed to remove the jitter generated by sampling the H pulse with the clock of 4f _SC , but the jitter removal circuit of FIG. It is designed to remove the included jitter itself. Further, also in this jitter removing circuit, the jitter is removed from the input signal according to the same principle as in the case of the jitter removing circuit of FIG.

The timing generating circuit 81 generates a pulse having a constant cycle, that is, a pulse having the same cycle as the cycle of the periodic input signal (pulse for removing jitter) input to the jitter removing circuit, and the phase comparing circuit 81. 82 and switch 8
4 is output to the terminal 84a. In addition,
An output of a switch 84 described later is supplied to the timing generation circuit 81, and the timing generation circuit 81 responds to the signal from the switch 84 by
The phase of the output pulse is controlled.

The phase comparison circuit 82 compares the phase of the pulse from the timing generation circuit 81 with the phase of the input signal and outputs the phase difference to the discrimination circuit 83.
The determination circuit 83 is configured to determine whether the cycle of the input signal is stable, based on the phase difference from the phase comparison circuit 82. That is, the determination circuit 83 determines that the cycle of the input signal is stable when the absolute value of the phase difference from the phase comparison circuit 82 is less than or equal to the predetermined threshold value SH.
The absolute value of the phase difference from the phase comparison circuit 82 is a predetermined threshold value S
If it is larger than H, it is determined that the cycle of the input signal is not stable. The determination result of the determination circuit 83 is supplied to the switch 84.

The switch 84 is adapted to select the terminal 84a or 84b, respectively, when it receives the judgment result from the judgment circuit 83 that the cycle of the input signal is stable or not stable. In the terminal 84b,
The input signal is supplied so that when the cycle of the input signal is stable or not stable, the timing generation circuit 81 is switched from the switch 84.
The pulse or input signal from is output.

In the jitter removing circuit configured as described above, the periodic input signal (pulse) is supplied to the phase comparison circuit 82 and the terminal 84b, and the timing generation circuit 81 generates the input signal. Pulses of the same cycle are supplied to the phase comparison circuit 82 and the terminal 84a.
The phase comparison circuit 82 obtains the phase difference between the pulse from the timing generation circuit 81 and the input signal, and outputs it to the discrimination circuit 83. The determination circuit 83 determines whether or not the cycle of the input signal is stable based on the phase difference from the phase comparison circuit 82, and the determination result is supplied to the switch 84.

When the switch 84 receives the determination result that the cycle of the input signal is stable or not stable from the determination circuit 83, it selects the terminal 84a or 84b, respectively.

Therefore, when the cycle of the input signal is not stable, the input signal supplied to the terminal 84b is directly output from the switch 84. This input signal is supplied to the timing generation circuit 81, and the timing generation circuit 81 controls so that the phase of the output pulse matches the phase of the input signal.

As a result, the pulse output from the timing generation circuit 81 matches the phase of the input signal, and as a result, the discrimination circuit 83 determines that the cycle of the input signal is stable. become. Therefore, the switch 84 switches from the terminal 84b to the terminal 84a, and the pulse output from the timing generation circuit 81, which is supplied to the terminal 84a, is output from the switch 84.

In this case, the pulse output from the timing generation circuit 81 is controlled so that its phase matches the phase of the input signal, and its cycle matches the cycle of the input signal. As a result, it is equal to the one obtained by removing the jitter contained in the input signal. Therefore, according to this jitter removing circuit, it is possible to remove the jitter contained in the periodic input signal.

The case where the present invention is applied to a television receiver has been described above. However, the present invention is applicable to, for example, a VTR (video tape recorder) in addition to the television receiver.
The present invention can be applied to any video signal processing device that processes a composite video signal such as a video camera.

[0097]

According to the jitter removing circuit of the first aspect and the video signal processing apparatus of the fourth aspect, the phase between the pulse having a predetermined constant period generated by the generating means and the periodic input signal. Are compared, and based on the comparison result, it is determined whether or not the cycle of the input signal is stable. Further, based on the determination result, either the pulse generated by the generating means or the input signal is selected by the selecting means and output. Then, the generating means controls the phase of the pulse corresponding to the output of the selecting means. Therefore, it is possible to obtain a pulse whose phase matches the phase of the input signal and whose cycle matches the cycle of the input signal. That is, it is possible to obtain a pulse from which the jitter is removed from the input signal.

According to the comb filter of the third aspect, the counting means performs counting in synchronization with the clock, and when a predetermined clear signal is input,
The count value is reset and a pulse is output. On the other hand, the detecting means detects a predetermined period including the timing when the count value of the counting means becomes a value corresponding to the cycle of the horizontal synchronizing signal. When the timing of the horizontal synchronizing signal is included in the predetermined period detected by the detecting unit, the pulse output by the counting unit is selected, and the timing of the horizontal synchronizing signal is set in the predetermined period detected by the detecting unit. If not included, the horizontal synchronizing signal is selected, and the selected signal is supplied to the counting means as a predetermined clear signal. Therefore, it is possible to obtain a pulse whose phase or cycle matches the phase or cycle of the horizontal synchronizing signal, respectively. That is, the jitter can be removed from the horizontal sync signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a jitter removal circuit of the present invention.

FIG. 2 is a timing chart for explaining the operation of the jitter removal circuit of FIG.

FIG. 3 is a timing chart for explaining the operation of the jitter removal circuit of FIG.

FIG. 4 is a timing chart for explaining the operation of the jitter removal circuit of FIG.

FIG. 5 is a block diagram showing a configuration of an embodiment of a television receiver (three-dimensional comb filter) to which the present invention is applied.

FIG. 6 is a block diagram showing the configuration of another embodiment of a jitter removal circuit to which the present invention is applied.

FIG. 7 is a block diagram showing a configuration of an example of a conventional comb filter.

FIG. 8 is a diagram for explaining the principle of Y / C separation performed by a comb filter.

FIG. 9 is a waveform diagram showing a composite video signal.

FIG. 10 is a diagram for explaining a method of synchronizing an H pulse with a 4f _SC clock.

FIG. 11 is a diagram for explaining a case where the H pulse has no jitter.

FIG. 12 is a diagram for explaining a case where the H pulse has jitter.

[Explanation of symbols]

 2 Timing generation circuit 3 Phase comparison circuit 4 Discrimination circuit 5 Selection circuit 21 10-bit counter 22 910 Detection circuit 23 906-910 detection circuit 31 D-flip-flop 41 4 bit U / D (up / down) counter 51 Switch 61 Sync separation circuit 62 Clock Generation circuit 63 Sampling circuit 64 Jitter removal circuit 65 Video section detection circuit 66 Frame buffer 67 Operation unit 68 BPF (Bandpass filter) 69 DL (Delay line) 70 Operation unit 81 Timing generation circuit 82 Phase comparison circuit 83 Discrimination circuit 84 Switch

Claims (4)

[Claims] 1. A jitter removing circuit for removing jitter contained in a periodic input signal, comprising: generating means for generating a pulse having a predetermined constant period; the pulse generated by the generating means; and the input. Comparing means for comparing the phase with the signal, based on the comparison result of the comparing means, determining means for determining whether the cycle of the input signal is stable, based on the determination result of the determining means, Selecting means for selecting either one of the pulse generated by the generating means or the input signal, wherein the generating means controls the phase of the pulse in response to the output of the selecting means. Characteristic jitter removal circuit. 2. The input signal is a horizontal synchronizing signal of a composite video signal, and the generating means counts in synchronization with a color subcarrier of the composite video signal, and receives a predetermined clear signal. Sometimes, the count value that resets the count value and outputs the pulse, and the detection that detects the predetermined period including the timing at which the count value of the count means becomes a value corresponding to the cycle of the horizontal synchronizing signal The comparing means compares the predetermined period detected by the detecting means with the timing of the horizontal synchronizing signal, and the judging means determines that the timing of the horizontal synchronizing signal is the detecting means. Depending on whether it is included in the predetermined period detected by, it is determined whether the cycle of the horizontal synchronization signal is stable, the selecting means, When the timing is included in the predetermined period detected by the detecting unit, the pulse output by the counting unit is selected, and the timing of the horizontal synchronizing signal is included in the predetermined period detected by the detecting unit. 2. The jitter removing circuit according to claim 1, wherein when there is no such signal, the horizontal synchronizing signal is selected, and the selected signal is supplied to the counting means as the predetermined clear signal. 3. A comb filter for separating a luminance signal and a chrominance signal from a composite video signal, the sampling means sampling the composite video signal at a timing of a clock synchronized with the color subcarrier. Horizontal sync signal detecting means for detecting a horizontal sync signal of the composite video signal, removing means for removing jitter contained in the horizontal sync signal detected by the horizontal sync signal detecting means, and jitter removing by the removing means. Corresponding to the horizontal synchronizing signal, a video signal section detecting means for detecting a video signal section of the composite video signal, and a signal of the video signal section detected by the video signal section detecting means is delayed by one frame. Delay means, and calculation means for calculating the luminance signal and the color signal based on the output of the delay means and the signal in the video signal section The removing means counts in synchronization with the clock, and when a predetermined clear signal is input, resets the count value and outputs a pulse to the jitter-removed horizontal synchronization signal. And a detection unit for detecting a predetermined period including a timing at which the count value of the counting unit is a value corresponding to the cycle of the horizontal synchronization signal, and a predetermined period detected by the detection unit. And comparing means for comparing the timing of the horizontal synchronizing signal with each other, based on the comparison result of the comparing means, whether the timing of the horizontal synchronizing signal is included in the predetermined period detected by the detecting means. When the judgment means and the timing of the horizontal synchronization signal are included in the predetermined period detected by the detection means, the counting hand When the pulse output by the above is selected and the timing of the horizontal synchronizing signal is not included in the predetermined period detected by the detecting means, the horizontal synchronizing signal is selected and the selected signal is changed to the predetermined clear signal. And a selection means for supplying the counting means. 4. A video signal processing device for processing a composite video signal, comprising: removing means for removing jitter of a synchronization signal included in the composite video signal, wherein the removing means generates a pulse having a predetermined constant period. Generating means for generating, a comparing means for comparing the phase of the pulse generated by the generating means with the synchronizing signal, and whether the cycle of the synchronizing signal is stable based on the comparison result of the comparing means. A determining means for determining whether or not, based on the determination result of the determining means, a selecting means for selecting one of the pulse generated by the generating means or the synchronization signal, the generating means, The video signal processing device, wherein the phase of the pulse is controlled according to the output of the selecting means.