JPH0983499A - Bit phase synchronous circuit, bit phase synchronizing device and data latch timing decision circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably output data latched in a most proper timing with respect to data and a clock signal whose mutual phase relation is unknown. SOLUTION: A pulse width generating circuit 1 makes a pulse width of input data of an NRZ signal from a data input terminal 0 narrow and provides an output of a 1st pulse width signal, a 2nd pulse width signal and delayed data delaying input data by a prescribed time. Even when mutual phase relation between the input data and n-phases clocks ϕ1 to ϕn being 1/n equal divisions of one clock width of the input data is unknown, shift registers 41 to 4n are used to match the top and the tail end to absorb phase fluctuation in m-bit width and data latched and outputted by latch timing decesion circuits 21 to 2n and phase align circuits 31 to 3n in the most proper timing are outputted stably from a selector 6 synchronously with the clock ϕ1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit phase synchronizing circuit, a bit phase synchronizing device, and a data latch timing judging circuit, which can be applied to, for example, high speed data transmission of 100 Mbit / s or more and data transmission timing judgment. Is.

[0002]

2. Description of the Related Art Conventionally, a large amount of data is exchanged between devices constituting a communication system. A clock signal for processing these data is distributed from the reference clock source to each device. In the conventional device having a low data rate, it was possible to easily reproduce and process the data signal transmitted from the transmission side device by using the clock distributed in the reception side device.

However, as the data signal rate increases,
Since the delay time difference between the data signal path and the clock signal distribution path is about the same as the time per data bit,
It becomes difficult to reproduce and process the data signal using the clock distributed on the receiving side.

Conventionally, as one means for solving such a problem, for example, a technique of a bit phase synchronizing circuit as disclosed in Japanese Patent Laid-Open No. 4-373230 has been proposed.

FIG. 2 is a block diagram of a bit phase synchronizing circuit according to the above-mentioned document. As shown in FIG. 2, this bit phase synchronization circuit generates a multi-phase clock by using a PLL circuit or the like on the receiving side, inputs continuous phase clocks to the latch circuits 100 to 102, and outputs the latch circuits. The data is latched at 100 to 102, the output thereof is input to the change point detection circuit 104, the change point of the data is detected by the change point detection circuit 104, and a clock having an appropriate phase is controlled by the selector control circuit 105. The selectors 106 to 108 make selections.

[0006]

However, in the above-mentioned conventional circuit, the change point of the input data is detected by the multi-phase clock, and the clock phase which seems to be able to latch the data stably is selected from the phase information. Therefore, there is a problem that it is not possible to judge whether or not the input data is properly latched.

Further, since the selector is used for clock selection, there is a problem that noise is convolved with the clock waveform unless the switching timing is adjusted.

From the above, when the mutual phase relationship between the input data and the clock is unknown, the bit phase synchronizing circuit can stably achieve the bit phase synchronization with the data latched at the most appropriate timing. It has been demanded to provide a data latch timing determination circuit applied to a bit phase synchronization circuit and the like, a small bit phase synchronization device for performing bit phase synchronization of parallel data transmission, and the like.

[0009]

Therefore, the invention of claim 1 provides a bit phase synchronizing circuit for performing bit phase synchronization between input data and a clock having the same frequency as the bit rate of the input data, which is characterized by the following features. With the above configuration, the above-mentioned problems are solved.

That is, according to the invention of claim 1, an n-phase clock forming means for phase-shifting the clock to form an n-phase (n is an integer of 3 or more) phase clock for phase determination, and the input data, A first pulse width signal for latching the input data, which is synchronized with the central portion of the high level period of the input data,
Either of the second pulse width signal for the input data latch synchronized with the central portion of the low level period of the input data, or both the first pulse width signal and the second pulse width signal. The data latch pulse forming means for forming a signal, and the input data and any one of the signals formed by the data latch pulse forming means are latched and output by using the clocks of the respective phases of the n-phase clocks. At the same time, a signal latch determination means for determining whether or not the values of these latch output signals match and outputting an n-phase match determination signal, and the latch output data corresponding to the respective latched phases are provided. A transfer means that transfers the n-phase clock by any one of the phases and outputs the transferred n-phase data, the n-phase coincidence determination signal, and the multiplication Using the clock of the phase used by the transfer means, select one of the phase data synchronized with the clock of the phase used by the transfer means from among the n-phase data transferred by the transfer means. And a phase synchronization determination output means for outputting.

By adopting such a configuration, even if the mutual phase relationship between the input data and the n-phase clock is unknown, the phase synchronization determination output means absorbs the phase fluctuation,
The data latched and output at the most appropriate timing can be stably and selectively output in synchronization with the clock of any phase. Therefore, in the bit phase synchronization of high-speed data, the data latched at the most appropriate timing can be output very stably.

The invention of claim 2 is the above-mentioned claim 1.
Of the phase synchronization determination output means shifts the n-phase data output from the transfer means by a shift register, shifts the phase to m (m is an integer of 2 or more) phases for phase fluctuation absorption, and outputs the phase-shifted data. This is the configuration.

By adopting such a structure, it becomes possible to easily absorb the phase fluctuation with an m-bit width in front and back.

Further, the invention of claim 3 is a bit phase synchronizing apparatus comprising a master bit phase synchronizing circuit for synchronizing bit phase with parallel data and a slave bit phase synchronizing circuit, wherein the master bit is synchronized. The phase-locked loop circuit is the first one of the parallel data.
3. The bit phase synchronizing circuit having the structure according to claim 1 or 2 is used for the data of 1., and an n phase clock and the n phase among these n phases are used for the slave bit phase synchronizing circuit. And a selection control signal for selectively controlling data of a phase synchronized with a clock of any one of the phases. The slave bit phase synchronization circuit is for performing bit synchronization with other data of the parallel data other than the first data, and uses the clocks of respective phases of the n-phase clocks to perform the above-mentioned synchronization. Slave signal latch means for latching and outputting other data other than the first data, and the latch output data corresponding to each of the latched phases are replaced with a clock of any one of n-phase clocks. Then, using the slave transfer means for outputting the transferred n-phase data and the phase clock used by the slave transfer means, the n-phase transfer means for the slave phase change is performed. Of the data, one of the phases of the data synchronized with the clock of the phase used by the slave transfer means is used as the master bit phase synchronization circuit. And a slave for phase synchronization determination output means for selectively outputting the selection control signal from a configuration synchronization bit phase.

By adopting such a configuration, it is possible to use the bit phase synchronizing circuit of claim 1 or 2 and the slave bit phase synchronizing circuit for parallel data whose phase relationship with the clock is unknown. Then, with the parallel data that absorbed the phase fluctuation and latched at the proper timing,
It is possible to output the synchronized clock.

Furthermore, the invention of claim 4 is a data latch timing determination circuit for determining whether or not the data latch timing of input data and a clock having the same frequency as the bit rate of the input data match. From the input data, the first pulse width signal for the input data latch synchronized with the central portion of the high level period of the input data, and the second pulse width signal for the input data latch synchronized with the central portion of the low level period of the input data. Pulse width signal, or data latch pulse forming means for forming either of the first pulse width signal and the second pulse width signal, and the input data using the clock. And one of the above signals formed by the data latch pulse forming means are latched out, and the values of these latched output signals are matched. Whether the outputs match determination signal is determined, in which a signal latch determination means for visually displaying the coincidence judgment signal as the matching determination result.

By adopting such a configuration, it is possible to confirm whether or not the input data and the clock match the data latch timing with a very simple configuration.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings.

[First Embodiment]: (Schematic Basic Structure): FIG. 1 is a functional block diagram showing a schematic basic structure of a bit phase locked loop circuit according to the first embodiment. In FIG. 1, the bit phase synchronization circuit is configured such that the number of phases of the internal clock is an n phase obtained by dividing one clock width into n equal parts and the phase fluctuation absorption width is m clock width. This bit phase synchronization circuit includes a pulse width forming circuit 1, latch timing determination circuits 21 to 2n, phase align circuits 31 to 3n, shift register circuits 41 to 4n, selectors 51 to 5n and 6, and a selector control circuit. 8 and.

The pulse width forming circuit 1 has a data input terminal 0
Narrow the pulse width of the input data of the NRZ signal from
It outputs a first pulse width signal, a second pulse width signal, and delay data obtained by delaying input data by a predetermined time. The first pulse width signal is a high level pulse width of the input data formed by the logic gate circuit to have a narrow pulse width. In short, the first pulse width signal is formed so as to correspond to the timing near the center so that the first pulse width signal is latched at the timing near the center where the signal level of the input data is the highest level. Even if such a pulse width is formed,
The pulse period is unchanged and is the same as the original data rate.

The second pulse width signal is obtained by forming the low-level pulse width of the input data into a narrow pulse width by the logic gate circuit. In other words, the second pulse width signal is formed so as to correspond to the timing near the center because the second pulse width signal is latched at the timing near the center where the signal level is the most sure during the low level period of the input data. Even if such a pulse width is formed, the pulse cycle is not changed and is the same as the original data rate.

The pulse width forming circuit 1 is arranged such that "the width for narrowing the pulse widths of the first pulse width signal and the second pulse width signal is the minimum that the latch circuit used can normally latch the input data. A setup time or a hold time or more, and a width in which the generated first pulse width signal and second pulse width signal can be latched by at least one phase clock of n phase clocks. Let's.

N latch timing determination circuits 21 to 2
When the pulse width forming circuit 1 supplies the first pulse width signal, the second pulse width signal, and the delay data, n is latched by clocks φ1 to φn, respectively. The three latched data are collated, and if all have the same value, it is determined that the clock phase input to the latch timing determination circuit is appropriate for latching the input data. The clock phase input to the latch timing determination circuit determines that the timing for latching the input data is inappropriate, and outputs the determination result as the timing determination result signal D2. The timing determination result signal D2 and the delay data D1 output from the latch timing determination circuits 21 to 2n are given to the phase align circuits 31 to 3n, respectively.

N phase align circuits 31 to 3n
Are for replacing the phases of the timing determination result signal and the delay data with the phase of the clock φ1, respectively. Therefore, in the phase align circuit 3i, the latch timing determination circuit 2i of the previous block operates at the clock φi, and the output data (timing determination result signal and delay data) can be latched most stably in the first stage. The clock input φi-1 is used for latching, the clock input φi-2 is used for latching in the next stage, and similarly, the operation of advancing the clock phase is performed in the subsequent stage, and finally the clock input φ1 is used for latching. These operations can be realized with a smaller number of stages as the value of i of the phase align circuit 3i is smaller, but in order to maintain the mutual plane relationship of the phase align circuits 31 to 3n, the number of stages is n of the phase align circuit 3n. -1 step.

Here, the "face" means "data of timing latched by n rising edges from one rising edge of the clock φ1 to the rising edge of the next clock φn".

N phase align circuits 31 to 3n
Outputs the timing determination result signal and the delay data which are added to the phase of the clock φ1 and supplies the timing determination result signal to the selector control circuit 8 and the delay data to the shift register circuits 41 to 4n.

The n shift register circuits 41 to 4n are
Each of the delay data is output by 1 bit by m bits of data shifted by m bits and output to the selectors 51 to 5n. The selector control circuit 8 is initialized by the reset signal input from the reset signal input terminal 7, and as an initial setting, the selectors 51 to 5n output from the shift register circuits 41 to 4n “the integer bit closest to m / 2”. Select the output side ”and the selector 6 is the selector 5
A control signal for selecting "data latched at an integer clock phase closest to n / 2" from the outputs of 1 to 5n is output and given.

Further, the selector control circuit 8 compares the phase determined to be proper by the timing determination result signal output of the phase align circuits 31 to 3n with the currently selected phase, and determines the newly determined phase. Decide the face,
A control signal is generated based on it. The phase align circuit 31 used to generate this control signal
Control signals are sent in synchronization with the timings at which the delayed data outputs of the phase align circuits 31 to 3n output at the same timings as the timing determination result signal outputs of to 3n appear at the inputs of the selectors 51 to 5n. The control signal thus generated is input to the control signal inputs of the selectors 51 to 5n and the selector 6. Each of the selectors 51 to 5n selects one of the m pieces of data by the control signal from the selector control circuit 8 and supplies it to the selector 6. The selector 6 selects one from the data of n clock phases by the control signal from the selector control circuit 8 and outputs it to the data output terminal 9.

(Timing of n-phase clock): FIG.
Are the latch timing determination circuits 21 to 2n, the phase align circuits 31 to 3n, and the shift register circuit 4 described above.
3 is a timing chart of n-phase clocks given to 1 to 4n and a selector 8. In FIG. 3, n
The phase clocks φ1 to φn are used in the circuit shown in FIG. 1. When the pulse period of the clock φ1 is T, the clock φ2 is delayed by T / n phase with respect to the clock φ1. is there. Similarly, clock φ3
Is delayed by 2 × T / n phase with respect to the clock φ1, and delayed by T / n phase with respect to the clock φ2.

That is, in the phase relationship between the clocks φi and φi + 1, the phase difference is 1 / n × 1 clock width, and φ
The phase of φi + 1 is delayed with respect to i. The frequencies of the clocks φ1 to φn and the bit rate of the data input from the data input terminal 0 are the same, but the phase relationship is unknown.

The clocks φ1 to φn are connected to the clock inputs of the latch timing determination circuits 21 to 2n, respectively,
In addition, the clock φ1 is the phase align circuit 31 to 3n.
, The clock φ2 is connected to the clock inputs of the phase align circuits 33 to 3n, and the clock φi is connected to the clock inputs of the phase align circuits 3 (i + 1) to 3n. Here, although the phase align circuits 31 and 32 have only a single-phase clock input, the phase align circuits 33 to 3n are provided with a plurality of phase clock inputs, and the number thereof is, for example, i- in the case of the phase align circuit 3i. It has one clock input. Furthermore,
The clock input φ1 is the reference clock of the functional block shown in FIG. 1, and is connected to the clock inputs of the shift register circuits 41 to 4n and the selector control circuit 8.

(Operation): The input data supplied to the data input terminal 0 is pulse-width formed by the pulse-width forming circuit 1, and the first pulse width signal, the second pulse width signal and the input data are input for a predetermined time. The delayed data delayed is output and given to the latch timing determination circuits 21 to 2n. On the other hand, when the above-mentioned data is supplied, clocks φ1 to φ
n is provided to the latch timing determination circuits 21 to 2n. With the clocks φ1 to φn, the above-mentioned first
The pulse width signal, the second pulse width signal and the delay data are latched, and these three signals are collated,
If the values are all the same, it is determined that the clock phase input to the latch timing determination circuit is appropriate as the timing for latching the input data, while if the values are different, the clock input to the latch timing determination circuit The phase is determined to be inappropriate as the timing for latching the input data, and the determination result is output as the timing determination result signal D2. At the same time, the delay data is also output as the latch output D1.

The delay data D1 and the timing judgment result signal D2 are used for n phase align circuits 31 to 31.
It is supplied to any corresponding phase-aligned circuit of n. Further, each of the n phase align circuits 31 to 3n has a clock φ1 for changing the phase of the timing determination result signal and the delay data to the phase of the clock φ1.
~ Φn are supplied, and clock input φi is first input in the first stage so that these clocks can be latched most stably.
-1 latches, the next stage latches with the clock input φi-2, the clock stage advances in the same way in the latter stage, and finally the clock input φ1 latches. These actions are performed. , The smaller the value of i of the phase align circuit 3i is, the smaller the number of stages can be realized, but in order to maintain the mutual surface relationship of the phase align circuits 31 to 3n,
The number of stages is n- of the phase align circuit 3n, which is the most multistage.
The delay data D1a is latched and output in accordance with one stage, is given to the shift register circuits 41 to 4n, and the other timing judgment result signal is given to the selector control circuit 8.

The delay data D1a is m bit by bit in the shift register circuits 41 to 4n according to the clock φ1.
The phase of bit is shifted, and m delay data D1a
m is output and provided to the selectors 51 to 5n. At the same time, at the time of reset, the selectors 51 to 51 are operated based on the timing determination result signal given to the selector control circuit 8.
5n to m / 2 from the outputs of the shift register circuits 41 to 4n
Select the output surface of the integer bit closest to
Generates a control signal from the outputs of the selectors 51 to 5n to select the data latched at the integer clock phase closest to n / 2. After the reset, a control signal that follows the fluctuation of the data at any time is generated. It is generated and given to the selectors 51 to 5n and the selector 6.

As a result, the delay data D1am given to the selectors 51 to 5n are selected and output, and the selected and output data are given to the selector 6,
Any one of the data is selected and output by the control signal from the selector control circuit 8 at any optimum timing.

(Effect of First Embodiment): With the above configuration, the mutual phase relationship between the input data and the n-phase clocks φ1 to φn obtained by dividing one clock width of this input data into n equal parts is unknown. Even if the shift register circuit 41
~ 4n absorbs phase fluctuations of m-bit width both before and after, and at the most appropriate timing, the phase align circuit 3
The data latched by 1 to 3n can be stably output from the selector 6 in synchronization with the clock φ1.

[Second Embodiment]: A second embodiment of the present invention is a more detailed configuration of the above-described first embodiment to show specific features of the present invention. . Therefore,
In the second embodiment, “a description will be given assuming that the number of phases of the internal clock is four phases obtained by dividing one clock width into four equal parts and the phase fluctuation absorption width is three clock width”.

FIG. 4 and FIG. 5 are functional block diagrams of the bit phase synchronizing circuit of the second embodiment. FIG. 4 shows the main components of the bit phase synchronizing circuit, and FIG. 5 particularly shows the detailed configuration of the selector control circuit 8. Figure 4,
In FIG. 5, the bit phase synchronization circuit includes a pulse width formation circuit 10 and data latch timing determination circuits 210-2.
40, the phase align circuits 310 to 340, the shift register circuits 410 to 440, and the selectors 51 to 54.
And a selector 6 and a selector control circuit 8.

The pulse width forming circuit 10 includes delay elements 11 to 1
3 and 3-input AND circuit 14 and 3-input OR circuit 1
And 5. In the pulse width forming circuit 10, the input data from the data input terminal 0 is given to the delay element 11, the AND circuit 14, and the OR circuit 15. The delay element 11 is a delay circuit that delays by 1 / 4T when 1 pulse width of the input data of the NRZ signal is T, delays the input data by 1 / 4T, and delays the delayed data by the next delay element 12. And another delay element 13,
It is also given to the AND circuit 14 and the OR circuit 15.

The delay element 12 also delays the input data by the time of 1 / 4T, and outputs the delay data obtained by further delaying the delay data from the delay element 11 by the time of T / 4 and outputs it to the AND circuit 14. , OR circuit 15. The delay element 13 is a delay circuit that delays the input data by the same input / output delay amount A as the AND circuit 14 and the OR circuit 15, and further delays the delay data from the delay element 11 by the delay time A to obtain the delay data. It is what is output. The waveform of this delay data is shown in FIG. The AND circuit 14 obtains a logical product from the input data, the T / 4 delay data output from the delay element 11 and the 2 × T / 4 delay data output from the delay element 12 to narrow the pulse width of the high level signal. 1 pulse width signal is output.

The waveform of this first pulse width signal is shown in FIG.
This is shown in FIG. The OR circuit 15 ORs the input data, the T / 4 delay data output from the delay element 11 and the 2 × T / 4 delay data output from the delay element 12,
A second pulse width shaping signal in which the pulse width of the low level signal is narrowed is output. This second pulse width signal is shown in FIG.
(C). The pulse width formation circuit 10 outputs the delay data, the first pulse width signal and the second pulse width signal to the data latch timing determination circuits 210 to 240.
Give to.

Data latch timing determination circuit 210-
Clocks 240 each having the same circuit configuration are provided with the delay data, the first pulse width signal and the second pulse width signal, and are further phase-shifted into four phases, respectively.
Input delay data is latched at ~ φ4. FIG. 7 is a timing chart showing the timing relationship between these clocks φ1 to φ4. In FIG. 7, clock φ1
Is a clock (pulse) cycle T, and this cycle T is
It corresponds to 1 bit of the input data. The clock φ2 is delayed in phase by T / 4 time with respect to the clock φ1. The clock φ3 is delayed in phase by 2 × T / 4 time with respect to the clock φ1, and is delayed in phase by T / 4 time with respect to the clock φ2. Clock φ4
Is delayed by 3 × T / 4 time with respect to the clock φ1, delayed by 2 × T / 4 time with respect to the clock φ2, and delayed by T / 4 time with respect to the clock φ3.

Specifically, clock φ1 is applied to data latch timing determination circuit 210, clock φ2 is applied to data latch timing determination circuit 220, clock φ3 is applied to data latch timing determination circuit 230, and clock φ4 is applied. It is provided to the data latch timing determination circuit 240. The data latch timing determination circuit 2 uses the clocks φ1 to φ4 having such a phase relationship.
Reference numerals 10 to 240 latch the delay data, the first pulse width signal and the second pulse width signal.

Here, the configuration of the data latch timing determination circuit 210 will be described as a representative. The data latch timing determination circuit 210 includes latch circuits 211 to 213.
And a code matching detection circuit 214. The clock φ1 is applied to the latch circuits 211 to 213. The latch circuit 211 latches the delayed data at the clock φ1 and outputs the latch output signal to the sign coincidence detection circuit 214. The latch circuit 212 latches and outputs the first pulse width signal at the clock φ1, and
The latch output signal is supplied to the code coincidence detection circuit 214. The latch circuit 213 latches and outputs the second pulse width signal at the clock φ1 and provides the latch output signal to the code coincidence detection circuit 214.

The code coincidence detection circuit 214 includes the latch circuit 2
11 latch output data, the latch output signal of the latch circuit 212, and the latch output signal of the latch circuit 213, these three data and signals are collated, and if all have the same value, they are input to the latch timing determination circuit. The latched timing determination circuit determines that the timing for latching the input data is appropriate, and the clock phase input to the latch timing determination circuit is incorrect when the input data is latched. Judgment is made, the judgment result is outputted as a timing judgment result signal D2, and it is given to the phase align circuit 310. The latch output data of the latch circuit 211 is output as delay data D1 and given to the phase align circuit 310.

Other data latch timing determination circuit 22
The circuits 0 to 240 have the same circuit configuration as the data latch timing determination circuit 220 described above, and are latched by the phase-shifted clocks φ2 to φ4 to obtain the delay data D1.
And the timing determination result signal D2 is generated and given to the phase align circuits 320 to 340.

Four phase align circuits 310 to 34
0 indicates the data latch timing determination circuits 210 to 240.
The phase alignment circuit 310 changes the phase of the delay data D1 given by the above and the timing determination result signal D2 to the phase of the clock φ1.
Change using the. Phase align circuit 320
Changes using the clock φ1. The phase-align circuit 330 uses the clocks φ1 and φ2 to change over. The phase align circuit 340 has clocks φ1 to φ1.
Use φ3 to change the transfer.

Four phase align circuits 310 to 34
Since the circuit configuration of 0 is the same except that the input clocks are different, the phase align circuit 3 is representatively shown.
The functions of 10 will be described. Phase align circuit 310
Is composed of latch circuits 311 to 316.
The clock φ1 is applied to these latch circuits 311 to 316. Latch circuits 311 to 311 connected in series
313 latches the delay data D1 by the clock φ1 and outputs it as delay data synchronized with the clock φ1. The other of the latch circuits 314 to 3 connected in series
16 latches the timing judgment result signal D2 and outputs it as the timing judgment result signal D2 synchronized with the clock φ1.

Four shift register circuits 410 to 440
Receives the delay data from the phase align circuits 310 to 340, respectively, and clocks φ1 to generate 3 bits each.
Three pieces of delay data in which the phases of the bits are shifted are output and given to the selectors 51 to 54. Shift register circuit 410
.. to 440 have the same circuit configuration, the circuit configuration of the shift register circuit 410 will be representatively described. The shift register circuit 410 is composed of four latch circuits 411 to 414 connected in series,
The input delay data is shifted by 1 bit by the clock φ1, and the output of the latch circuit 412 and the latch circuit 41 are shifted.
3 and the output of the latch circuit 414 are connected to the selector 51.
Give to.

The selector control circuit 8 outputs the timing judgment result signal D2 from the phase align circuits 310 to 340.
And a control signal for the selectors 51 to 5n,
The control signal for the selector 6 is generated and given. Specifically, as shown in FIG. 5, the selector control circuit 8 includes a data selection determining circuit 16, an up / down counter 17, a 4-bit latch circuit 1000, shift register circuits 1110-1140, and selectors 141-1.
44 and an output timing adjusting circuit 1300.

The data selection decision circuit 16 is composed of a combination circuit, and a truth table thereof is shown in FIG. FIG.
The meaning of each signal of is shown below. The a, b, c, and d inputs are phase-aligned circuits 310 to 340 that latch external data with clocks φ1, φ2, φ3, and φ4, respectively.
When the signal is "1", the timing is proper, and when "0", the timing is not proper. A, B, C, and D inputs respectively correspond to clocks φ1, φ2, φ3, and φ4, and indicate the clock phase selected immediately before from the 4-bit latch circuit 1000. If the signal is "1", it indicates that the clock phase has been selected. From FIG.
Of the 4-bit inputs of A, B, C, and D, the signal that becomes "1" is only 1 bit. When the reset signal is input, the B input becomes "1" and the A, C, D inputs become "0". Here, it is not necessary that B becomes "1" when the reset signal is input.

The data selection decision circuit 16 causes the 4-bit latch circuit 1000 to hold the value of the decided phase selection control signals Qa, Qb, Qc, Qd as the immediately preceding phase selection control signal, and shift register. Circuit 1
110 to 1140.

The up / down counter 17 sets the operation as shown in FIG. 9, and when the reset signal is input, the Q2 output is initialized to "1" and the Q1 and Q3 outputs are initialized to "0". Set. Then, when the up / down signal from the data selection determining circuit 16 is fetched and "1" is received at the up input, the Qi output is counted up to Qi + 1 output, and when the down input is received "1", the Qi output is changed to Qi. Count down to -1 output.

The 4-bit latch circuit 1000 has phase selection control signals Qa, Qb, Q from the data selection decision circuit 16.
The c and Qd outputs are held as the immediately preceding phase selection control signal and are again applied to the A, B, C and D inputs of the data selection determination circuit 16.

Shift register circuits 1110-1140
Is a phase selection control signal Q from the data selection determination circuit 16.
The outputs of a, Qb, Qc, and Qd are each shifted by 1 bit at the clock φ1, and three shift outputs are provided to the selectors 141 to 144, respectively. Shift register circuit 1
Since 110 to 1140 have the same circuit configuration, the circuit configuration of the shift register circuit 1110 will be described as a representative. The shift register circuit 1110 is composed of latch circuits 1111 to 1114 connected in series, and the latch circuit 1111 receives the phase selection control signal Qa from the data selection determination circuit 16 and the shift output of the latch circuit 1112. The shift output of the latch circuit 1113 and the shift output of the latch circuit 1114 are given to the selector 141.

According to the output control signal of the output timing adjusting circuit 1300, the selectors 141 to 144 output the i-th data input signal if the i-th control signal is "1". That is, the selectors 141 to 144 select and output the phase control signal of an appropriate surface, and this signal is output by the selector 6
Give to.

The output timing adjusting circuit 1300 includes latch circuits 1301 to 1303 and 1311 to 13 with a selector.
13, 1321-1323, and latch circuits 1331, 1
332 and an OR circuit 1333. The output timing adjusting circuit 1300 adjusts the timing of the surface selection control signal input from the up / down counter 17, and then outputs the control signal to the selector 5 and the selector 14.
Control signals are given to 1-144. FIG. 10 shows timings of control signals and control signals. The phases of these control signals are shifted by 1 bit, and by doing so, the same data is prevented from being read twice when the surface phase is advanced.

Specifically, the output timing adjusting circuit 13
00, the Q3 input signal is transferred to the latch circuit 133.
2 data input and latch circuits with selectors 1301 and 13
02 is applied to the first data input of the latch circuit 1331 and the first data inputs of the latch circuits with selectors 1311 and 1312.
1 input signal is latch circuits with selectors 1321 and 1322
Is provided to the first data input of.

Further, the second data input of the latch circuit with selector 1321 is given a high level signal, the second data inputs of the latch circuits with selector 1301 and 1311 are given a low level, and the latch circuit with selector 1301 is provided.
Is supplied to the second data input of the latch circuit with selector 1302, the output of the latch circuit with selector 1311 is supplied to the second data input of the latch circuit with selector 1312, and the output of the latch circuit with selector 1321 is the selector. It is provided to the second data input of the attached latch circuit 1322.

The data output of the latch circuit 1331 is given to the input of the 2-input OR 1333, and the output of the latch circuit 1332 is given to the input of the 2-input OR 1333 and the control signal inputs of the latch circuits with selectors 1302, 1312, 1322. The output of the 2-input OR 1333 is given to the control signal inputs of the latch circuits with selectors 1301, 1311, and 1321. Further, the latch circuit with selector 1302
Is used as the data input of the latch circuit 1303 and the control signal output of the output timing adjusting circuit 1300. The output of the latch circuit with selector 1312 is the latch circuit 1313.
Data input and output of the control signal of the output timing adjusting circuit 1300. The output of the latch circuit with selector 1322 is used as the data input of the latch circuit 1323 and the control signal output of the output timing adjusting circuit 1300.

The output of the latch circuit 1303 is used as the control signal output of the output timing adjusting circuit 1300, and the output of the latch circuit 1313 is the output timing adjusting circuit 13.
00 as a control signal output, and the output of the latch circuit 1323 as a control signal output of the output timing adjusting circuit 1300. Clock φ1 is output timing adjustment circuit 13
00 is applied to the clock inputs of all latch circuits used internally.

(Operation): Next, the operation of the bit phase synchronizing circuit shown in FIGS. 4 and 5 will be described. First, the NRZ digital signal is input to the data input terminal 0 and becomes the input data of the pulse width forming circuit 10. Pulse width forming circuit 10
In, the input data is given to the delay element 11, the 3-input AND 14 and the 3-input OR 15. The delay element 11 delays the input data. The delay amount is set to 1/4 phase.

The delay amount may be more or less than this. The output signal of the delay element 11 is the delay elements 12, 13
And 3-input AND14 and 3-input OR15. The delay amount of the delay element 12 is set to 1/4 phase.
The delay amount may be more or less than this. The output signal of the delay element 12 is a 3-input AND14 and a 3-input OR1.
Given to 5. The delay amount of the delay element 13 is a 3-input AND
It is set to the same value as the delay amount of 14 and 3 inputs OR15. The delay amounts of the 3-input AND 14 and the 3-input OR 15 are set to have the same value.

The output signals of the delay element 13, the 3-input AND 14 and the 3-input OR 15 are output as the delay data of the output of the pulse width forming circuit 10, the first pulse width signal, and the second pulse width signal, respectively. The waveforms of the delay data, the first pulse width signal, and the second pulse width signal of the pulse width forming circuit 10 are shown in FIG.

As shown in FIG. 6, the first pulse width signal with respect to the input data narrows the rising and falling sides of the high level period by 1/4 phase. Similarly, the second pulse width signal narrows the low level period by 1/4 phase.

Delay data of the pulse width forming circuit 10,
The first pulse width signal and the second pulse width signal are supplied to the latch timing determination circuits 210 to 240, respectively.

The clocks φ1 to φ4 are input to the latch timing determination circuits 210 to 240, respectively. In the latch timing determination circuits 210 to 240, the input data is latched by the input clocks φ1 to φ4, the data is output, it is determined whether the latch timing is proper, and the determination result is output.

For example, the latch timing determination circuit 210
In the case of, the delay data, the first pulse width signal, and the second pulse width signal are given to the latch circuits 211 to 213, respectively. These input signals are the latch timing determination circuit 2
It is latched by the clock φ1 input to 10 and output. The output signals of the latch circuits 211 to 213 are supplied to the sign coincidence detection circuit 214, and the output signal of the latch circuit 211 is output as the data output of the latch timing determination circuit 210. Sign matching detection circuit 214
The output signal of 1 is output as "1" when it is determined that the timing is a proper timing as the timing determination result signal of the latch timing determination circuit 210, and "0" is output when it is determined to be incorrect.

Latch timing determination circuits 210-240
The data output of each is the phase align circuit 310-310.
Is supplied to the latch timing determination circuit 210 to 340.
The timing determination result signals of the outputs of 240 are given to the phase align circuits 310 to 340, respectively.

The clock φ1 is the first to third clock inputs of the phase align circuit 310 and the first, second and third clock inputs of the phase align circuit 320.
The clock φ2 is supplied to the second and third clock inputs of the phase align circuit 330 and the third clock input of the phase align circuit 340.
30 first clock input and phase-aligned circuit 3
A second clock input of 40 and clock φ3
Are applied to the first clock input of the phase align circuit 340.

In the phase align circuits 310 to 340, the latch timing of each input data is aligned with the clock φ1. For example, the phase alignment circuit 3
In the case of 40, both the data 1 input and the data 2 input, which are the inputs, are latch circuits 341, 3 which are the first latch stage.
Latched at 44. The latch timing is latched by the clock φ3 which is the first clock input of the phase align circuit 340. The reason for latching at the phase of the clock φ3 is that since the data 1 input is the data latched at the clock φ4, it is stably latched at the clock of the phase φ3 which is advanced by ¼ phase from the clock φ4.

The outputs of the latch circuits 341 and 344 are latched by the latch circuits 342 and 345 which are the next latch stage. The latch timing is the phase align circuit 34.
It is latched at the clock φ2 which is the second clock input of 0. Further, those outputs are latched by the latch circuits 343 and 346 which are the next latch stage. The latch timing is latched by the clock φ1 which is the third clock input of the phase align circuit 340. These output signals are output as the data 1 output and the data 2 output of the phase align circuit 340, respectively.

By such an operation, the phase of the data input to the phase align circuit is stably transferred to the clock φ1 which is the reference clock. The data 1 outputs of the phase align circuits 310 to 340 are supplied to the data inputs of the shift register circuits 410 to 40, respectively.

The shift register circuits 410 to 440 have the same function as a normal shift register. For example, in the case of the shift register circuit 410, the four latch circuits 411 to 414 are provided as described above, and the data is generated by the clock φ1. The shifted output signals of the latch circuits 412 to 414 are output as the first to third data outputs of the shift register circuit 410, respectively.

The first, second and third data outputs of the shift register circuits 410 to 440 are given to the first, second and third data inputs of the selectors 51 to 54 of 3: 1 respectively.

The respective data outputs of the phase align circuits 310 to 340 are a to d of the data selection decision circuit 16.
Given to input. Qa to Q of the data selection decision circuit 16
The d outputs are shift register circuits 1100 to 114, respectively.
0 data input and 4-bit latch circuit 1000
Given to the fourth data input. 4-bit latch circuit 1
At 000, the data supplied to the first, second, third, and fourth data inputs are latched by the clock φ1 and output as the first to fourth data outputs.

First to fourth of the 4-bit latch circuit 1000
Of the data selection decision circuit 16 from A to
Given to the D input. A to d of the data selection determination circuit 16
The input shows the determination result of the timing of latching the external data with each of the clocks φ1 to φ4. If the signal is “1”, the timing is proper, and if the signal is “0”, the timing is incorrect. The A to D inputs correspond to the clocks φ1 to φ4, respectively, and show the clock phase selected immediately before. If the signal is "1", it indicates that the clock phase has been selected. 4 of A to D inputs
Of the bit inputs, the signal that becomes "1" is only 1 bit. When the reset signal is input, the B input becomes "1" and the A to D inputs become "0". Here, it is not necessary that B becomes "1" when the reset signal is input.

In the data selection decision circuit 16, for example, assuming that the clock phase selected immediately before is the phase located inside (the B or C input is "1"), the corresponding phase is judged to be the current phase. Is "1", the clock phase selected immediately before is held, and if the corresponding phase is "0" and the adjacent phase is "1", the phase is changed to be selected, and the corresponding phase is selected. The phase and its adjacent phase are "0"
Then, if there is "1" in any other phase, it is changed to select that phase, and if there is no phase judged to be correct at present, the clock phase selected immediately before is held.

On the other hand, assuming that the clock phase selected immediately before is a phase located outside (the A or D input is "1"), if the corresponding phase is judged to be "1" at the presently judged appropriate phase. , If the clock phase selected immediately before is held, the corresponding phase is “0”, and the phase adjacent to the inside is “1”, that phase is changed to be selected, and the corresponding phase and the inside If the phase adjacent to is “0” and the phase at the other end is “1” with respect to the clock phase selected immediately before, that phase is selected, and in this case the surface is considered to have moved, The selection is also changed.

When the phase selection is changed from A to D, it is considered that the data has been advanced with respect to the clock, and "1" is output to the up output terminal to advance the surface. . On the contrary, when the phase selection is changed from D to A, it is considered that the data is delayed with respect to the clock, "1" is output to the down output terminal, and the surface is delayed. The corresponding phase, the adjacent phase inside and the phase at the other end are "0"
Then, if there is "1" in any other phase, the phase is changed so as to be selected, and if there is no phase judged to be proper at present, the clock phase selected immediately before is held.

The values of the phase selection control signals Qa to Qd determined by the data selection determining circuit 16 in this way are held in the 4-bit latch circuit 1000 as the immediately preceding phase selection control signal. In addition, the surface selection change signal up and down output signals are respectively up and down counter 1
7 up / down input terminal.

In the up / down counter 17, first, when the reset signal is input, the Q2 output is set to "1"
1, Q3 output is initialized to "0". Thereafter, when "1" is input to the up input, the Qi output is counted up to Qi + 1 output, and when "1" is input to the down input terminal, the Qi output is counted down to Qi-1 output. Further, when an up signal is given at i = 3 and a down signal is given at i = 1, self reset (RST) is applied so that the Q2 output becomes "1".

Outputs Q1 to Q3 of the up / down counter 17 are surface selection control signals, and the output timing adjusting circuit 1
The data is input as the first, second, and third data inputs of 300, respectively. The output timing adjusting circuit 1300 adjusts the timing of the input surface selection control signal and then outputs it as a control signal. This timing is shown in FIG.
Is shown in

Here, the control signal is a surface selection control signal for the input data, and the control signal is a surface selection control signal for the phase control selection signal. These phases are shifted by 1 bit, so that it is possible to prevent double reading of the same data when the surface phase is advanced.

Thus, the output timing adjusting circuit 1300
The control signals, which are the surface selection control signals output from the respective selectors, are input to the control signal inputs of the 3: 1 selectors 51 to 54, and the control signals are the 3: 1 selectors 141, respectively.
To 144.

3: 1 selectors 51-54, 141-1
At 44, for example, if the i-th control signal input is "1", the i-th data input is output. As a result, 3: 1 selectors 51 to 54 select the data of the appropriate surface,
A phase control signal of an appropriate surface is selected by the 3: 1 selectors 141 to 144, and the phase control signal is applied to the 4: 1 selector 6.
To the data output terminal 9. The data of the proper phase is selected by the 4: 1 selector 6 and is output to the data output terminal 9.

(Effect of Second Embodiment): With the above configuration, the mutual phase relationship between the input data and the four-phase clocks φ1 to φ4 obtained by dividing one clock width of this input data into four equal parts is unknown. Even if the shift register circuit 41
It is possible to absorb the phase fluctuation of 3 bit width in front and back by 0 to 440 and to stably output the data latched and output by the phase align circuits 310 to 340 at the most appropriate timing from the selector 6 in synchronization with the clock φ1. it can. Moreover, stable output can be achieved without noise.

(Modification): FIG. 11 is a block diagram showing a first modification of the pulse width forming circuit 10 shown in FIG.
As shown in FIG. 11, in the first modification, the 3-input OR 15 of the pulse width forming circuit 10 of FIG. 4 is deleted to reduce the circuit scale.

FIG. 12 is a block diagram showing a second modification of the pulse width forming circuit 10 shown in FIG. This FIG.
As shown in FIG. 5, in the second modification, the 3-input AND 14 of the pulse width forming circuit 10 of FIG. 4 is deleted to reduce the circuit scale.

FIG. 13 is a block diagram showing a modification of the latch timing determination circuit 210 shown in FIG. As shown in FIG. 13, in this latch timing determination circuit, the latch circuit 213 of the latch timing determination circuit 210 shown in FIG. 4 is deleted to reduce the circuit scale. It should be noted that the latch timing determination circuits 220 to 220 shown in FIG.
The 240 can also have the same configuration as in FIG.

Next, the operation of bit phase synchronization will be described based on the circuit configurations shown in FIGS. 11 to 13 described above. Generally, 1 bit width of "1" of external input data and 1 of "0"
The bit widths are the same, and only the input delay data and the first pulse width signal are generated as in the pulse width forming circuit of the first modification shown in FIG. 11, and those are generated by the latch timing determination circuit shown in FIG. Or comparing only the input delay data and the second pulse width signal as in the pulse width forming circuit of the second modified example shown in FIG. 12, and using the latch timing determination circuit shown in FIG. Of the pulse width forming circuit 10 and the latch timing determining circuits 210 to 24 in the second embodiment described above.
A function equivalent to 0 is obtained.

As described above, the pulse width forming circuit 10 is configured as in the first and second modifications shown in FIGS. 11 and 12, and the latch timing determination circuits 210 to 240 are as in the modification of FIG. With this configuration, it is possible to reduce the circuit scale while obtaining the same effect as that of the above-described second embodiment.

[Third Embodiment]: FIG. 14 is a block diagram of a bit phase synchronizing circuit according to a third embodiment of the present invention. In the third embodiment shown in FIG. 14, the present invention is applied when the input data is parallel data, the parallel data is j pieces of parallel data, and the number of internal clock phases is n. The phase absorption width is m bits wide.

This bit phase synchronization circuit comprises a bit phase synchronization master circuit 3 and a plurality of bit phase synchronization slave circuits 71 to 7j-1. Data input terminal 01-
0j to bit phase synchronization slave circuits 71 to 7 respectively
The input data is given to the data input terminal of j−1, the input data is given from the data input terminal 0j to the data input terminal of the bit phase synchronization master circuit 3, and the phase control signal output and the plane of the bit phase synchronization master circuit 3 are provided. The phase control signal outputs are bit phase synchronization slave circuits 71 to 7j-, respectively.
1 to the phase control signal input terminal and the surface phase control signal input terminal, and the bit phase synchronization slave circuits 71 to 7j-
The data outputs of 1 are external data output terminals 81 to 8 respectively.
The data output of the bit phase synchronization master circuit 3 is output to the data output terminal 8j.

The bit phase synchronization master circuit 3 has the above-mentioned first configuration.
1 is a functional configuration shown in FIG. 1 of the embodiment, and the control signal output of the selector control circuit 8 of FIG. 1 is distributed to the bit phase synchronization slave circuits 71 to 7j-1. Each of the bit phase synchronization slave circuits 71 to 7j-1 extracts only the function of the data path of the bit phase synchronization master circuit 3.

Bit phase synchronization slave circuits 71 to 7j-
Taking the bit phase synchronization slave circuit 71 as an example, the pulse width forming circuit of the bit phase synchronization master circuit 3 is replaced with the delay element 7100, the latch timing determination circuit is replaced with the latch circuits 7111 to 71n1, and the phase align circuit 7112 to 71n2 is provided only for one data input, the selector control circuit is omitted, and the other configuration is the same as that of the bit phase synchronization master circuit 3. That is,
The internal configuration is provided with m: 1 selectors 7114 to 71n4 and n: 1 selector 7115. The same applies to the other bit phase synchronization slave circuits 72 to 7j-1.

(Operation): Next, the operation of the bit phase synchronizing circuit according to the third embodiment of FIG. 14 will be described. First,
External parallel data input is external data input terminal 01-0
j. It is assumed that the external parallel data have almost the same phase at the change points. Of these, the data input to the external data input terminal 0j is used as master data,
The phase selection control signal and the plane selection control signal are generated so as to select the data that can be latched at the proper timing by the bit phase synchronization master circuit 3. These signals are input to the bit phase synchronization slave circuits 71 to 7j-1. In the bit phase synchronization slave circuits 71 to 7j-1 and the bit phase synchronization master circuit 3, proper data is selected by the phase selection control signal and the plane selection control signal and output to the data output terminals 81 to 8j.

(Effects of the third embodiment): With the configuration and operation of the third embodiment described above, the phase of m bits in front and rear of the input parallel data whose phase relationship with the internal clock is unknown. It is possible to absorb the fluctuation and stably output the parallel data latched at an appropriate timing and the clock synchronized with the parallel data.

(Other Embodiments) (1) In the data latch timing judgment circuit in which the pulse width forming circuit and the latch timing judgment circuit are combined, the first embodiment example and the second embodiment example In the modification, the third embodiment has been described as an example applied to the bit phase synchronization circuit, but an element capable of varying the phase of data or clock is arranged outside, and the timing of the input data and the input clock is manually adjusted by the element. The data latch timing determination circuit of the present invention can also be applied to a device that adjusts with. In such a case, it was generally necessary to make adjustments while monitoring the input data and input clock with an oscilloscope, etc., but an expensive measuring instrument such as an oscilloscope was required, and further, if the signal was high speed, The timing of the signal changes depending on the load of the monitor probe.

Therefore, if a light emitting diode or the like which is turned on by a timing judgment result signal is attached to the outside by using the data latch timing judgment circuit of the present invention, the timing can be adjusted by turning on or off the light emitting diode. Moreover, since there is no need to attach a monitor probe,
Adjustments can be made at the actual timing.

Further, even in the interface in which the input data and the input clock are input in a fixed phase, the timing verification can be easily performed only by inserting the data latch timing judgment circuit of the present invention into the circuit of the interface section. it can.

(2) Also, from clock φ1 to clock φ
The generation of the multiphase clocks of 1 to φn can be easily realized by a multivibrator circuit, a ring oscillator circuit, or the like.

(3) Furthermore, the above-mentioned first pulse width signal,
The pulse width of the second pulse width signal may be narrow or slightly wide as long as the pulse has a timing at which a stable level can be latched.

(4) Furthermore, the bit phase synchronization circuit as described above is effective when applied to a transmission device, a switching device, a communication device or the like which performs high speed data transmission at, for example, 100 Mbit / s or more. . The input data may be an RZ signal instead of the NRZ signal.

[0105]

As described above, according to the first aspect of the invention, the n-phase clock forming means for forming the n-phase clock for phase determination by shifting the phase of the clock, and the high level of the input data from the input data. A first pulse width signal for input data latch synchronized with the central part of the period, a second pulse width signal for input data latch synchronized with the central part of the low level period of the input data, or a first pulse width signal Data latch pulse forming means for forming either of the two signals of the second pulse width signal, input data using the clocks of respective phases of the n-phase clock, and data latch pulse forming means And a signal latch determination unit that outputs a n-phase coincidence determination signal by determining whether or not the values of these latch output signals are coincident with each other. H. Each latch output data corresponding to each output phase is transferred with a clock of any phase of the n-phase clock, and the transfer means for outputting the transferred n-phase data, and the n-phase Using the coincidence determination signal and the clock of the phase used by the transfer means, one of the n-phase data transferred by the transfer means synchronized with the clock of the phase used by the transfer means By providing the phase synchronization judgment output means for selectively outputting the data, the data latched at the most appropriate timing can be stably bit-phase synchronized when the mutual phase relationship between the input data and the clock is unknown. A bit phase synchronization circuit can be realized.

The second aspect of the present invention is a bit phase synchronizing apparatus comprising a master bit phase synchronizing circuit and a slave bit phase synchronizing circuit for achieving bit phase synchronization with parallel data. The circuit uses the bit phase synchronization circuit according to claim 1 or 2 for bit data of any one of the parallel data, and at the same time, for the slave bit phase synchronization circuit. , An n-phase clock and a selection control signal for selectively controlling data of a phase synchronized with any one of these n-phase clocks, and the slave bit phase synchronization circuit is The bit phase is synchronized with other data other than the first data of the parallel data, and the clock of each phase of the n-phase clock is clocked. Signal latch means for latching and outputting other data except the first data by using, and each latch output data corresponding to each latched phase is added by a clock of any phase of the n-phase clock. Alternatively, the n-phase data transferred by the slave transfer means using the slave transfer means for outputting the transferred n-phase data and the phase clock used in the slave transfer means. Among these, the slave phase synchronization determination output means for selectively outputting the data of any phase synchronized with the clock of the phase used in the slave switching means by the selection control signal from the master bit phase synchronization circuit is provided. Since the configuration is such that bit phase synchronization is achieved, synchronization can be easily established on the receiving side in parallel data transmission, and the device is made compact. It can be achieved Tsu preparative phase synchronization apparatus.

Further, in the third invention, the first pulse width signal for input data latch synchronized with the central portion of the high level period of the input data and the central portion of the low level period of the input data are synchronized with the input data. A second pulse width signal for input data latch, or both signals of the first pulse width signal and the second pulse width signal, a data latch pulse forming means for forming either signal, and a clock are used. Input data and one of the signals formed by the data latch pulse forming means is latched and output, and a match determination signal is output by determining whether or not the values of these latch output signals match, By providing the signal latch determination means for visually displaying this coincidence determination signal as a coincidence determination result, it is possible to accurately determine the appropriateness of the data latch timing with a very simple configuration. It can be realized over data latch timing determination circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a bit phase locked loop circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a bit phase synchronization circuit according to a conventional example.

FIG. 3 is a timing chart of n-phase clocks according to the first embodiment.

FIG. 4 is a functional configuration diagram of a bit phase synchronization circuit according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram of a selector control circuit according to a second embodiment.

FIG. 6 is a waveform diagram of an output signal of the pulse width forming circuit according to the second embodiment.

FIG. 7 is a waveform diagram of clocks according to the second embodiment.

FIG. 8 is a chart showing a truth value of the data selection determining circuit according to the second embodiment.

FIG. 9 is a chart showing the operation of the up / down counter according to the second embodiment.

FIG. 10 is an explanatory diagram of output data of the output timing adjustment circuit according to the second embodiment.

FIG. 11 is a configuration diagram showing a first modification of the pulse width forming circuit shown in FIG.

12 is a configuration diagram showing a second modification of the pulse width forming circuit shown in FIG.

13 is a configuration diagram showing a modified example of the latch timing determination circuit shown in FIG.

FIG. 14 is a configuration diagram of a bit phase synchronization circuit according to a third embodiment of the present invention.

[Explanation of symbols]

0 ... Data input terminal, 1 ... Pulse width forming circuit, 21-2
n ... Latch timing determination circuit, 31-3n ... Phase align circuit, 41-4n ... Shift register circuit, 51
5n ... m: 1 selector, 6 ... n: 1 selector, 7 ... reset signal input terminal, 8 ... selector control circuit, 9 ... data output terminal.

 ──────────────────────────────────────────────────の Continued from the front page (72) Inventor Takashi Oya 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (4)

[Claims] 1. A bit phase synchronization circuit for performing bit phase synchronization between input data and a clock having the same frequency as the bit rate of the input data, wherein the clock is phase-shifted and n (n is 3 or more) for phase determination. An n-phase clock forming means for forming a clock of an (integer number) phase, and a first pulse width signal for latching the input data, which is synchronized with the central portion of a high level period of the input data, from the input data, A second pulse width signal for the input data latch synchronized with the central portion of the low level period,
Alternatively, a data latch pulse forming means for forming one of the first pulse width signal and the second pulse width signal, and a clock for each phase of the n-phase clock are used. The input data and any one of the signals formed by the data latch pulse forming means are latched and output, and it is determined whether or not the values of these latch output signals match with each other to determine the n-phase match. The signal latch determination means for outputting a signal, and the latch output data corresponding to the respective phases output by the latch are transferred by the clock of any phase of the n-phase clock, and the transferred n-phase data Is used, the n-phase coincidence determination signal, and the clock of the phase used by the transfer means are used to transfer the n-phase data transferred by the transfer means. Of data, bit phase synchronizing circuit comprising the phase synchronization determination output means for selectively outputting one of the phases of the data synchronized with the phase of the used clock by the handoff unit. 2. The phase synchronization judgment output means shifts each of the n-phase data output from the transfer means by a shift register to obtain an m (m is an integer of 2 or more) phase for phase fluctuation absorption. 2. The bit phase locked loop circuit according to claim 1, wherein the bit phase locked loop circuit is configured to output a phase shift. 3. A bit phase synchronizing apparatus comprising a master bit phase synchronizing circuit and a slave bit phase synchronizing circuit for achieving bit phase synchronization with parallel data, wherein the master bit phase synchronizing circuit is the parallel circuit. The bit phase synchronization circuit having the configuration according to claim 1 or 2 is used for any one of the first data, and the n-phase is used for the slave bit phase synchronization circuit. The slave bit phase synchronization circuit is configured to output a clock and a selection control signal for selectively controlling data of a phase synchronized with a clock of one of these n phases. Bit phase synchronization with other data other than the first data in the data, wherein each of the n-phase clocks The slave signal latch means for latching and outputting the other data except the first data by using the phase clock, and the latch output data corresponding to the latched phases are the n-phase clocks. Using the clock of this phase and outputting the transferred n-phase data to the slave, and using the clock of the phase used by the slave transferring means, the slave transferring means Among the n-phase data transferred in step S1, the data of any phase synchronized with the clock of the phase used in the slave transfer means is selectively output by the selection control signal from the master bit phase synchronization circuit. A bit phase synchronization device comprising a slave phase synchronization determination output means for achieving bit phase synchronization. 4. A data latch timing determination circuit for determining whether or not the data latch timings of input data and a clock having the same frequency as the bit rate of the input data are matched. The first pulse width signal for the input data latch synchronized with the central portion of the high level period, the second pulse width signal for the input data latch synchronized with the central portion of the low level period of the input data, or the first pulse width signal Data latch pulse forming means for forming either one of the first pulse width signal and the second pulse width signal; the input data using the clock; and the data latch pulse forming means Latch output with any of the above signals formed by means, and determine whether or not the values of these latch output signals match, and determine whether they match. Outputs No., data latch timing determination circuit, characterized in that a signal latch determination means for visually displaying the coincidence judgment signal as the matching determination result.