JPH0981622A - Method for generating flattened pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of a minute flattened pattern not satisfying the design rule of the layout design of a wiring pattern by applying a reduction processing to an obtained flattened pattern. SOLUTION: The inversion processing of a plane pattern (a) near wiring is performed, the reduction processing for reducing an obtained graphic pattern (d) to the inside is performed and the graphic pattern (e) is outputted. The OR arithmetic processing of the graphic pattern (e) and the graphic pattern (c) is performed and the flattened pattern (f) including minute patterns is obtained. Then, in order to eliminate square patterns smaller than the size of original square patterns in the graphic pattern (c) in the graphic pattern (f), the reduction processing is applied and the graphic pattern (g) is outputted. A magnification processing for the absolute value of the reduction width of the reduction processing used at the time is performed, the graphic pattern (h) is outputted and the flattened pattern to be used for the wiring pattern (a) is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for easily generating a flattening pattern for flattening a wiring layer in a multilayer wiring layer in an LSI chip.

[0002]

2. Description of the Related Art In recent years, a technique for forming wiring layers in multiple layers has been used for higher integration of VLSI.

However, when the wiring layers are multi-layered, the unevenness of the underlying wiring pattern affects the interlayer insulating film formed on the wiring pattern layer, and the unevenness appears in the interlayer insulating film. These irregularities cause step coverage defects when forming the upper layer wiring film, resulting in disconnection and defects of the wiring. Therefore, flattening the surface of the interlayer insulating film has become a necessary technique for realizing highly reliable multilayer wiring.

Conventionally, a resin coating method or the like has been used as a flattening technique, but there is a problem that sufficient flattening cannot be obtained. In order to improve this, a CAD technique is provided in a gap between wirings. A method has been invented for performing planarization by filling in a planarization pattern using. As a method of generating a flattening pattern using this CAD technique, for example, there is one described in Japanese Patent Application Laid-Open No. 5-267460.

An example of such a conventional method of generating a flattening pattern for a wiring layer will be described below with reference to the drawings.

FIG. 9 is a diagram showing an example in which a flattening pattern is generated in the vicinity of a wiring by a conventional flattening pattern generating method for a wiring layer.

FIG. 9A shows an original figure pattern, 10 is a wiring pattern, and 11 is a plane pattern (plain) near the wiring. FIG. 9B shows a wiring pattern and a flattening pattern generated by a conventional method of generating a flattening pattern for a wiring layer, and FIG. 9C shows a figure pattern (hereinafter, dummy pattern) in which a square pattern is arranged in a satin pattern. Pattern).

In FIG. 9A, the plane pattern in the vicinity of the wiring is inverted and the figure pattern of FIG. 9D is output.
Next, reduction processing for shrinking the figure pattern in FIG. 9D inward is performed and the figure pattern shown in FIG. 9E is output. Compared to FIG. 9D, this reduced distance is set to be about the minimum distance between wirings on the chip plane. Next, FIG.
The logical product operation of the figure pattern of (e) and the figure pattern of FIG. 9 (c) is performed, and FIG. 9 (f) is output. 9F is a flattening pattern for the wiring pattern, and the flattening pattern of FIG. 9F and the wiring pattern of FIG. 9A are ORed to perform the OR operation. Output the figure pattern.

[0009]

However, in the above-described flattening pattern generating method for the wiring layer, the position of the wiring pattern and the position of the dummy pattern which is the source of the flattening pattern in the flattening pattern generated in the vicinity of the wiring. Depending on the relationship, the shape of the square of the original dummy pattern is not maintained, that is, the shape of the original square pattern is deformed. In this case, there is a problem that a minute figure that does not satisfy the design rule of the layout design of the wiring pattern is generated for the flattening pattern.

The present invention solves the above-mentioned conventional problems, and when generating a flattening pattern for a wiring layer, a fine flattening pattern that does not satisfy the design rule of the layout design of the wiring pattern does not occur. A method for generating a flattening pattern for a wiring layer is provided.

[0011]

In order to solve the above problems, a method of generating a flattening pattern for a wiring layer according to the present invention includes a process of graphically reversing a plane pattern around a wiring pattern and the reversing process. A process of reducing the figure pattern inside the figure, a process of performing a logical product operation of the figure pattern in which simple figures are repeatedly arranged and the figure pattern subjected to the reduction process, and a figure pattern subjected to the logical product operation process is reduced to the inside of the figure. And a process of expanding the enlarged graphic pattern to the outside of the graphic.

[0012]

According to the present invention, with the above-described configuration, the flattening pattern obtained when the flattening pattern is generated for the wiring layer is subjected to the reduction processing, whereby the design rule of the layout design of the wiring pattern is established. Layout of the wiring pattern by erasing the minute figure pattern that does not satisfy the size and expanding only the figure pattern that satisfies the design rule of the wiring pattern layout design to the size of the figure pattern before performing the reduction process again. The flattening pattern is generated for the wiring layer that satisfies the design rule of the design.

[0013]

【Example】

Embodiment 1 Hereinafter, a first embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

FIG. 1 is a diagram for explaining a method of generating a flattening pattern for a wiring in this embodiment.

FIG. 1A shows an original figure pattern, which is 10
Shows a wiring pattern, and 11 shows a plane pattern (plain) near the wiring. FIG. 1B shows a flattening pattern and a wiring pattern generated according to this embodiment, and 12 is a flattening pattern generated according to this embodiment. FIG.
A in (b) indicates an interval between the wiring pattern and the flattening pattern, and this value is equal to or larger than the minimum value that satisfies the rule of the wiring pattern in the semiconductor manufacturing process. FIG.
(C) is a figure pattern (hereinafter referred to as a dummy pattern) in which square patterns used to generate a flattening pattern are repeatedly arranged in a satin pattern, and B in FIG.
Indicates the size of the square pattern in the dummy pattern,
This value is equal to or larger than the minimum value that satisfies the rule of the wiring pattern in the semiconductor manufacturing process. 1 (d)-
(H) shows a graphic pattern showing the process and result of generation of the planarization pattern for the wiring according to the present embodiment.

FIG. 2 is a logical operation formula showing a procedure for generating a planarization pattern for a wiring by using the method for generating a planarization pattern for a wiring in the embodiment of the present invention.

For the numbers in the equation used in FIG. 2, "1"
Represents the original figure pattern of FIG. 1A, and “10” represents the pattern of FIG.
(C) represents a dummy pattern, and “20” to “25” represent graphic patterns output as a result of logical operation processing of graphics. In addition, regarding the operator in the expression used in FIG.
= C ”represents a process of inverting the graphic pattern indicated by a and outputting the result to c, and“ a + b = c ”outputs the logical sum operation processing result of the graphic pattern indicated by a and the graphic pattern indicated by b to c "A * b = c" represents a process of outputting the logical product operation processing result of the graphic pattern indicated by a and the graphic pattern indicated by b to c, and "a (+ b) = c" is a
The figure pattern indicated by is enlarged outside the figure by the value of b and c
"A (-b) = c" represents a reduction process of reducing the figure pattern indicated by a to the inside of the figure by the value of b and outputting the result to c. Further, in the alphabetical symbols used in FIG. 2, “A” has the same value as A in FIG. 1B, and represents the distance between the wiring pattern and the flattening pattern. This value is used in the semiconductor manufacturing process. The size is equal to or larger than the minimum value that satisfies the wiring pattern rule. “D” is a value equal to or less than ½ of the value of B in FIG.
A value that can delete only a pattern having a size smaller than the square pattern in (c) is used.

The operation of this embodiment configured as described above will be described. In FIG. 1A, the plane pattern near the wiring is inverted, and the figure pattern of FIG. 1D is output.

Next, reduction processing for shrinking the figure pattern of FIG. 1D inward is performed, and the figure pattern shown in FIG. 1E is output. Compared to FIG. 1D, this reduced distance is set to be about the minimum distance between wirings on the chip plane.

Next, the figure pattern of FIG. 1E and FIG.
The logical product arithmetic processing of the figure pattern of (c) is performed, and FIG.
Output (f).

The processing up to step 3 is the same as the conventional method, and as shown in FIG. 1F, a flattening pattern including a fine pattern is obtained.

Next, of the figure patterns in FIG. 1 (f),
In order to delete a square pattern that is smaller than the size of the original square pattern in FIG. 1C, the reduction process is performed by the value of D in FIG. 2 and the graphic pattern in FIG. 1G is output.

In order to restore the figure pattern of FIG. 1 (g) to the original size of the square pattern of FIG. 1 (c), the pattern of FIG.
1G is output by performing expansion processing by the absolute value of the reduction width (value of D in FIG. 2) of the reduction processing used when the graphic pattern of (g) is output. Among the square patterns in the dummy pattern of (c), the flattening pattern used for the wiring pattern of FIG. 1 (a) can be obtained.

Finally, the figure pattern of FIG. 1 (h) and FIG.
The logical sum operation processing with the wiring pattern of (a) is performed to obtain a graphic pattern in which the flattening pattern and the wiring pattern of FIG. 1 (b) are combined.

As described above, according to the present embodiment, when a flattening pattern is generated for a wiring layer, a pattern for deleting a minute graphic pattern of a size that does not satisfy the design rule of the layout design of the wiring pattern is created. The design rule of the wiring pattern layout design is performed by reducing the pattern and expanding the figure pattern that satisfies the design rule of the layout design of the wiring pattern to the size of the figure pattern before the reduction process again. It is possible to generate a flattening pattern for the wiring layer that satisfies the above condition.

There are various methods for obtaining a flattening pattern including a fine pattern. For example, even if the procedure of this embodiment is replaced with a step of enlarging the wiring pattern to the outside of the figure and a step of deleting the overlapping portion of the enlarged figure pattern from the figure pattern in which simple figures are repeatedly arranged, The same effect as can be obtained.

(Embodiment 2) Next, a method of generating a planarization pattern for wiring in the second embodiment of the present invention will be described.

FIG. 3A shows an original figure pattern, which is 10
Shows a wiring pattern, and 11 shows a plane pattern (plain) near the wiring. FIG. 3B shows a flattening pattern and a wiring pattern generated according to the embodiment of the present invention.
Is a planarization pattern generated according to an embodiment of the present invention. A in FIG. 3B indicates the distance between the wiring pattern and the flattening pattern, and this value is equal to or larger than the minimum value that satisfies the rule of the wiring pattern in the semiconductor manufacturing process.

FIGS. 3C to 3F are graphic patterns in which square patterns used to generate a planarized pattern are repeatedly arranged in a satin pattern (hereinafter referred to as dummy patterns). A fourth dummy pattern is shown. In FIGS. 3 (c) to 3 (f), the layout position coordinates of the graphic are shifted by different values with respect to the coordinate origin.

B in FIG. 3C shows the size of the square pattern in the dummy pattern, and this value is equal to or larger than the minimum value that satisfies the rule of the wiring pattern in the semiconductor manufacturing process. Further, C in FIG. 3C shows a space between the square patterns in the dummy pattern, and this value is also a value equal to or larger than the minimum value that satisfies the rule of the wiring pattern in the semiconductor manufacturing process. is there.

FIGS. 4 to 6 are graphic patterns showing a process and result of generating a flattening pattern for a wiring according to an embodiment of the present invention.

FIG. 7 is a logical operation formula showing a procedure for generating a flattening pattern for a wiring by using the method for generating a flattening pattern for a wiring in the embodiment of the present invention.

Regarding the numbers in the formula used in FIG. 7, "1"
Represents the original figure pattern of FIG. 3 (a), and “10” represents FIG.
FIG. 3C shows the first dummy pattern in (c), and “11” is shown in FIG.
(D) represents the second dummy pattern, and "12" is shown in FIG.
(E) represents the third dummy pattern, and "13" is shown in FIG.
(F) represents a fourth dummy pattern, and is represented by "40" to "6".
2 "represents a graphic pattern output as a result of logical operation processing of the graphic.

Regarding the alphabetic symbols used in FIG. 7, “C” is the same value as C in FIG. 3B, which is the value of the interval between the flattening patterns, and this value is used in the semiconductor manufacturing process. The size is equal to or larger than the minimum value that satisfies the wiring pattern rule. Other symbols are the same as those in FIG.

The operation of this embodiment configured as described above will be described. First, of the first dummy patterns of FIG. 3C, the flattening pattern used for the wiring pattern of FIG. 3A is generated by the following method.

The value of the minimum distance that must be satisfied between the wiring pattern and the flattening pattern to finally obtain the graphic pattern shown in FIG. 3A (FIG. 3B and FIG. 7).
The enlargement processing is performed only for "A" in the inside, and the figure pattern of FIG. 4A is output. The figure included in FIG. 4A represents a wiring pattern and a region in which it is prohibited to generate a flattening pattern around the wiring pattern according to the rule of the wiring pattern in the semiconductor manufacturing process.

Next, a process (FIG. 4 (b)) for deleting the graphic pattern overlapping with the graphic pattern of FIG. 4 (a) from the dummy pattern of FIG. 3 (c) is performed to obtain the graphic pattern of FIG. 4 (c). 3 of the figure patterns shown in FIG.
In order to delete the square pattern which is smaller than the size of the original square pattern in (c), the reduction process is performed by the value of D in FIG. 7 and the figure pattern of FIG. 4 (d) is output.

In order to restore the figure pattern of FIG. 4 (d) to the original size of the square pattern of FIG. 3 (c), FIG.
3D is performed by performing expansion processing by the absolute value of the reduction width (value of D in FIG. 7) of the reduction processing used when outputting the figure pattern of FIG. 4D, and outputting the figure pattern of FIG. Among the square patterns in the dummy pattern of (c), the flattening pattern used for the wiring pattern of FIG. 3 (a) can be obtained.

Next, of the dummy patterns shown in FIG. 3D, a flattening pattern used for the wiring pattern shown in FIG. 3A is generated by the following method.

First, the flattening pattern of FIG.
Enlargement processing is performed by the value of C, and FIG. 4 (f) is output. The figure included in FIG. 4 (f) has the flattening pattern of FIG. 4 (f) and FIG. 3 (f) according to the rule of the spacing between the figure patterns in the semiconductor manufacturing process around the flattening pattern. The region from which the generation of the flattening pattern is prohibited from (d) is shown.

Next, the figure pattern of FIG. 4A and FIG.
The logical sum operation processing of the figure pattern of FIG.
Output (g). The figure included in FIG. 4 (g) is
Of the dummy patterns shown in FIG. 3D, the area where generation of the flattening pattern is prohibited is shown.

Next, a process (FIG. 4 (h)) for deleting the graphic pattern overlapping with the graphic pattern of FIG. 4 (g) from the dummy pattern of FIG. 3 (d) is performed to obtain the graphic pattern of FIG. 5 (a). Output.

Of the figure patterns in FIG. 5A, FIG.
In order to delete the square pattern which is smaller than the size of the original square pattern in (d), the reduction process is performed by the value of D in FIG. 7 and the figure pattern of FIG. 5 (b) is output.

In order to restore the figure pattern of FIG. 5 (b) to the original size of the square pattern of FIG. 3 (d), FIG.
FIG. 3C is output by performing enlargement processing by the absolute value of the reduction width (value of D in FIG. 7) of the reduction processing used when outputting the graphic pattern of FIG. Among the square patterns in the dummy pattern of (d), the flattening pattern used for the wiring pattern of FIG. 3 (a) can be obtained.

Next, of the dummy patterns shown in FIG. 3E, a flattening pattern used for the wiring pattern shown in FIG. 3A is generated by the following method.

First, the flattening pattern of FIG.
The value of C in FIG. The figure included in FIG. 5D is the flattening pattern of FIG. 5C, and FIG. 3C according to the rule of the spacing between the figure patterns in the semiconductor manufacturing process around the flattening pattern of FIG. 5C. The region (e) from which the generation of the flattening pattern is prohibited is shown.

Next, the figure pattern of FIG. 4 (g) and FIG.
As shown in FIG.
Output (e). The figure included in FIG. 5 (e) is
Of the dummy patterns shown in FIG. 3 (e), the area where generation of the flattening pattern is prohibited is shown.

Next, a process (FIG. 5 (f)) for deleting the graphic pattern overlapping the graphic pattern of FIG. 5 (e) from the dummy pattern of FIG. 3 (e) is performed, and the graphic pattern of FIG. 5 (g) is obtained. Output.

Of the figure patterns in FIG. 5 (g), FIG.
In order to delete the square pattern which is smaller than the size of the original square pattern in (e), the reduction process is performed by the value of D in FIG. 7 and the figure pattern of FIG. 5 (h) is output.

In order to restore the figure pattern of FIG. 5 (h) to the original size of the square pattern of FIG. 3 (e), FIG.
FIG. 3A is output by performing enlargement processing by the absolute value of the reduction width (value of D in FIG. 7) of the reduction processing used when outputting the figure pattern of FIG. Among the square patterns in the dummy pattern of (e), the flattening pattern used for the wiring pattern of FIG. 3 (a) can be obtained.

Next, among the dummy patterns shown in FIG. 3 (f),
The flattening pattern used for the wiring pattern of FIG. 3A is generated by the following method.

First, the flattening pattern of FIG.
The value of C is enlarged and the output of FIG. The figure included in FIG. 6B has the flattening pattern of FIG. 6A and the figure 3A according to the rule of the spacing between the figure patterns in the semiconductor manufacturing process around the flattening pattern of FIG. 6A. The area from (f) in which generation of the flattening pattern is prohibited is shown.

Next, the figure pattern of FIG. 5E and FIG.
FIG. 6 shows the logical sum operation processing of the figure pattern of FIG.
(C) is output. The figure included in FIG. 6C is
Of the dummy patterns shown in FIG. 3 (f), the area where generation of the flattening pattern is prohibited is shown.

Next, a process (FIG. 6 (d)) for deleting the figure pattern overlapping the figure pattern of FIG. 6 (c) from the dummy pattern of FIG. 3 (f) is performed to obtain the figure pattern of FIG. 6 (e). Output.

Of the figure patterns in FIG. 6 (e), FIG.
In order to delete the square pattern that is smaller than the size of the original square pattern in (f), the reduction process is performed by the value of D in FIG. 7, and the figure pattern in FIG. 6 (f) is output.

In order to restore the figure pattern of FIG. 6 (f) to the original size of the square pattern of FIG. 3 (f), FIG.
FIG. 3G is output by performing expansion processing for the absolute value of the reduction width (value of D in FIG. 7) of the reduction processing used when outputting the figure pattern of FIG. Among the square patterns in the dummy pattern of (f), the flattening pattern used for the wiring pattern of FIG. 3 (a) can be obtained.

As described above, the flattening pattern of FIG. 4E is generated from the dummy pattern of FIG.
The flattening pattern of FIG. 5C is generated from the dummy pattern of FIG. 5D, and the flattening pattern of FIG.
6A is generated, and the flattening pattern of FIG. 6G is generated from the dummy pattern of FIG. 3F.
The logical sum operation processing of each flattening pattern is performed, and
The flattening pattern of (h) is output. Finally, Fig. 6 (h)
The flat pattern and the wiring pattern of FIG. 3A are ORed to obtain the graphic pattern of the wiring pattern and the flattening pattern of FIG. 3B.

As described above, according to the second embodiment of the present invention, a plurality of dummy patterns are used to generate the flattening pattern when the flattening pattern is generated for the wiring pattern. As compared with the flattening pattern of the first embodiment, the distance between the wiring pattern and the flattening pattern and the distance between the flattening patterns can be reduced,
The flatness of the wiring layer can be further improved.

Although the wiring pattern is used as it is in this embodiment, it is also possible to use the wiring pattern by inverting it graphically. The procedure of the processing in that case will be described with reference to FIG.

First, an inverted figure of the wiring pattern is output (FIG. 8A), the inverted figure pattern is reduced to the inside of the figure (FIG. 8B), and the reduced figure pattern and FIG.
The dummy pattern of (c) is ANDed (see FIG. 8).
(C)), reduction processing (FIG. 8 (d)) and enlargement processing (FIG. 8 (e) similar to those in the above-described embodiment in order to delete a fine pattern from the figure obtained as a result of the logical product operation. )) Is performed to obtain a flattening pattern for the dummy pattern in FIG.

Next, the graphic pattern of FIG. 8 (e) is enlarged as in the above embodiment (FIG. 8 (f)), and FIG. 8 (b).
8 (f) is deleted from the figure pattern of FIG. 8 (f) (FIG. 8 (g)), and the figure pattern of FIG. 8 (g) and the figure pattern of FIG. 3 (d) are ANDed. (FIG. 8 (h)) The flattening pattern for the graphic pattern of FIG. 3 (d) is obtained by reducing and enlarging the obtained graphic pattern.

Hereinafter, with respect to the figure patterns of FIGS. 3 (e) and 3 (f), the flattening pattern is obtained in the same manner, and finally the logical sum of all the flattening patterns is taken to obtain the wiring pattern of FIG. 3 (a). Can be obtained.

The simple pattern is as shown in FIG.
In addition to the pear-shaped pattern shown in (c) and FIGS. 3 (c) to (f), it is possible to use a stripe-shaped pattern, a lattice-shaped pattern, or the like. Further, as a simple pattern, various modifications such as a rectangle, a triangle, and a star are possible other than the square pattern.

Further, the present invention is not limited to the above-described embodiment, and various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0065]

As described above, according to the present invention, when a flattening pattern is generated for a wiring layer, a minute graphic pattern of a size that does not satisfy the design rule of the layout design of the wiring pattern is reduced. Wiring that satisfies the design rule of the layout design of the wiring pattern by deleting and expanding the graphic pattern that satisfies the design rule of the layout design of the wiring pattern to the size of the graphic pattern before the reduction processing again A planarization pattern for the layer can be generated.

Further, since the distance between the wiring pattern and the flattening pattern and the distance between the flattening patterns can be reduced, the flatness of the wiring layer can be further improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a method of generating a flattening pattern for a wiring layer according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a logical operation formula showing a procedure for generating a planarization pattern for wiring in the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a method of generating a flattening pattern for a wiring layer according to a second embodiment of the present invention.

FIG. 4 is an explanatory diagram of a method of generating a flattening pattern for a wiring layer according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of a method of generating a flattening pattern for a wiring layer according to a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a method of generating a flattening pattern for a wiring layer according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a logical operation formula showing a procedure for generating a planarization pattern for wiring in the second embodiment of the present invention.

FIG. 8 is a diagram for explaining another method of generating a flattening pattern according to the second embodiment of the present invention.

FIG. 9 is an explanatory diagram of a conventional method of generating a flattening pattern for a wiring layer.

[Explanation of symbols]

 10 Wiring pattern 11 Plane pattern 12 Planarization pattern

Claims (6)

[Claims] 1. A method of generating a flattening pattern for flattening a wiring layer, comprising a process of removing a flattening pattern that does not satisfy a design rule of a layout design of a wiring pattern. Pattern generation method. 2. A method of generating a flattening pattern for flattening a wiring layer, the method comprising: a first process of graphically inverting a plane pattern around a wiring pattern; and a first process. A second operation of reducing the obtained graphic pattern to the inside of the graphic by a first value; and a logical AND operation of the graphic pattern obtained in the second processing and the graphic pattern in which simple graphics are repeatedly arranged. The third process, the fourth process of reducing the graphic pattern obtained by the third process to the inside of the graphic by the second value, and deleting the graphic having a predetermined size or less. And a fifth process of enlarging the figure pattern obtained by the above process to the outside of the figure by the second value. 3. A method of generating a flattening pattern for flattening a wiring layer, comprising: expanding a wiring pattern by a first value to the outside of a figure.
Of the graphic pattern obtained by repeatedly arranging the simple graphic, the second process of deleting the overlapping portion with the graphic pattern obtained by the first process, and the graphic pattern obtained by the second process. , A third process of reducing the inside of the graphic by a second value and deleting a graphic of a predetermined size or less, and the graphic pattern obtained by the third processing, And a fourth process of expanding to the outside of the flattening pattern. 4. A method of generating a flattening pattern for flattening a wiring layer, comprising: a wiring pattern of a wiring layer plan; and a plurality of graphic patterns in which simple graphics are repeatedly arranged. A method for generating a flattening pattern, characterized by performing processing. 5. A graphic logic operation process for expanding a wiring pattern by a first value to the outside of the graphic.
And the first figure pattern in which simple figures are repeatedly arranged,
A second process of deleting an overlapping portion with the graphic pattern obtained by the first process; and a graphic pattern obtained by the second process being reduced by a second value inside the graphic, A third process for deleting a graphic having a predetermined size or less; a fourth process for expanding the graphic pattern obtained by the third process to the outside of the graphic by the second value; A fifth pattern for enlarging the figure pattern obtained by the above process to the outside of the figure by a third value; a figure pattern obtained by the first process; and a figure pattern obtained by the fifth process. A sixth process for performing a logical sum operation of the above; a seventh process for deleting an overlapping portion with the graphic pattern obtained in the sixth process from the second graphic pattern in which simple graphics are repeatedly arranged; Shrink the figure pattern obtained by the process to the inside of the figure by the second value. Then, an eighth process for deleting a graphic having a size equal to or smaller than a predetermined size, and a ninth process for expanding the graphic pattern obtained by the eighth process to the outside of the graphic by the second value, The flattening pattern according to claim 4, further comprising: a tenth process of performing a logical sum operation of the graphic pattern obtained by the fourth process and the graphic pattern obtained by the ninth process. Generation method. 6. A graphic logic operation process comprises a first process for graphically inverting a plane pattern around a wiring pattern, and a graphic pattern obtained by the first process, A second process of reducing inward, a third process of performing a logical product operation of the graphic pattern obtained in the second process and a first graphic pattern in which simple graphics are repeatedly arranged, and the third process The graphic pattern obtained by the above is reduced by a second value to the inside of the graphic, and a fourth process for deleting a graphic having a predetermined size or less; and the graphic pattern obtained by the fourth process, A fifth process for expanding the figure pattern by the second value to the outside of the figure; a sixth process for expanding the figure pattern obtained by the fifth process to the outside of the figure by the third value; The graphic pattern obtained by the sixth process from the graphic pattern obtained by the two processes. Part 7 of deleting the overlapping part with
Process, an eighth process of performing a logical product operation of the graphic pattern obtained in the seventh process and a second simple graphic in which simple graphics are repeatedly arranged, and the graphic obtained in the eighth process. A ninth process of reducing the pattern to the inside of the graphic by the second value and deleting a graphic having a predetermined size or less; and the graphic pattern obtained by the ninth process, A tenth process of enlarging only the value to the outside of the graphic, and an eleventh process of performing a logical sum operation of the graphic data obtained in the fifth process and the graphic data obtained in the tenth process. The method for generating a flattening pattern according to claim 4, further comprising: