JPH0974348A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with which a leakage current does not flow among power sources even when a low voltage power source (VDDL) is turned off at a multi-power source IC provided with a boost level shifter. SOLUTION: Inside a booster circuit 102, a control circuit composed of a Pch transistor 110 and an Nch transistor 111 is provided and the booster circuit is controlled by a control (CNT) signal. Then, since a VSS potential is supplied to a CNT terminal even when the VDDL power source is turned off, the Nch transistor 111 is turned off so that no current can flow between a VDDH power source and a VSS power source even when the potential at an IN terminal and a point B turns into an intermediate potential between the VDDL potential and the VSS potential. Since the booster circuit can be stopped when the low voltage power source is turned off by the control signal, the low voltage power source can be turned off and the semiconductor device with low current consumption can be prepared.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-power supply IC having a boost level shifter.

[0002]

2. Description of the Related Art A conventional boosting level shifter includes, for example, as shown in FIG. 4, an inverter 401 which uses a low voltage power source (hereinafter abbreviated as VDDL) and a high voltage power source (hereinafter VDDH).
Abbreviated) as the power source, and VDDH
It is comprised by the inverter 403 which uses as a power supply. Here, other internal circuits operating in the VDDL system for supplying the input signal to the inverter 401 are not shown. Normal booster circuit 40
2 is a Pch transistor 404 and an Nch transistor 4
06-based inverter, Pch transistor 407 and N
Each output of the inverter by the ch transistor 409 is connected to the gates of the Pch transistors 405 and 408.

[0003]

In order to reduce the power consumption in a multi-power supply IC, it is desirable to turn off the power supply when the circuits of each power supply system are not operated, but in the case of the conventional step-up level shifter, the step-up circuit is Since it has an inverter configuration, when VDDH is turned off, VDDL to VSS
No current flows between them. However, when VDDL is turned off, not only the output of the inverter 401 becomes open, but also the IN terminal which is the output of the front stage of the inverter 401 becomes open (unless a signal is directly applied to the IN terminal from the outside). Unavoidable). Therefore, the booster circuit 4
02, the gate potentials of the Pch inverters 404 and 407 and the Nch inverters 406 and 409 forming the 02 are indefinite, and a leak current flows between VDDH and VSS. Therefore, there is a problem that VDDL cannot be turned off.

Therefore, the present invention solves the problems of the conventional boost level shifter.
It is an object to supply a semiconductor device in which a leak current does not flow between power supplies regardless of which of DDL and VDDH is turned off.

[0005]

A first inverter connected between a first power supply terminal having a first potential and a second power supply terminal having a ground potential; an input signal of the first inverter; A booster circuit connected between the third power supply terminal having a second potential and operating on the basis of the output signal and the second power supply terminal, and an output signal of the booster circuit being input to the second potential A switch for controlling the operation of the booster circuit between the booster circuit and the second or third power supply terminal, the switch being an NchFET, and the FET Is provided with the ground potential or the second potential, and a pull-up transistor for pulling up the input terminal of the second inverter is provided. Is commonly connected to the gate electrode of the FET, the switch is a PchFET, and the ground potential or the second potential is applied to the gate terminal of the FET, the second inverter A pull-down transistor that pulls down the input terminal of the FET, the gate electrode of the pull-down transistor is commonly connected to the gate electrode of the FET, and a voltage detection circuit for comparing a reference potential with the potential of the first power supply terminal. The gate potential of the FET is controlled by the output of the voltage detection circuit.

[0006]

1 shows a circuit diagram of a boost level shifter as a first embodiment of the present invention. In FIG. 1, an inverter 101 having VDDL as a power source, a booster circuit 102 having VDDH as a power source, and an inverter 103 having VDDH as a power source constitute a boosting level shifter. Here, the booster circuit 102 includes a Pch transistor 107 having a VDDH power source as a source, an IN terminal for transmitting a signal from a circuit of a VDDL power source connected to the gates of an Nch transistor 109, and a Pch transistor 104 having a VDDH power source as a source. At the gate of Nch transistor 106,
The output of the inverter 101, which is the inverted signal of the IN terminal, is connected. In addition, Pch transistor 104 and Nc
The Pch transistor 105 is placed between the drains of the h transistors 106, and the Pch transistor 1 is placed between the drains of the Pch transistor 107 and the Nch transistor 109.
08 is provided, the gate of the Pch transistor 105 is connected to the point A which is the output of the inverter composed of the Pch transistors 107 and 108, and the Nch transistor 109, and the gate of the Pch transistor 108 is P
It is connected to the point B which is the output of the inverter constituted by the ch transistors 104 and 105 and the Nch transistor 106, and constitutes a boosting function unit that boosts the VDDL potential to the VDDH potential. Further, a Pch transistor 110 is used as a pull-up transistor between the VDDH power source and point A.
Is provided, and the Nch transistor 11 is used as a switch for controlling the operation of the booster circuit 102 between the VSS power source and the point C.
1 is provided. Pch transistor 110 and Nc
The h-transistor 111 has a gate connected to a CNT terminal to which a signal from the VDDH power supply circuit is propagated, and constitutes a control function unit.

As a result, VDD is applied to the control (CNT) terminal.
When the H potential is supplied, the Pch transistor 110
Turns off and the Nch transistor 111 turns on.
The VDDL potential and the VSS potential propagated to the N terminal are boosted by the booster circuit 102, propagated to the OUT terminal as the VDDH potential and the VSS potential, and function as a boost level shifter. Further, when the VSS potential is supplied to the CNT terminal, the Pch transistor 110 is turned on, and Nc
Since the h transistor 111 is turned off, VDD is applied to the IN terminal.
Even if L potential and VSS potential are supplied, OUT terminal is V
The SS potential will be output. Therefore, logically, the booster circuit 102 receives the IN terminal and the CNT terminal as input, and
It has a 2-input NAND configuration that outputs points, and the boost level shifter receives IN terminal and CNT terminal as input
It has a 2-input NAND configuration in which the T terminal is an output.
As a result, even when the VDDL power supply is turned off, C
By supplying the VSS potential to the NT terminal, the Nch transistor 111 is turned off. Therefore, even if the potential at the IN terminal and the point B becomes an intermediate potential between the VDDL potential and the VSS potential, a current flows between the VDDH power supply and the VSS power supply. Does not flow.

As a second embodiment of the present invention, FIG. 2 shows a circuit diagram of a boost level shifter.

In FIG. 2, an inverter 201 powered by VDDL and a booster circuit 202 powered by VDDH,
It constitutes an inverter 203 and a control function unit of the voltage detection circuit 212. Pch transistor 210 and Nch
The output of the voltage detection circuit 212 is connected to the gate of the transistor 211, and the booster circuit 202 is controlled by the output signal of the voltage detection circuit 212. Further, in the voltage detection circuit 212, the VDDL power supply is connected to the plus terminal and the Vref terminal is connected to the minus terminal.

Therefore, by supplying the Vref terminal with a potential slightly lower than the fluctuation range of the VDDL power supply as the reference potential, when the VDDL power supply is on, the potential of the VDDL power supply is higher than the potential of the Vref terminal. Two
Reference numeral 12 outputs the VDDH potential, and when the VDDL power supply is turned off, the potential of the VDDL power supply becomes lower than the potential of the Vref terminal, so that the comparison circuit 212 outputs the VSS potential.

As a result, when the VDDL power supply is on, the booster circuit 202 is in the operating state, and when the VDDL power supply is off, the booster circuit 202 is in the stop state.
It is not necessary to input a control signal for recognizing that the VDDL power supply is turned off from the VDDH power supply system circuit when the VDDL power supply is turned off, and it is possible to prevent a current from flowing from the VDDH power supply to the VSS power supply. .

A NAND-type booster circuit is used in FIGS. 1 and 2. This is a Pch transistor provided as a switch between VDDH and the booster circuit.
The same applies to a NOR-structured booster circuit including an Nch transistor provided as a pull-down transistor.

Considering the drop in the transistor capability of the booster circuit due to the insertion of the switch transistor, a Pch transistor is preferable for the switch.

FIG. 3 is a block diagram showing an example of signal propagation in FIG. In FIG. 3, the inside of the chip is VDDL.
It is composed of a VDDL system logic 302 that operates by a power supply, a boost level shifter 303, and a VDDH system logic 304 that operates by a VDDH power supply, and an I / O cell that performs a signal interface with the outside of the chip and a power supply are arranged around the chip. VDDL system I / O 301 that performs signal interface of VDDL potential and VSS potential, and VDD
VDDH system I / O 305 that performs signal interface of H potential and VSS potential, VDDL power supply, VDD
It is composed of H power supply and VSS power supply.

Here, VDDL system I / O 301 and VDD
VDD to L system logic 302 and boost level shifter 303
LH power is supplied, VDDH system I / O 305 and VDDH
VDDH for system logic 304 and boost level shifter 303
Power is supplied and VSS power is supplied to all circuits.

The signal is propagated between the VDDL system I / O 301 and the VDDL system logic 302 and the VDDH system I / O 301.
There is a bidirectional interface between the / O 305 and the VDDH system logic 304, and the interface between the VDDL system logic 302 and the VDDH system logic 304 is performed from the logic 302 to the logic 304 via the boost level shifter 303. , Logic 3
The interface from 04 to logic 302 is done directly.

When VDDL power is turned off, VD
The boost level shifter 303 is controlled by the control signal (point A) from the DH logic 304 or the VDDH I / O 305.
Is controlled to prevent a leak current between the VDDH power supply and VSS.

[0018]

As described above, according to the present invention, the boost level shifter can be controlled by the switch for controlling the operation of the boost circuit. Therefore, even if the VDDL power supply is turned off, extra current consumption does not flow. There is an effect that the current consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a boost level shifter according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a boost level shifter according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing an example of signal propagation in FIG.

FIG. 4 is a circuit diagram of a boost level shifter circuit showing a conventional example.

[Explanation of symbols]

101, 103, 201, 203, 401, 403 ...
..Inverters 102, 202, 402 ... Step-up circuits 104, 105, 107, 108, 110, 204, 2
05, 207, 208, 210, 404, 405, 40
7, 408 ... Pch transistors 106, 109, 111, 206, 209, 211, 4
06, 409 ... Nch transistor 212 ... Voltage detection circuit 301, 305 ... I / O cell block 302, 304 ... Logic block 303 ... Boost level shifter block

Claims (6)

[Claims] 1. A first inverter connected between a first power supply terminal having a first potential and a second power supply terminal having a ground potential, and an input signal and an output signal of the first inverter. A third power supply terminal of a second potential which operates based on the
A booster circuit connected between the booster circuit and the second power source terminal, and a second inverter that receives the output signal of the booster circuit and operates at the second potential. 3. A semiconductor device having a switch for controlling the operation of the booster circuit between the power supply terminal 3 and the power supply terminal 3. 2. The switch is composed of an NchFET, and a gate terminal of the FET has the ground potential or the second
2. The semiconductor device according to claim 1, wherein the semiconductor device is provided with a potential of 2. 3. A pull-up transistor for pulling up an input terminal of the second inverter is provided, and a gate electrode of the pull-up transistor is commonly connected to a gate electrode of the FET. 2. The semiconductor device according to 2. 4. The switch is composed of a PchFET, and the gate terminal of the FET has the ground potential or the second
2. The semiconductor device according to claim 1, wherein the semiconductor device is provided with a potential of 2. 5. A pull-down transistor for pulling-down the input terminal of the second inverter is provided, and the gate electrode of the pull-down transistor is commonly connected to the gate electrode of the FET. Semiconductor device. 6. A voltage detection circuit for comparing a reference potential with a potential of the first power supply terminal, wherein a gate potential of the FET is controlled by an output of the voltage detection circuit. 5. The semiconductor device according to any one of 5 to 5.