JPH0973417A - Multiple memory control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain highly reliable memory control under simple control with simple constitution while a method which records the same information in duplex memories is powerless for a fault having the possibility that files in both the memories are destroyed. SOLUTION: This method has a step wherein an information memory is divided into areas 1 and 2, areas of normalcy flags 1 and 2 showing that each wiring process is normal are provided, and the normalcy flags are made ineffective at the time of writing to write data in the area 1, a step wherein the normalcy flag 1 is rewritten after the data writing ends, a step wherein the flags are made ineffective as well, data are written in the area 2, and the normalcy flag 2 is rewritten into normal states, a step the normalcy flags 1 are read out first at the time of reading and the data in the area 1 are read out as normal data when the flag shows normalcy, and a step wherein the data in the area 2 are read out as normal data when the normalcy flag 1 is ineffective and the normalcy flag 2 is normal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiple memory control method for improving reliability of information held in memories of communication equipment and information equipment.

[0002]

2. Description of the Related Art Generally, in an information processing apparatus including a communication device, various setting information and history information are stored in a memory, and the operation of the apparatus and the operation between external management control apparatuses can be performed based on this information. Therefore, these pieces of information are extremely important and should not be impaired by the interruption and interruption of the power supply or the online insertion / removal of the memory board. conventionally,
In order to retain information with high reliability, a memory battery has been provided with a backup battery. However, in order to avoid the holding property and use of the battery, recently, a non-volatile RAM composed of a RAM cell and an EEPROM cell is used. This is because when the voltage value becomes a certain value or less (Vst), the content of the RAM cell is transferred to an EEPROM cell and held (hereinafter, store operation), and the voltage value is a certain value (Vrc). In the above case, the contents of the EEPROM cell are transferred to the RAM cell (hereinafter referred to as a recall operation), and the processor or the like can be accessed. However, also in this method, in a transient state from power ON to OFF (including instantaneous interruption) during writing to the RAM cell, malfunction of the store operation due to noise such as voltage fluctuation or voltage = Vst
ICs around non-volatile RAM with slightly higher voltage value
There is a possibility that incorrect information is written in the RAM cell without guaranteeing the normal operation and the incorrect information is transferred to the EEPROM cell at the voltage = Vst.

As another conventional example, based on erroneous information due to these factors, in order to prevent the device from being restarted after power is restored or a memory board is inserted online, Japanese Patent Laid-Open No. Hei 6 (1994) -1999
-332805 and Japanese Patent Laid-Open No. 5-46494,
The following methods are used to increase the reliability of information. That is, the same information is written in a plurality of areas, the information in each area is read out after the power is restored, and the comparison is performed to determine the reliability. The determination is normal when at least the information read from the two areas is the same.
Further, as another conventional example, in Japanese Unexamined Patent Publication No. 2-125350, when a fixed pattern is written in advance in a plurality of addresses in a memory area and the information is read out after the power is restored, all the information in the plurality of addresses is written in advance. The reliability of the information is determined by whether or not it matches the fixed pattern. FIG. 6 is a block diagram of an example of backup memory control of a communication device or the like. FIG. 7 illustrates a backup memory control method based on the above determination method.
In FIG. 7, the memory area is defined as area 1 (91) and area 2 (9
2) ..., A plurality of areas N (93) are divided. Normally, when information to be written in the memory is generated, the processor or the like writes the information in each of the memory areas 1 (91) to N (93) in steps S81 to S84 ((W
1) to (WN)). After that, when a power failure occurs, these pieces of information are transferred to the EEPROM cell and R is restored after restoration.
Return to AM cell. At this time, in steps S91, areas 1 to N
Of information ((R1) to (RN)),
In steps S92, S93, and S96, the information about the area 1 is mainly compared, and if the information matches the information about at least one other area, the information about the area 1 is regarded as correct. In this example,
Steps S94 and S9 in combination of two or more areas
7, S98 and a considerably complicated judgment process are required.

Further, as another conventional example, Japanese Patent Application Laid-Open No. 4-30
In the Japanese Patent No. 5743, the same volume is written for each file in the two primary and secondary file storage memories 101A and 101B (steps S110 and S111). At the time of reading, it is checked which one is specified as positive (steps S103 and S104), and the file on the positive side, for example, 11
Data is read from 1A (step S105). By the way, this system has a premise that the file 111
Which of A and 111B is the positive side is determined after checking the update record before executing the memory access. That is, there is a process of setting attributes. If there is a defect on one side and it is not updated, it is assumed that the file will be determined to be defective and will become old, and the new one will be positive.

[0005]

Since the conventional backup memory control method is configured as described above, it has the following problems. That is, the method of reading a plurality of pieces of the same information and obtaining the data by comparison or majority decision requires a large circuit scale and processing time. The method of discarding the stored information at the time of abnormality requires a long time for restarting, and history information cannot be obtained, and failure analysis is difficult.
Also, the method of simultaneously recording the same information in the dual memory is effective for hardware failure, but it may cause a failure in which files in both memories may be destroyed, such as a momentary power failure. Was powerless and needed to have a management information file.

[0006]

A multiple memory control method according to the present invention divides a backup information memory containing the same information into two information areas 1 and 2 and each information area 1
Areas of flags 1 and 2 which indicate that writing of flags 1 to 2 are normal are provided.
Invalidate, and then write data to area 1, write back flag 1 after writing data, and similarly invalidate flag, write data to area 2, and set flag 2 to normal. The step of writing back, the step of reading the flag 1 first and reading the data of the area 1 as normal when reading is normal, and the step of reading the data of the area 2 normal when the flag 1 is invalid and the flag 2 is normal. Prepared

Alternatively, an address flag 1 indicating that the writing of the new information area 1 is normal at least temporally and an address flag 2 indicating the writing information area of the immediately preceding time are provided in the memory including the backup information. When writing, the address flag 1 corresponding to the information area 1 is written as invalid, the step of setting the address value of the information area, the step of subsequently writing the data in the information area 1, and the address when the necessary amount of necessary data is written The step of writing back the flag 1 as normal, the step of subsequently setting the value of the address 2 to a required value, the step of reading the address flag 1 first and the step of reading the data of the area 1 as normal when reading the address, If flag 1 is invalid and address flag 2 is normal, is it the value of address 2? The data up to a temporally previous region is provided the step of reading as normal.

Alternatively, flag information areas 1 to N composed of a combination of the address and the flag are provided corresponding to the write information areas 1 to N of the memory, the flag 1 is temporarily invalidated at the time of writing, and the value of the address 1 is set. Information area 1 corresponding to the flag information area 1 of the memory
The step of writing data to the address of the address 1 and the step of subsequently writing back the flag 1 in the flag information area 1 as normal, and the flag 2 are invalidated, the value of the address 2 is set, and the corresponding memory The step of writing data to the information area 2 and writing the flag 2 back to normal is provided up to the information area N. When reading, the flag 1 of the flag information area 1 is read, and if normal, the information area 1 having the value of the address 1 is read. Reading the data as normal, and then reading the flag 2 in the flag information area 2 and reading the data in the information area 2 of the memory corresponding to the address 2 if the reading is normal. The data in the information area corresponding to the address is deleted, and the data is obtained.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. Embodiment 1 of the present invention will be described below with reference to the drawings. In FIG. 1, 11 is a data recording area A,
Similarly, reference numeral 12 is a backup recording area B, and 1 is a normal flag area indicating that normal writing to the area A is completed. Further, (W1) is an invalid value rewrite control of the flag A from the processor, (W2) is information write control to the information area (A), (W3) is a flag A valid rewrite control, and (W4) is an information area. (B) information writing control, (R1) flag A reading control, (R2)
Indicates information read control from the information area (A), and (R3) indicates information read control from the information area (B).

Next, the operation will be described. Normally, when the write information to the backup memory is generated in step S1, the processor or the like sets flag A in step S2.
The value of (actually, an arbitrary pattern of 1 to 2 bytes) is rewritten to an invalid value (for example, all'1 ') (W1). Then, in step S3, information data is written in the information area (A) (W2). In step S4 at the time when all the writing is completed, the flag A is written back to the valid value (W3). If a power failure occurs during this time, writing to the information area (A) has not been completed, and the flag A has an invalid value. Upon completion of (W3), the processor or the like writes the same information in the information area (B) in step S6 (W4).

Next, the control when the power source abnormality occurs and the power source is restored will be described. When the processor or the like recognizes that the power supply is restored, in step S11, the value of the flag A is first read and the following determination is performed. Steps S13a and S13b
If the flag A has a valid value, it is determined that the information in the information area (A) is the latest information and normal information, and the information in the information area (A) is read in step S14. If necessary, the information in the information area (B) is also rewritten to the information in the information area (A) at this time. If flag A
If the value of is an invalid value, it is determined that a power supply abnormality has occurred while writing information in the information area (A).

The writing control to the information area (A) and the information area (B) is performed by the serial processing as described above, so that there is a time difference. Therefore, if a power failure occurs while writing the latest information to the information area (A), the latest information writing control to the information area (B) is not performed, and the previous information of the latest information is normal. It has been saved. As described above, if the value of the flag A is an invalid value, it is determined that there is an abnormality during the data writing in the area A, and therefore the processor or the like reads the information in the information area (B) and updates the latest information. The information immediately before the information restarts the device, the damage is minimized, and a highly reliable system is obtained.

Embodiment 2. FIG. 2 shows an example of the second embodiment, in which a flag B is further provided in the control described in the first embodiment. In FIG. 2, reference numeral 2 denotes an area of a normal flag of B indicating that the normal writing to the area B is completed. Further, (W5) shows flag B invalid value rewrite control, (W6) shows flag B valid value rewrite control, and (R4) shows flag B read control. The other (W1) to (W4) and (R1) to (R3) are
The same thing as in the first embodiment is shown.

Next, the operation will be described. Normally,
When the write information to the backup memory is generated in step S1, the processor sets the flag A in step S2.
The value of is rewritten to an invalid value (W1). After this step S
At 3, the information is written in the information area (A) (W2). In step S4 at the time when all the writing is completed, the flag A is written back to the effective value or less (W3). If a power failure occurs during this time, writing to the information area (A) has not been completed, and the flag A has an invalid value. Up to this point, the process is the same as that of the first embodiment, but after this step S
At 5, the value of flag B is rewritten to an invalid value (W4). Thereafter, in step S6, the same information is written in the information area (B) (W5). Further, in step S7 at the time when all the writing is completed, the flag B is written back to the valid value (W6).
If a power failure occurs during this period, writing to the information area (B) has not been completed, and the flag B has an invalid value.

Next, the control when a power supply abnormality occurs and the power supply is restored will be described. When the processor or the like recognizes that the power supply is restored, first, in steps S11 and S12, the values of the flag A and the flag B are read and the following determination is performed. If the flag A has a valid value in step S13, it is determined that the information in the information area (A) is the latest information and is normal information, and in step S14, the information in the information area (A) is updated. read out.

If the flag A is an invalid value, then the flag B is determined in step S15. If the value of the flag B is a valid value, the information in the information area (B) is the latest information. It is determined that the information is the frontmost information and is normal information, and in step S16, the information in the information area (B) is read. At this time, if necessary, the information in the information area (A) is also rewritten to the information in the information area (B). If the flag B is also an invalid value, in step S17, the abnormal sequence is restarted with the default information, and the memory substrate becomes a failure. According to the embodiment, it is possible to combine the determinations of both the flags A and B to more finely specify the failure portion.

Embodiment 3 FIG. 3 shows an example of the third embodiment, and the amount of information is large in memory control such as sequential writing from a specific address of the backup memory such as history information (writing by incrementing the address by one address). This is an example corresponding to the case where it is difficult to provide the backup memory capacity for two surfaces.
In FIG. 3, 21 is a data recording area, 22 is an area corresponding to address A, 22a is a normal / invalid (writing) recording area of flag A therein, 22b is a recording area of the address value of address A, 23 , 23b are areas for address B and address B value, respectively. Also, (W
21) is the invalid value rewriting control of the address A flag from the processor, (W22) is the address value increment control of the address A, (W23) is the information writing control to the information area (writing to the address set by the address A. ) And (W24) show the effective value write-back control of the address A flag, (W25) shows the address value setting of the address B (the final address value of the address A), and (R21) shows the read control of the address A flag.

Next, the operation will be described. Normally, when write information to the backup memory is generated in step S21, the processor or the like rewrites the value of the flag of the address A to an invalid value in step S22 (W2).
1). Next, in step S23, the address value of the address A is incremented (W22), and in step S24,
Information is written in the address of the information area indicated by the address value (W23). After that, until all the information is written, (W
21) to (W23) are repeated. When all the information is rewritten, the value of the flag of the address A is written back to the valid value in step S25 (W24). If a power failure occurs during this period, writing to the information area has not been completed, and the flag of address A has an invalid value. After that, in step S27, the address value of the address B is set to the same value as the final address A (W25).

Next, the control when the power supply abnormality occurs and the power supply is restored will be described. When the processor recognizes that the power supply is restored, first in step S31, the value of the flag of the address A is read and the following determination is performed. If step S32
If it is a valid value of the flag of the address A, it is determined that the information in the information area is the latest information and normal information up to the address indicated by the address A. Read data up to the address value. If necessary, the address value of the address B is set to the same value as the final address A. If the flag value of the address A is an invalid value, it is determined that the power supply abnormality has occurred during the writing of the latest information, and another predetermined procedure, for example, the address value of the previous address B is used. Processing such as reading. As described above, since the control of the address A and the address B is performed by the serial processing, there is a time lag, and when a power failure occurs while writing the latest information in the information area, the address value of the address B is The address in which the latest information of the latest information is written is normally saved. Therefore, if the value of the flag of the address A is an invalid value, the processor or the like reads the information up to the address set in the address B, and the apparatus is restarted with the latest information of the latest information ( The roll memory method is dealt with by adding roll information to the address value).

Embodiment 4 FIG. 4 shows the second and third embodiments.
In addition to the control described in the third embodiment, the address B is also provided with a flag. In FIG. 4, 23a is a normal / invalid flag area of the address B, and the others are the same as those of the third embodiment. Further, (W26) shows the invalid value rewrite control of the address B flag, (W27) shows the valid value write back control of the address B flag, and (R22) shows the flag read control of the address B. Other (W21) ~ (W
25) and (R21) are the same as those in the third embodiment.

Next, the operation will be described. Step S
The processes from 21 to S24 to the writing back of the flag in S25 are the same as those in the third embodiment. Next, in step S26, the flag of address B is rewritten to an invalid value (W
26), in step S27, the address value of the address B is set to the same value as the final address A (W25). Then, in step S28, the flag of address B is written back to a valid value (W27). During this period, if a power failure occurs, the control for setting the address value of the address B to the same value as the final address A has not been completed, and the flag of the address B has an invalid value.

Next, the control when a power supply abnormality occurs and the power supply is restored will be described. Also in this case, steps S31 to S33 are the same as those in the third embodiment. If the flag of the address A is an invalid value in step S32, then the flag of the address B is read in step S34, and the flag of the address B is determined in step S35. If the value of flag B is a valid value, address B
Up to the address indicated by the address value, the information in the information area is determined to be normal information, and the device is restarted using this data in step S36. If the flag B is also an invalid value, in step S36, the memory board is restarted with the default information as an abnormal sequence, and the memory substrate is made to be a failure (for the roll memory method, the roll information is added to the address value. deal with).

Embodiment 5 FIG. 5 shows an example of the fifth embodiment, which is important information randomly written in address units in the history / setting information and the like.
As shown in, it is an example of an embodiment in which it is difficult to provide the backup memory capacity for two surfaces. In the figure, 41 is a region corresponding to the address ****, 41a is a recording region in which the flag therein is normal / invalid (during writing), 4
Reference numeral 1b is an area for describing an actual data write range address. 42, 42a and 42b are addresses ΔΔΔ respectively
[Delta] [Delta] corresponding areas, the flag normal / invalid, and data write address areas, and 43, 43a and 43b are areas corresponding to the addresses □□□□□. FIG.
(W41) is a writing control of (flag + information) from the processor etc. to the address ***, and (W42) is ΔΔ.
Writing control of (flag + information) to address △△△, (W
43) is (flag + information) write control to address □□□□□□, (R41) is (flag + information) read control from address ***, and (R42) is △△△△△ address (Flag + information) read control from (R43) is □□
□□□ Indicates the (flag + information) read control from address.

Next, the operation will be described. When the write information to the backup memory is generated in the normal time step S41, the processor sets the write address (***** address) and adds a flag (actually, an arbitrary pattern) to the write information in the step S41. And write. If a power failure occurs during this time, ****
* The flag written in the address is an invalid value.
When the data writing is completed, the flag 41a is written back as normal in step S43 (W41), and further in step S43.
At 44, the address ΔΔΔΔΔ address is set. If a power supply error occurs while writing information to the address ΔΔΔΔΔ, the flag written at the address ΔΔΔΔΔ is an invalid value. When the writing of the data to the address ΔΔΔΔΔ is completed, the flag 42a is set in step S45.
Is written back as normal (W42), and the next address is set. This control is repeated until the address □□□□□
After the end of the last write information to, the flag 43a is written back as normal in step S47. If the address □□□□
If a power failure occurs while writing data to □, the flag written to address □□□□□□ has an invalid value.

Next, the control when a power supply abnormality occurs and the power supply is restored will be described. The processor proceeds to step S51.
Then, when the power restoration is recognized, the backup information of each address is read as usual. For example, in step S52, **
When the address information is read out, the value of the (R41) flag is read, and if it is a valid value in step S54, the information in the *** address is fetched in step S56, and if it is an invalid value. It is determined that a power failure has occurred during writing, and that information is discarded. Thereafter, the above operation is repeated, and the same is done for the addresses ΔΔΔΔΔ and □□□□□□ ((R42), (R43)). As described above, write control to each address is performed in serial processing, so there is a time lag, and if a power failure occurs while writing information to a certain address, the flags of other addresses are valid values. , The information is also normal. From the above,
Even if a power failure occurs during writing to the backup memory, the information loss of at most one block address can be suppressed.

[0026]

According to the present invention, a large-scale H / W,
There is an effect that the latest information in the backup memory can be easily confirmed when a power failure is recovered without using a complicated management S / W.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a second embodiment of the present invention.

FIG. 3 is a diagram showing an example of a third embodiment of the present invention.

FIG. 4 is a diagram showing an example of a fourth embodiment of the present invention.

FIG. 5 is a diagram showing an example of a fifth embodiment of the present invention.

FIG. 6 is a diagram showing a configuration example of backup memory control.

FIG. 7 is a diagram showing the configuration and operation of a conventional backup memory.

FIG. 8 is a diagram showing the configuration and operation of another conventional backup memory.

[Explanation of symbols]

1 flag A area, 2 flag B area, 11 information (data) area A, 12 information (data) area B, 21 information (data) area, 22 address A corresponding area, 22a
Address A flag area, 22b Address A value area, 2
3 address B corresponding area, 23a address B flag area, 23b address B value area, 41 address ***
* Corresponding area, 41a flag area, 41b information area,
42 address ΔΔΔΔΔ corresponding area, 42a flag area, 42b information area, 43 address □□□□□ corresponding area, 43a flag area, 43b information area, S2 flag A invalidating step, S3 information A writing step,
S4 flag A normalization step, S5 flag B invalidation step, S6 information B writing step, S7 flag B normalization step, S13 flag A determination step,
S14 information A reading step, S15 flag B determining step, S16 information B reading step, S22
Address A invalidating step, S24 Information A writing step, S25 Address A flag normalizing step,
S26 address B invalidation step, S27 information B writing step, S28 address B flag normalization step, S32 address A flag determination step, S33
Address A value information reading step, S35 Address B flag determination step, S36 Address B value information reading step.

Claims (5)

[Claims] 1. A backup information memory containing the same information is divided into two information areas 1 and 2 and a flag 1 indicating that writing to the information area 1 is normal.
The writing area is provided, and when writing, the above flag 1 is invalidated (writing)
Then, the step of writing the data in the information area 1, the step of writing the flag 1 back to the normal state after the writing in the information area 1, and the step of writing the data in the information area 2 are performed. First, a multiple memory control method including a step of reading the flag 1 and reading the data of the information area 1 as normal if it is normal, and a step of reading the data of the information area 2 as normal if the flag 1 is not normal. 2. Further, after adding a writing area of a flag 2 indicating that writing of the information area 2 is normal, the writing of the information area 1 is normally completed and the flag 1 is written back at the time of writing. , The step of invalidating the flag 2 before the step of writing the data in the information area 2, the step of writing the data in the information area 2 and then writing the flag 2 back as normal, and the flag 1 is normal when reading out. If not, the flag 2 is read next, and if it is normal, it is connected to the step of reading the data of the information area 2 as normal, and if flag 2 is not normal, a step of determining that a failure has occurred is added. The method for controlling multiple memories according to claim 1. 3. An address 1 area in which an address value of a new information area 1 is written at least temporally in a memory including backup information, an area of an address flag 1 indicating that writing in the information area 1 is normal, and a resultant result area. An address 2 area indicating a write information area of the immediately preceding time is provided, and at the time of writing, first writing the address flag 1 corresponding to the information area 1 as invalid (writing) and setting the value of the address 1. Next, a step of writing data in the information area 1, a step of writing back the address flag 1 as normal when the necessary data is written in the required amount information area, and a step of setting the value of the address 2 to a predetermined value, At the time of reading, first, the address flag 1 is read, and if it is normal, the step of reading the data in the information area 1 as normal is performed. When, multiple memory control method comprising the steps of reading the data if the address flag 1 is invalid from the value of the address 2 to the front of the information area as a normal. 4. Further, when the address flag 2 is added and the address flag 1 is written back as normal when writing, the step of writing the address flag 2 as invalid (writing) and the value of the address 2 are written. After the step of setting
When the address flag 2 is written back as normal, and when reading, if the address flag 1 is not normal, the address flag 2 is read subsequently, and if normal, the data from the value of the address 2 to the region preceding in time is read. 4. The multiple memory control method according to claim 3, further comprising a step of determining that there is a failure if the address flag 2 is not normal, connected to the step of reading. 5. A flag information area 1 to N consisting of a set of an address and a flag is provided corresponding to the write information area 1 to N of the memory, and at the time of writing, the value of the address 1 of the flag information area 1 is first set. Then, the step of invalidating (writing) the flag 1, the step of writing the data to the information area 1 corresponding to the value of the address 1 of the memory, and the flag after the data writing to the information area 1 is completed. The step of writing back the flag of the information area 1 as 1 normal (write completed), the step of setting the value of the address 2 for the next writing and invalidating the flag 2 in order, and the information corresponding to the value of the address 2 of the memory The step of writing data to the area 2 and the step of writing back the flag 2 as normal are provided up to the information area N, and the flag information area is used for reading. If the flag 1 of No. 1 is normal and the data of the information area 1 corresponding to the value of the address 1 is normal, then read the flag 2 of the flag information area 2 if normal and the memory corresponding to the address 2 is normal. The multiple memory control method in which the data in the information area 2 is read, and when the read flag is invalid, the data in the information area corresponding to the value of the paired address is discarded to obtain the data.