JPH0969728A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a pseudo sine wave by improving the working efficiency of a CPU which is free from limitation of the clock frequency used for reading of the sine waveform data and also corrects and controls the frequency of the generated pseudo sine wave. SOLUTION: A semiconductor device consists of a sine waveform output ROM 2 which inputs the overflow signal OF of a dividing counter 1 that counts the reference clocks CLK, a D/A converter 3 which converts the data read out of the ROM 2 into the analog signals, a 1st (2nd) correction counter 5 (6) which inputs the overflow signal OF via a switch circuit S1 (S2), and an interruption signal generation circuit 7 which inputs the overflow signals OF1 and OF2 , of the counter 6, and a CPU 8 which rewrites the count value of the counter 1 by means of an interruption signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device that generates a pseudo sine wave.

[0002]

2. Description of the Related Art CTCSS (Conti
nuous Tone-Controlled Squelch System) has the function of outputting a sine wave in the audio frequency band. FIG. 6 is a block diagram of the main part of the microcomputer that generates the pseudo sine wave required for this CTCSS. The sine waveform data read from the frequency division counter 1, sine waveform output ROM 2 and sine waveform output ROM 2 is shown in FIG. Is provided with a digital / analog converter 3 for performing digital / analog conversion.

In this microcomputer, a frequency dividing counter 1 counts a reference clock CLK generated by an oscillation circuit (not shown), which is obtained by dividing a main clock input from the outside by two, for example. When the frequency division counter 1 counts a predetermined number, it outputs an overflow signal OF, and the reload latch provided in the frequency division counter 1 is reloaded with a predetermined value.
The predetermined value to be reloaded is written in the frequency division counter 1 by software or hardware before the frequency division counter 1 counts according to the target tone frequency (standard frequency) of the pseudo sine wave.

Whenever the overflow signal is output from the frequency dividing counter 1, the sine waveform data is sequentially read from the sine waveform output ROM 2 and input to the digital / analog converter 3, and the digital / analog converter 3 is input. The sine waveform data is digital-to-analog converted, and analog values corresponding to the sine waveform data are sequentially output to generate a pseudo sine wave.

Therefore, as shown in FIG. 7, the waveform of the pseudo sine wave SW is obtained by the sine waveform data divided by the output frequency of the overflow signal OF output from the frequency division counter 1 within a predetermined time. Since the analog value is output from the digital / analog converter 3 in this way, the number of outputs is an integer multiple and the frequency accuracy is limited. Especially when the frequency of the reference clock is low, a pseudo sine wave is generated. The time width for obtaining one becomes long and the frequency largely deviates from the standard frequency.

Therefore, a means for correcting the output frequency has been frequently used. There are a correction method for alternately changing the division width that divides one cycle of the pseudo sine wave to be generated into a plurality, and a frequency correction method for changing the division width at the peak position of the pseudo sine wave.

[0007]

However, the frequency of the reference clock is limited in such means for correcting the frequency of the pseudo sine wave. In addition, in any of the frequency correction methods described above, even if the frequency accuracy of the pseudo sine wave is high enough that the accuracy does not matter, the CPU executes the operation to correct the frequency and the CPU load is large. There is a problem of inefficient CPU.

In view of the above problems, the present invention provides a semiconductor device that generates a pseudo sine wave by improving the efficiency of the CPU that controls the correction of the frequency of the pseudo sine wave that is not limited to the frequency of the reference clock. The purpose is to provide.

[0009]

A semiconductor device according to the present invention is provided with a first correction counter and a second correction counter having different counter target values to which a signal based on the count value of a counter for counting a first clock should be input. A signal generating circuit to which a signal output from the first correction counter and the second correction counter should be input according to the count values of the first correction counter and the second correction counter, and a second clock related to the first clock And a correction necessity instruction counter for instructing the necessity of correcting the frequency of the pseudo sine wave, and when the correction necessity instruction counter indicates that the frequency correction is necessary, The counter value of the counter is corrected based on the output signal.

In the present invention, the sine waveform data is read from the ROM based on the count value of the first clock, and the digital / analog conversion is performed to generate the pseudo sine wave. The correction necessity instruction counter counts a predetermined number of second clocks related to the first clock and outputs a second clock related to the first clock.
It detects that the frequency of the clock is high, and instructs the frequency correction of the pseudo sine wave. If the second clock cannot be counted by a predetermined number, it is detected that the frequency of the second clock is low, and an instruction to correct the frequency of the pseudo sine wave is issued. When the frequency correction is instructed, the count operation of the first and second correction counters having different count target values is prohibited, and the count target value of the counter is not rewritten by the output signal of the signal generation circuit.

When it is instructed to correct the frequency, the first and second correction counters are operated to count, and the signal output from the first correction counter is input to the signal generation circuit according to the count value of the first correction counter. Then, the count target value of the counter is rewritten based on the output signal. In addition, the signal output from the second correction counter is input to the signal generation circuit according to the count value of the second correction counter, and the rewritten counter target value is restored based on the output signal. By rewriting the count target value of such a counter, the time width of the generated pseudo sine wave at a predetermined time position changes, and the frequency of the pseudo sine wave changes. As a result, when it is detected that the frequency of the pseudo sine wave is low, the frequency of the pseudo sine wave is corrected and the load on the CPU is reduced.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to the drawings showing the embodiments of the present invention. FIG. 1 is a block diagram showing an embodiment of a semiconductor device according to the present invention. A reference clock CLK generated by dividing a main clock X _IN, which will be described later, output from a clock generator (not shown) by 2 is input to a frequency dividing counter 1 including a reload latch. The overflow signal OF output when the frequency dividing counter 1 counts a predetermined value of the reference clock CLK is input to the sine waveform output ROM 2. The sine waveform output ROM 2 stores the sine waveform data corresponding to each time position obtained by dividing the cycle of the pseudo sine wave to be generated. Sine waveform data read from ROM 2 for sine waveform output is digital / analog converter
(D / A converter) Input to 3.

Overflow signal output from the frequency division counter 1
No. OF has a reload latch via switch circuit S1
Is input to the first correction counter 5 and the switch circuit S2
To the second correction counter 6 having a reload latch via
Is entered. The first correction counter 5 counts a predetermined value
The first overflow signal OF that is output when₁And the second supplement
Output when the positive counter 6 counts a predetermined value
2 Overflow signal OF ₂Enters the interrupt signal generation circuit 7
Is forced. Interrupt output by the interrupt signal generation circuit 7
The request signal INT is input to the CPU 8.

The switch circuits S1 and S2 are turned on when a correction bit clear signal CLR to be described later becomes "L",
It turns off when it becomes "H". The interrupt signal generation circuit 7 is provided with the first and second overflow signals O output from the first correction counter 5 and the second correction counter 6.
When F ₁ and OF ₂ are input, the interrupt request signal INT is output. CPU 8 is an interrupt request signal INT
According to the above, a predetermined interrupt process is performed, and a predetermined value is written in the reload latch of the frequency division counter 1.

FIG. 2 is a block diagram of a frequency correction instruction circuit for instructing the necessity of frequency correction. Most of the recent microcomputers are provided with a circuit for generating a clock for clock display, but here, a microcomputer is provided with a clock clock input terminal 9 to which a clock clock CLK _W having an oscillation frequency of 32 kHz should be input. Clock clock input terminal 9
The clock clock CLK _W input to is input to the frequency divider circuit 10 and the trigger terminal TR of the frequency correction instruction counter 12. The main clock X _IN input to the main clock input terminal 11 to which the main clock X _{IN, which} is the driving clock of the microcomputer, should be input to the frequency correction instruction counter 12.

The divided clock output from the divide-by-2 circuit 10 is AN
It is input to one input terminal 13a of the D circuit 13. The overflow signal output from the frequency correction instruction counter 12 is a latch circuit.
Latch data of the latch circuit 14 is input to the AND circuit.
Input to 13 other input terminal 13b. The correction bit clear signal CLR is output from the AND circuit 13. Then, the frequency correction instruction counter 12 is controlled by the clock for clock CLK _W to start and stop the counting operation,
The main clock X _IN within the period when the clock clock CLK _W is at H level is counted. The latch circuit 14 latches when the overflow signal OF _C of the frequency correction instruction counter 12 becomes H level. The clock clock CLK _W and the main clock X _IN are synchronized as shown in FIG.

FIG. 3 is a timing chart of the clock clock CLK _W and the main clock X _IN , where the horizontal axis represents time and the vertical axis represents signal level. FIG. 4 shows a divide-by-2 circuit 10.
6 is a timing chart of the divided clock, the main clock X _IN, and the overflow signal OF _C output by the above. FIG.
When the frequency of the main clock X _IN shown in FIG. 4 (b) is higher than the frequency A of the divided clock shown in (a) at the H level, that is, the frequency of the clock clock CLK _W , it is shown in FIG. 4 (c). As shown, the frequency correction instruction counter 12 outputs the overflow signal OF _C within the period A in which the divided clock is at the H level.

On the other hand, when the frequency of the main clock X _IN is low, as shown in FIG. 4 (d), the overflow signal OF _C is not output from the frequency correction instruction counter 12 within the period A in which the divided clock is at the H level. . Thereby, it can be determined whether or not the frequency of the main clock X _IN is high.

Here, the count value n of the frequency correction instruction counter 12 is set in advance to, for example, "81". The count value n is set by hardware or software when the microcomputer is shipped. Divide by 2 circuit
Half cycle of divided clock output from 10 is 1 / 32kHz =
It is 31.25 μsec. Here, if the frequency of the main clock X _IN input to the microcomputer is, for example, 2.6 MHz or more, the count value n is "81", so 81/2.
Within the period A of 6 MHz = 31.15 μsec, the frequency correction instruction counter 12 outputs the overflow signal OF _C.

At this time, the latch circuit 14 latches this and outputs the correction bit clear signal CL output from the AND circuit 13.
R becomes H level, and the correction required bit (not shown) of the register (not shown) built in the microcomputer is cleared. Then, when the divide-by-2 clock output from the divide-by-2 circuit 10 becomes L level, the frequency correction instruction counter 12 thereafter stops the counting operation.

On the other hand, when the main clock X _IN input to the microcomputer is 2.5 MHz or less, 81 / 2.5 MHz =
Since it is 32.4 μsec, overflow signal OF _C
Does not occur and the correction bit clear signal CLR does not go to H level. In this way, it is possible to detect whether the frequency of the main clock X _IN is higher or lower than the specified frequency.

Next, the operation of the microcomputer thus configured will be described. Considering the case where the main clock input to the main clock input terminal 11 is 2.5 MHz or less, the correction bit clear signal CLR is “L” and the correction required bit of the register (not shown) is not cleared and is in the valid state. . Set the initial setting value of the first correction counter 5 to "1.
4 ", the initial setting value of the second correction counter 6 is set to" 15 ", and the first correction counter 5 and the second correction counter 6 are set.
Set both reload latch values of to “32”.

Now, when the first correction counter 5 counts 14 times, it outputs an overflow signal OF ₁ , which is input to the interrupt signal generation circuit 7. When the CPU 8 receives the interrupt request signal INT, it executes the first interrupt process and rewrites the reload latch value of the frequency division counter 1 with the correction value. At this time, the value “32” of the reload latch is reloaded into the first correction counter 5.

When the second correction counter 6 counts 15 times, it outputs an overflow signal OF ₂ , which is input to the interrupt signal generation circuit 7. When the CPU 8 receives the interrupt request signal, it executes the second interrupt process and rewrites the latch value of the frequency division counter 1 to the original value. At this time, the value “32” of the reload latch is reloaded to the second correction counter 6.

Thereafter, every time the frequency division counter 1 outputs the overflow signal OF 32 times, the CPU 8 causes the CPU 8 to perform the above-mentioned first operation.
And the second interrupt process are repeated to execute the process of correcting the cycle of the sine wave. When the frequency of the main clock X _IN is 2.6 MHz or higher, the correction bit clear signal CLR is at the H level, the correction required bit is cleared, both the switch circuits S1 and S2 are turned off, and the pseudo sine The correction of the wave frequency is not executed and the CPU 8 becomes irrelevant to the correction operation.

At this time, the first correction counter 5 and the second correction counter 6 can be used as counters for other counting purposes, in other words, the load on the CPU for correcting the frequency of the pseudo sine wave is reduced. It will be. Then, as shown in FIG. 5 by the above-described operation, the generated pseudo sine wave SW is generated at the 15th count and the 15 + 32th count at which the count value of the first correction counter 5 and the count value of the second correction counter 6 overflow. , The time width obtained by dividing the period of the pseudo sine wave into a plurality of times is controlled, and the frequency of the pseudo sine wave is controlled so as not to deviate from the standard frequency.

Further, since the frequency can be corrected in this way, even if the frequency of the main clock input to the microcomputer is different, that is, even if the frequency of the oscillator of the oscillator circuit is different, Can generate a pseudo-sine wave with a standard frequency. It should be noted that although the microcomputer has been described in this embodiment, the invention is not limited to the microcomputer, and the same effects can be obtained by applying the same to a semiconductor device.

[0028]

As described above in detail, the semiconductor device of the present invention executes the correction of the frequency of the pseudo sine wave when the frequency of the second clock related to the first clock is low,
Since the correction of the frequency of the pseudo sine wave is not executed when the frequency of the clock is high, the pseudo sine wave having a frequency close to the standard frequency can be generated even if the frequency of the second clock is different. Moreover, since the frequency of the pseudo sine wave is corrected and controlled by the CPU only when the frequency of the second clock is low, the present invention has an excellent effect such that the load on the CPU is reduced when the frequency is controlled.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of a semiconductor device according to the present invention.

FIG. 2 is a block diagram of a frequency correction necessity instruction circuit.

FIG. 3 is a timing chart of a clock clock and a main clock.

FIG. 4 is a timing chart of each clock and overflow signal.

FIG. 5 is a waveform diagram of a generated pseudo sine wave.

FIG. 6 is a block diagram showing a main part of a conventional microcomputer.

FIG. 7 is a waveform diagram of a generated pseudo sine wave.

[Explanation of symbols]

1 divider counter, 2 sine waveform output ROM, 3 digital / analog converter, 7 interrupt signal generation circuit,
8 CPU, 9 clock clock input terminal, 10 2 frequency divider circuit, 11 main clock input terminal, 12 frequency correction instruction counter, 13 AND circuit, 14 latch circuit.

Claims (1)

[Claims] 1. A ROM storing sinusoidal waveform data based on a count value of a counter that counts a first clock.
In a semiconductor device which reads out sine waveform data from a ROM and digital-analog converts the sine waveform data read out from the ROM to generate a pseudo sine wave, a signal based on the coefficient value should be input. A correction counter and a second correction counter, and the first
A signal generating circuit to which a signal output from the first correction counter and the second correction counter should be input according to the count values of the correction counter and the second correction counter, and a second clock related to the first clock, A correction necessity instruction counter for instructing whether or not the frequency of the pseudo sine wave should be corrected, and based on the output signal of the signal generating circuit when the correction necessity instruction counter indicates that the frequency correction is required. And a semiconductor device configured to correct the count target value of the counter.