JPH096713A - Method for optimization of transfer of data between system memory and pci master device and system for optimization of memory access time in computer - Google Patents

Abstract

PURPOSE: To provide a system for optimizing data transfer time between an external master device and a main memory. CONSTITUTION: The system includes an integrated processor provided with a PCT bridge 80 for adjusting data transfer to/from a PCT master 75 and a memory controller 90 for controlling an access to the main memory. When the PCI master 75 can not timely respond, the bridge 80 asserts a MEMWAIT signal to the controller 90 to indicate the necessity of deceleration of data transfer, applies a succeeding memory address to open a proper page in the memory and asserts a suitable row address strobe line to accelerate succeeding data transfer. When the MEMWAIT signal is deasserted, the controller 90 immediately asserts a column address strobe line to drive data. Since the page in the memory is quickly opened, RAS access time and RAS precharging time can be saved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates generally to transferring data between a memory unit and peripheral components within a computer system. More specifically, the present invention relates to a system for accelerating transactions between components external to a central processing unit (CPU) and main memory. More specifically, the present invention relates to a system for optimizing the transfer of data between main memory and peripheral master controllers.

[0002]

2. Description of the Related Art Data is generally transferred between a memory and other components in a computer system in two steps. First, the accessing component generates a signal on the address bus that represents the address of the desired memory location. On the next or subsequent clock cycle, the component actually transfers data to or from the addressed memory location via the data bus. In most computer systems, the number of clock cycles required to access data in the memory depends on the components accessing the memory and the speed of the memory unit.

The speed of memory circuits is based on two timing parameters. The first parameter is the memory access time, which is the minimum time required by the memory circuit to set the memory address and to generate or capture data via or from the data bus. The second parameter is the memory cycle time, which is the minimum time required between two consecutive accesses to the memory circuit. In dynamic random access memory (DRAM) circuits, which are typically used to form the main working memory of computer systems, the cycle time is typically about twice the access time. D
RAM circuits typically have access times in the range of about 60-100 nanoseconds and cycle times of 120-200 nanoseconds. The extra time required for successive memory accesses in the DRAM circuit is necessary because the internal memory circuit requires additional time to recharge (or precharge) to accurately generate the data signal. Therefore, a microprocessor operating at 10 Mhz will continue to see the same 100 nanosecond chip (ie, with adjacent clock pulses), even though clock pulses in such microprocessors are generated every 100 nanoseconds. ) Two memory accesses cannot be performed. DRAM chips need time to stabilize before the next address in the chip can be accessed. As a result, in such a situation, the microprocessor must go through one or more loop cycles before gaining access to the data in the DRAM circuit. A memory controller unit (MCU) is typically provided as part of the computer system to coordinate access to DRAM main memory.

In addition to the delay caused by cycles and access times, DRAM circuits also require periodic refresh cycles to preserve the integrity of stored data. These cycles consume about 5-10% of the time available for memory access and typically require 256 refresh cycles every 4 milliseconds. DR
If the AM circuit is not refreshed periodically, DRA
The data stored in the M circuit is lost.

Because of these constraints, a memory comprised of DRAM circuits cannot always respond to memory access within a time interval allocated by a central processing unit (CPU) or peripheral master controller. In this case, the external circuit indicates that a supplemental processor cycle or wait state is required until the data is ready via the data bus or until the data from the data bus is stored by the memory circuit. I have to tell the controller). In addition to slowing the CPU's processing, wait states generally require the use of the CPU local bus, thereby limiting access to the bus by other system circuits.

As processor operating speeds increase and new generations of processors are developed, it is advantageous to minimize wait states in order to fully utilize the capabilities of these new processors. However, it is especially difficult to get the maximum benefit of these new generation high speed processors in personal computers due to size and power constraints of other components in the system such as DRAM main memory. In a memory-intensive application involving technical or scientific calculation or a computer-aided design program, the memory access time may significantly delay the operation of the system.

FIG. 1 illustrates a prior art computer system 1.
0 is a block diagram of a microprocessor or central processing unit (CPU) 12 and a C coupled to the CPU 12.
It includes a PU local bus 14, a memory controller 16 and a local bus peripheral 18, both of which are coupled to the CPU local bus 14. System memory 1 coupled to a memory controller 16 via a memory bus 15.
7 is also shown. In addition, PCI standard bus 20 couples to CPU local bus 14 via PCI bus bridge 22. PCI peripheral device 28 coupled to PCI bus 20
Is shown. The PCI peripheral device 28 may include a PCI master controller that can claim ownership of the PCI bus during a PCI master cycle.

The microprocessor 12 shown in FIG. 1 may include a model 80486 microprocessor,
CPU local bus 14 may include an 80486 style local bus. The CPU local bus 14 has a data line set D [31: 0] and an address line set A.
[31: 0], and a set of control lines (not specifically shown). Details regarding the 80486 CPU local bus 14 protocol and various bus cycles are well known in the art and can be found in many publications and will not be discussed in detail here. CPU 12, memory controller 16 and PCI bus bridge 22 were conventionally manufactured on separate integrated circuit chips. However, recent trends in computer systems include CP
The U core is combined with various peripherals on a single integrated processor chip. An exemplary integrated processor chip includes a bus bridge that provides a high performance interface between an internal CPU local bus and an external PCI bus. By providing a high performance interface to the external PCI bus, relatively high performance characteristics can be achieved for external data transfers.

The PCI bus bridge 22 provides a standard interface between the CPU local bus 14 and the PCI bus 20. In this way, the PCI bus bridge 22
Coordinates the transfer of data, address and control signals between the two buses. PCI bus 20 typically includes a high performance peripheral bus that includes multiplexed data / address lines, which supports burst mode data transfers.

The burst mode feature allows for fast read or write to consecutive memory locations over a burst cycle on the PCI bus. In the normal procedure for reading or writing from memory, the CPU generates an address signal on the address bus on the first clock cycle and data is transferred to and from system memory 17 on subsequent clock cycles. It 32 data buses
Because of the bit width, a total of 4 8-bit bytes of data can be read or written by the CPU every 2 clock cycles. Each set of four 8-bit bytes transferred over the data bus is referred to as a "doubleword". In burst mode, additional sequential doublewords can be transferred during subsequent clock cycles without interfering with the address stage. For example, since only the start address is sent over the address bus,
A total of 4 doublewords is C using only 5 clock cycles.
It is read into the PU, then the first doubleword data is read during the second cycle, the next doubleword data is read during the third cycle, and so on. This allows burst mode operation to provide a relatively high data rate.

As will be appreciated, PCI peripheral device 28 may include a PCI master controller. According to conventional techniques, a PCI master can request "ownership" of a PCI bus to control transactions over the PCI bus 20. As will be appreciated by those skilled in the art, multiple PCI masters may be included in a computer system, any of which may request ownership of PCI bus 20. The PCI master is connected to the PCI bridge 22 via the control line in the PCI bus 20 and the PCI bus 2
Make a request for ownership of 0. PCI bus bridge 22 typically arbitrates ownership requests between various PCI masters and between internal masters such as CPU 12 and other internal masters. Each of the various masters is typically assigned a priority rank to assist the bus bridge 22 in determining its priority.

The PCI bridge 22 can operate as both a PCI master and a local bus master. CPU1
When 2 accesses a PCI "slave" external to the integrated processor, PCI bridge 22 operates as a PCI master. Typically, these P's of PCI bridge 22
During the CI master cycle, the CPU 12 or another local bus master (eg DMA controller)
Owns U local bus 14 and PCI bridge 22 is P
Owns the CI bus 20. Conversely, CPU local bus 1
For PCI external master access to devices residing on device 4, PCI bridge 22 acts as a target or slave to the external master and acts as a master of CPU local bus 14.

As a result, when the PCI master (ie, peripheral device 28, etc.) takes ownership of PCI bus 20 and initiates a cycle corresponding to a device on the CPU local bus such as memory controller 16, PCI bridge 22 will Take ownership of the local bus 14. During this period, CP
U12 and other internal masters cannot use local bus 14. As a result, since access to the data in the main memory 17 requires at least several clock cycles as described above, a considerable delay may occur in the operation of the system. You must wait while the data is being accessed in /. This problem is compounded by the fact that PCI masters can transfer data at very slow rates and can transfer multiple doublewords during burst data transfers. As a result, the slow access of the PCI master to the system memory 17 limits the bandwidth of the system memory bus and the CPU local bus.

[0014]

SUMMARY OF THE INVENTION The problems outlined above are related to peripheral PCI.
It is largely solved by providing a computer system that includes a PCI bridge that coordinates data access from the master device to main memory. The PCI bus bridge translates burst memory cycles performed by the PCI master into a single memory cycle on the CPU local bus. Data by driving the memory address of the next data transaction via the CPU local bus when the PCI master is not ready to send data during a write cycle or receive data during a read cycle The PCI bridge works to optimize transactions. The memory controller unit (MCU) receives the memory address from the CPU local bus, determines that it is in the valid memory area, and decodes the address signal into a row address signal and a column address signal. The row address signal is immediately DRA
Row address strobe signal (RAS) appropriate for M memory
With pages and banks of memory that are input and accessed with. The DRAM memory responds by opening the appropriate page of memory and the precharge time that would be required to open the DRAM page if the MCU had to wait until the PCI master was ready to give or receive data. And save access time.

When the PCI master gives write data,
While waiting for the CI bridge or the PCI master to indicate that it is ready to receive read data (after the first data transaction for burst write and read), the PCI bridge sends the MEMWAIT signal to the MCU.
To indicate that the data is not yet ready to be written or read. However, during this MEMWAIT period, and PCI
While it has ownership of the local bus, the MCU uses the next address signal to open the appropriate page of memory to speed up subsequent data transfers. When data is received from the master by the PCI bridge (or indicating that the master is ready to read the data), the PCI bridge deasserts the MEMWAIT signal and the MCU asserts the column address strobe (CAS) signal. , Transfer data.

Effectively asserting the MEMWAIT signal while the PCI bridge waits for the PCI master to send the next write data or to indicate that it is ready to read the data currently latched by the PCI bridge. At the same time, the PCI bridge drives the local bus address strobe ADS # to drive the memory address of the next transaction, including the next data transaction. By initiating the next data transaction by applying the address and control signals, the MCU decodes the address signals and D
The RAM page can be opened, while at the same time the master device is ready to receive or drive data. DRA
While the M page is open and the MEMWAIT signal is active, the MCU "slows down" or waits until the PCI bridge deasserts the MEMWAIT line to indicate that the PCI master is ready to complete the data transfer. Loop through.

When the MEMWAIT line is deasserted by the PCI bridge, the MCU "accelerates" the memory access, leaving the DRAM page open and BRDY #.
Complete the cycle by asserting the line. When BRDY # is asserted, the PCI bridge begins the next cycle by asserting ADS # and driving the new address onto the CPU local bus. The PCI bridge asserts MEMWAIT to slow down the memory bus while the MCU decodes the address and the next access will be the same DRAM page or DR
Determine if it is in the AM bank. MEMWAI
The next access is made by opening the appropriate DRAM page while T is asserted.

During the period when MEMWAIT is asserted,
A refresh cycle may be initiated by the system timer on any of the banks of system memory to refresh the DRAM circuitry within that bank. The MCU must first latch the addressed memory location before the refresh cycle is serviced. After the refresh is complete, the previous page in memory is reopened unless an address to another page is received in the meantime.

Other objects and advantages of the present invention will become apparent upon reading the following description with reference to the accompanying drawings.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will herein be described in detail. However, the drawings and their detailed description are not intended to limit the invention to the particular forms disclosed, as the invention is intended to include all modifications and equivalents within the scope and spirit of the invention as defined by the appended claims. And alternatives.

[0021]

DETAILED DESCRIPTION Referring now to FIG. 2, a computer system configured in accordance with the preferred embodiment generally includes an integrated processor (IP) 50 and an external PCI master connected to integrated processor 50 via PCI bus 100. 7
5 and a main memory unit 125, which preferably comprises DRAM circuitry connected to the integrated processor 50 by a memory bus 150. The integrated processor 50 is preferably a CPU core 60 and a C coupled to the CPU core 60.
PU local bus 65, local bus 65 and external PC
A memory controller unit (MCU) 9 and a PCI bus bridge 80 capable of interfacing data, address and control signals with the I-bus 100.
0, a timer 85, and an on-chip peripheral device 70. Each of the illustrated components of integrated processor 50 are preferably manufactured on a single integrated circuit and housed in a common integrated circuit package.

In the preferred embodiment, CPU core 60 implements a model 80486 microprocessor instruction set and CPU bus 65 comprises a model 80486 style local bus. Therefore, in the preferred embodiment,
The CPU local bus 65 has a 32-bit data line D [31: 0] and a 32-bit address line A.
[31: 0] and a set of control lines (not specifically shown). However, it should be understood that the CPU core may be configured to implement other microprocessor type instruction sets without departing from the principles of the present invention.

As will be appreciated by those skilled in the art, PCI bus bridge 80 preferably forms part of a bus interface unit (BIU) (not specifically shown), and C
It provides a standard interface between the PU local bus 65 and the PCI bus 100. As such, the PCI bus bridge 80 coordinates the transfer of data, addresses, and control signals between the CPU local bus 65 and the PCI bus 100. As will be appreciated, CPU local bus 65 preferably includes an 80486 style local bus, which includes separate address and data lines, as is well known to those skilled in the art, while PCI bus 100 is multiple multiplexed. Includes address / data lines. Therefore, as will be appreciated by those skilled in the art, PCI
The bus bridge 80 is preferably 3 of the local buses 65.
2-bit address lines A [31: 0] are connected to PCI bus 1
Function to connect to the multiplexed address / data lines AD [31: 0] on 00 through an appropriate multiplex unit (not shown). Similarly, P
The CI bridge 80 connects the 32-bit data lines D [31: 0] of the local bus 65 to the multiplexed address / data lines AD [31: of the PCI bus 100.
0] directly.

The PCI bridge 80 also has several control signals, ADS #, R / W, M / IO, byte enable (C / BE #), D /, which are driven through the control lines of the CPU local bus 65. Generate C and BLAST #. In accordance with normal convention, ADS # is an address strobe control signal which functions to initiate a read or write cycle via CPU local bus 65. PCI
Bridge 80 generates the ADS # signal for bus cycles with the target on local bus 65. A
The DS # signal is preferably an active low strobe signal. PCI bridge 80 also generates an R / W signal in response to the state of the C / BE # (0) line on the PCI bus to indicate whether the transaction involves a read or write cycle. M / IO indicates the cycle status to the memory or I / O device. Finally, BLAST
The # signal indicates whether data is being transferred in a single access on the local bus or in burst mode. According to the preferred embodiment, the PCI bridge 80 also sends a MEMWAIT signal to and receives a MEMWAIT signal from the memory controller unit (MCU) 90. These signals may be transmitted via a direct electrical connection between the PCI bridge 80 and the MCU 90 as shown in FIG. 2 or provided via control lines within the CPU local bus 65. Good.

PCI bridge 80 also receives the RDY # / BRDY # control signals from a component on the CPU local bus to indicate the completion of a cycle by that component. For example, memory controller 90 asserting BRDY # indicates that it is providing data or has received data over data lines D [31: 0]. On the side of the PCI bus 100, the PCI bridge 80
Is preferably a PCI master 75, as shown in FIG.
To the TRDY # output signal which is connected to the control line via the control line. Similarly, the PCI bridge 80 is preferably P
Receive IRDY # from PCI master 75 via a control line between CI master 75 and integrated processor 50.
Data is transferred when both IRDY # and TRDY # are asserted.

The CPU internal local bus 65 is preferably a multi-master bus capable of supporting multiple bus masters. CPU60, PCI bridge 80,
And peripherals 70 (which may include, for example, a direct memory access controller) each include a CPU local bus 65.
Can claim ownership. Ownership of internal local bus 65 by these internal masters is typically arbitrated by a bus interface unit (BIU) or other bus arbiter (not specifically shown).

PCI bridge 80 may function as a PCI master, as described in more detail below in the description of the operation of the present invention. The integrated processor 50 is an external PCI
When you access the "slave", the PCI bridge 80
Acts like any other external PCI master by taking ownership of the PCI bus 100. Therefore, CP
When the U-core 60 or peripheral device 70 claims ownership of the CPU local bus 65, the PCI bridge 80 preferably takes ownership of the PCI bus 100 if the cycle is directed to a device on the PCI bus 100. Insist.

Conversely, when a PCI external master seeks access to a device on CPU local bus 65, PCI bridge 80 acts as a target or slave to the external PCI master. The PCI bridge in response executes a corresponding cycle on the CPU local bus 65, thereby allowing the external PCI master to read and write data allocated in, for example, system memory 125. Therefore,
During these PCI master cycles, the external PCI master owns the PCI bus 100 and the PCI bridge 80 owns the local bus 65. PCI bridge 80 is C
When requesting ownership of the PU local bus 65, H
When an OLD request is issued to the CPU 60 and mastership is given, the CPU 60 returns an acknowledge signal HLDA to the PCI bridge 80.

Memory controller 90 preferably includes an integrated control unit that supports a high performance 32-bit data path to main memory 125. In the preferred embodiment, the memory controller 90 uses industry standard modules to provide a direct connection of four 32-bit banks supporting up to 256 MB of DRAM. The MCU 90 controls access to the main memory 125, connects to the CPU local bus 65, and connects the CPU 60 and the PCI bridge 80.
And a path to memory for other peripherals (generally shown as 70). As mentioned above, MCU
90 preferably provides a MEMHIT signal to and receives a MEMWAIT signal from PCI bridge 80 in accordance with the principles of the present invention. The MCU 90 receives the timing signal from the system timer 85.

Continuing to refer to FIG. 2, the MCU 90 preferably connects to the main memory 125, address lines MA [11:
0], memory data lines MD [31: 0], row address strobe (RAS) lines RAS # (3: 0), column address strobe (CAS) lines CAS # (3:
0) and the write enable line WE #. Address signals are transmitted over the memory address lines MA [11: 0] to select the location in memory to be accessed for the multiplexed and non-multiplexed memory devices. The data lines (MD31-MD0) are memory data bus lines for transferring data to and from the DRAM circuit and integrated processor 50, or other external device, according to conventional techniques. The write enable signal WE # indicates whether the memory access is a write cycle, typically W on the CPU local bus.
/ R control signal.

In accordance with conventional techniques, the row address strobe (RAS) lines (RAS3 # -RAS0 #) are preferably for clocking in row address data from the memory address bus MA [11: 0] for each DRAM bank. It includes an active low output used by the DRAM circuit. In the preferred embodiment, one RAS line is dedicated to each bank. In the preferred embodiment, where four DRAM banks are used, four RAS lines are provided.
Similarly, four column address strobe (CAS) lines (CAS3 # -CAS0 #) have 1 CA per byte.
At S, it is provided as an active low output used by the DRAM circuit to clock in column address data from memory address bus MA [11: 0] to each bank of DRAM bytes. So, for example, CAS3 #
Is the DRAM column address strobe for byte 3 in each DARM bank.

Continuing to refer to FIG. 2, main memory 125 preferably includes DRAM circuitry arranged in banks, each bank being 32 bits (ie, 4 bytes) wide. As will be appreciated by those skilled in the art, each DRAM bank is typically subdivided into "pages". The page size depends on the size of each DRAM chip used. DRA with fewer connector pins to reduce the number of chips that can be placed on the system board
DRAM to enable M chips to operate
The chips are addressed in a multiplexed fashion.
That is, the address of each memory cell is transmitted in two parts. The first half of the address defines the row address,
The second half defines the column address. In the preferred embodiment, the first twelve lines of the memory address bus MA (11: 0) are multiplexed outputs, carrying row address locations during the RAS signal and column address locations during the CAS signal. Therefore, individual memory cells are selected by column and row addresses. The conventional manner in which row address and column address signals are input to DRAM memory is shown in the conventional timing diagrams of FIGS. FIG. 3 (read cycle) and FIG. 4 (write cycle)
When the RAS (row address strobe) control line is asserted (ie, RAS
Is driven low), the row address is driven to the address input of the DRAM memory. This clocks the row address into the internal row address latch. The row address is RA
It must be stable between the period before S is asserted (t _ASR ) and the period after RAS is asserted (t _RAH ). The address input is then converted to the column address and CAS (column address strobe) is asserted (CAS is driven low). CAS also functions as an output enable to ensure that the tristate driver on the data pinout is enabled whenever CAS is asserted. The time that CAS can be asserted is determined by the minimum RAS to CAS delay period (t _RCD ). Access time from RAS (t _RAC ) and CAS
After both access time (t _CAC ) from
The data will be available. The performance limit is determined by the access time from RAS (t _RAC ). Another timing parameter that is crucial for memory access is the RAS precharge time (t _RP ). Precharge time (t _RP ) is the time required for the DRAM circuit to recover from a previous access. Another cycle to the same DRAM device is not started at the moment the data becomes available. Therefore, the cycle time for the dynamic memory exceeds the access time. The difference between the access time and the cycle time is the precharge time. These timing characteristics of DRAM circuits are crucial when trying to expedite memory transactions.

Continuing to refer to FIG. 2, another important factor regarding the operation of the DRAM main memory 125 is the DRAM.
It relates to the need for periodic refreshing of the circuit. As will be appreciated by those skilled in the art, there is typically only one transistor used in each DRAM circuit to store a data bit. The transistor simply acts as a switch that stores a small charge on the capacitor. The amount of charge determines whether a "0" or a "1" is stored. Since there is leakage in any capacitor, the charge on the capacitors in the DRAM chip will slowly dissipate as a result of the loss of the insulator. Eventually the charge on the capacitor will be completely dissipated and the memory contents may be lost. A solution to this problem is to read the DRAM circuit before the data is lost and DRA the same data.
To rewrite to the M chip. This procedure is
M is called "refresh".

The DRAM refresh rate is preferably derived from the system timer 85. In the preferred embodiment, a "hidden" pre-RAS CAS staggered refresh mechanism is used so that most DRAM refresh cycles do not impact system performance. To further minimize the period required for a refresh cycle, MCU 90 preferably does not perform a refresh cycle on empty banks (ie DR
If no DRAM circuit is provided in a specific bank of AM memory). If you shift the refresh time, each DR
Instantaneous current demand is reduced by individually refreshing the AM banks. In this manner, bank 0 is refreshed, then bank 1 is refreshed, and so on. The period in which the refresh cycle occurs is determined by the system timer 85. The clock provided by the timer is preferably a standard frequency (25
6 KHz) and the refresh cycle is 4
Starting every microsecond, the effective refresh period is 256 cycles per millisecond. As a result, each DRA
The timer output can be used to drive the M banks separately and continuously within the standard refresh period of 4 milliseconds for 256 refresh cycles. In this manner, each bank is approximately 15.625μ without any banks being refreshed at the same time.
Receive refresh cycles at a standard rate of seconds. According to the prior art, the refresh cycle is initiated by asserting CAS before the leading edge of RAS, which does not occur during normal DRAM access.

On-chip peripheral block 70 represents various peripherals that may preferably be implemented within integrated processor 50. For example, components such as a direct memory access controller (DMA) or interrupt controller may be included as an integral part of the integrated processor package. Various peripherals are provided as part of the integrated processor 50, as will be appreciated by those skilled in the art.

Continuing to refer to FIG. 2, PCI bus 100
The PCI master device 75 will be described in detail below.
The PCI bus 100 is a high performance 3 with multi-master capability that can support several PCI masters.
2-bit multiplex address / data bus.
In a preferred computer system embodiment, which PC
The I-master can also request control of the PCI bus, and once granted ownership of the bus, can issue cycles to any PCI target device.

Control lines of the PCI bus 100 and multiplexed address / data lines AD [31:
0] preferably connects to PCI peripheral components such as PCI master 75 and PCI bridge 80. The control lines preferably include command / byte enable, cycle frame signals, target ready signals, and initiator ready signals. Command / Byte Enable (C / BE3 # -C / BE0 #) carries the multiplexed transfer command and byte enable data over the same line. The command / byte enable line C / BE [3-0] # defines the bus command in the address stage. C / BE during the data phase
[3-0] # is used as a byte enable that determines which byte lane has meaningful data.

The cycle frame signal (FRAME #) is a sustain input / output signal and preferably includes an active low signal driven by the PCI master to indicate the start and continuation of a transaction. Therefore, FRA
ME # signals the start of a bus transaction when asserted. When FRAME # is deasserted, the transaction is in the final data stage. Note that IRDY # must be asserted on the same clock edge as FRAME # deasserts, which marks the final data stage.

Target / Local Bus Ready (TRD
Y # / LRDY #) contains an active low input signal that is driven by the PCI and CPU local bus targets to indicate the target's ability to complete the current data phase. The initiator ready signal (IRDY #) used in conjunction with TRDY # includes an active low signal that indicates the PCI master's ability to complete the current data phase. During a write cycle, for example, IRDY # indicates that valid write data is at AD [31-0].

A further feature of the PCI bus is the publication "PC," published by the PCI Special Interest Group of Hillsboro, Oregon.
I Local Bus Specification "(PCI Local Bus Specification
) And incorporated herein by reference.

Continuing to refer to FIG. 2, the operation of the present invention will be described in accordance with the preferred embodiment. The PCI master 75 is
Request ownership of the PCI bus 100 by driving the request through the PCI bus. In response to this, the PCI bridge 80 sends a HOLD signal to the CPU 60.
To request ownership of the CPU local bus 65. The CPU 60 grants ownership of the local bus 65 by asserting the HLDA signal, which is the P
Received by the CI bridge 80. PCI bridge 80 acknowledges that PCI master device 75 owns PCI bus 100 by sending the appropriate bus grant signal to master device 75.

When the FRAME # signal is asserted by the PCI master 75, the multiplexed address data lines AD [31: 0] of the PCI bus 100 become
It is driven by the PCI master 75 at an effective address.
The PCI bridge 80 captures the address and sends it to the CPU
It is given via the local bus 65. If the address corresponds to a location in memory, the MCU 90 issues a MEMHIT signal to the PCI bridge 80, which then issues a device select (DEVSEL #) to the PCI master to claim the transaction. . P
The cycle definition / byte enable lines C / BE [3: 0] on CI bus 100 are then driven with a cycle state opcode, indicating that the current cycle is a write (or read) operation. According to the preferred embodiment, the PCI bridge M / IO signal is captured from the C / BE [2] line of the PCI bus and the PCI bridge read / write signal R is read.
/ W is captured from the C / BE [0] line of the PCI bus. Next (in the write cycle), the PCI master 7
5 sends the data to be written via the AD line of the PCI bus 100 and asserts the IRDY # signal to indicate that valid data is on the PCI bus.

If the cycle initiated by PCI master 75 is burst mode operation, PCI master 75
Sends the initial memory address and then drives the data signal through PCI bus 100. PC in the subsequent cycle
The I-master 75 only drives the data signal over the bus 100, knowing that the memory address should be incremented by 4 bytes for each successive data transmission.

In response to the burst transmission from the PCI master 75, the PCI bridge 80 is back-to-bac
k) Generate a sequence of memory cycles. When the CPU is put on hold by the PCI bridge 80, the PC
The burst cycle from the I master 75 is transformed into a sequence of single cycle data transfers on the CPU local bus 65 by holding the BLAST # signal asserted in accordance with conventional techniques. In accordance with the principles of the present invention, each single access to main memory by PCI bridge 80 allows the speed of a PCI master to be compromised without compromising performance, even when the master device is operating at full speed. You can accelerate and decelerate.

The operation of the present invention differs depending on whether the PCI bridge is performing a memory write cycle or a memory read cycle. Each of these cycles will be described in detail below. During a write transaction, the burst cycle from PCI master 75
The I-bridge 80 converts the sequence of single-cycle write access on the CPU local bus 65. P
First, the CI master first detects the AD line AD [3 of the PCI bus.
1: 0] to drive the address of the location in memory that you want to access. In response, the PCI bridge 80 drives the address via the CPU local bus 65,
EMHIT is issued by the MCU 90 (if a hit occurs). Device select is PCI bridge 8
Asserted by 0 and returned to PCI master. P
Data is driven by the CI master through the PCI bus (shown as IRDY #) and the PCI bridge 80
Data is latched in (indicated by TRDY #). The PCI bridge 80 is the first from the PCI master 75.
When the PCI bridge 80 receives the data information and address of C, the PCI bridge 80 asserts the ADS # signal and sends the address and data signals to the CPU local bus.
Start the cycle via PU local bus 65.
The MCU 90 advances the writing of data to the specified address in the memory, and the PCI is transferred via the CPU local bus 65.
The BRDY # control signal is asserted to the bridge 80 to indicate that the first doubleword of the data write cycle has been received.

For subsequent data writes to the memory (during a burst cycle over the PCI bus), the present invention is by issuing MEMWAIT and M
The memory is "accelerated" by providing the CU 90 with the memory address of the next doubleword data before the corresponding doubleword is received from the PCI master 75. This causes the MCU 90 to open the page in memory to which the data has been previously written. As a result, the MCU 90 can essentially determine "look ahead" where the next data write will occur and access that page of memory before the data is actually transmitted by the PCI master 75. Can start.

As for the ability to look ahead, the MCU 90 has a BDR.
This is accomplished by initiating the second and all subsequent data transfers during the burst cycle immediately after returning the Y # signal. After receiving the BRDY # signal from the MCU 90, the PCI bridge 80 asserts the TRDY # signal to target the PCI master device 75 (ie, M
CU) has completed or is ready for the data write transaction. On the next clock signal, the PCI master also drives the next data to be written if it is ready and asserts IRDY # to indicate that valid data is being driven through the AD line. Good. However, if the PCI master 75 is slow and the data is not yet ready to be carried, IRDY
# Is deasserted by the PCI master to indicate that it has no valid data ready. IRDY #
Is deasserted in the clock cycle following the assertion of TRDY #, the PCI bridge 80
The signal continues to be asserted to the MCU 90, preventing the MCU from writing invalid data. Note that the MEMWAIT signal is unconditionally asserted for at least one clock cycle. In addition to providing the MEMWAIT signal, the PCI bridge 80 drives the memory address of the next write location via the CPU local bus 65,
At the same time, assert the ADS # signal, which causes the MCU
90 is to latch the address signal. The MCU then asserts the appropriate row address strobe (RAS) line, thereby allowing the page at which the next address is located to open in the appropriate bank in DRAM memory.

When the PCI master device 75 is ready to drive data as indicated by the assertion by the master of IRDY #, the data is transferred from the PCI bus 100 to the PCI bus 100.
It is transferred to the CPU local bus 65 via the bridge 80, and the MEMWAIT signal is deasserted by the PCI bridge 80. In response, MUC 90 latches the data and asserts the column address strobe (CAS) to complete the transfer. As a result of this procedure, RAS access time (t _RAC ) can be saved if the addresses are in different DRAM banks, and R if the addresses are in different pages in the same DRAM bank.
Both AS access time (t _RAC ) and RAS precharge time (t _RP ) can be saved.

On the contrary, in the first cycle of the burst read transaction by the PCI master 75, the cycle for the system memory 125 is the PCI bus 10.
Started after mastership of both 0 and CPU local bus 65 has been achieved. The PCI master 75 is F
A cycle is indicated by asserting the RAME # signal to drive the address line of PCI bus 100 with the address of the requested data. PCI bridge 80
Drive addresses in memory to be read at substantially the same time. The MCU 90 receives the read address, and if the address corresponds to the address in the main memory 125, the ME 90
The MHIT signal is issued, and in response, the PCI bridge issues the DEVSEL # signal to the master 75. PCI
The master 75 continues the transaction and the PCI bridge 80 asserts the local bus address strobe signal ADS # to cause the MCU 90 to latch the address signal. The MCU 90 then proceeds to access rows and columns of memory and returns valid data, which is the local bus 6
5 asserted by BRDY #. In response, PCI bridge 80 issues a TRDY # signal on PCI bus 100 to immediately begin the next read cycle to memory.

Unless the PCI master 75 asserts the IRDY # signal in response to (or before) the TRDY # signal, the PCI bridge 80 causes the MCU 90 to MEMWA.
The read cycle is accelerated or decelerated by asserting IT. ME
While MWAIT is asserted, MCU 90
It receives the next read address from I-bridge 80 and decodes the address signal into row and column addresses. MCU9
The 0 then opens the page in memory where the read address is located with the row address enabled by assertion of the appropriate RAS line. In the preferred embodiment, MCU 90 also drives data into memory bus 150 by providing the column address enabled by the appropriate CAS line. As a result, MEMWA
The data to be read is driven onto the local bus while IT is still asserted.

When PCI master device 75 asserts IRDY # and receives the first data stage, the next read cycle proceeds with PCI bridge 80 deasserting MEMWAIT. When the next data is loaded onto the local bus according to the preferred embodiment, the MCU 90 will
The PCI bridge 8 responds immediately with an RDY # signal.
0 issues the TRDY # signal to indicate to the PCI master that it is ready to read the next data stage. TRD
After issuing the Y # signal, the PCI master immediately begins the next read cycle by asserting ADS # to drive the next read address via the local bus and asserting MEMWAIT.

The principles of the present invention can also be implemented during refresh cycles to allow refresh cycles to be performed while MEMWAIT is asserted. If a refresh request is issued to the same DRAM bank in which the page is opened while MEMWAIT is asserted, MCU90
Preferably, the pre-RAS CAS refresh cycle is initiated by keeping the CAS line active and deasserting the RAS line to initiate the precharge cycle. When the precharge cycle is complete, the MCU 90 asserts the RAS line to initiate the refresh cycle until the t _RAS time is encountered, at which time the RAS line is deasserted and the precharge cycle begins again. When the precharge cycle is complete, the MCU 90 reopens the previous DRAM page and continues to slow down the memory bus if MEMWAIT is still asserted.

When MEMWAIT is deasserted during the refresh cycle, MCU 90 preferably t.
Wait until it encounters the _RAS, begin a precharge cycle to deassert RAS line. When the precharge cycle is complete, the MCU 90 opens the previous DRAM page and asserts BRDY # to the PCI bridge 80 before completing the memory access. Different DRAM until a refresh request occurs or by another master
DR until subsequent data access to page
The AM page remains open. The time saved in this sequence by opening the DRAM page first after the refresh is complete is the t _RAC period.

If a refresh request is issued to a different DRAM bank while MEMWAIT is asserted, then the MCU 90 preferably deasserts the current active RAS line while keeping the CAS line active to assert the current page. Close and immediately assert the RAS line of the new bank to start the refresh cycle. The new RAS line remains active until t _RAS is encountered, at which point the RAS line is deasserted and begins precharging. When the precharge cycle is complete, the MCU 90 opens the previous DRAM page and continues to slow down the memory bus if MEMWAIT is still asserted.

Conversely, during the refresh cycle, the MEM
If WAIT is deasserted, the MCU preferably t
Wait until it encounters the _RAS, begin a precharge cycle to deassert RAS line. At the completion of the precharge cycle, the MCU opens the previous DRAM page and BR
After asserting DY #, the memory access is completed. The DRAM page remains open until a refresh request or another PCI master issues a memory request for a different page. Again, the time saved by opening the DRAM page in advance after the refresh is complete is the t _RAC period.

To further understand how the protocol of the present invention is implemented, an exemplary timing diagram is described. 5-9 are timing diagrams showing data, address and control signals associated with read and write cycles to various locations in main memory. The state of the DRAM memory is shown in the bottom row of the timing diagrams for a better understanding of these figures.

First, referring to FIG. 5, the DRA in the main memory
Accelerated memory read cycles are shown for two consecutive accesses to memory for the same page of M banks. Initially, a page in memory is open, as shown in the DRAMSTATE display, which shows a previous memory access to the same page. During this initial period, the RAS (1) line is asserted to indicate that bank 1 of the DRAM memory has been accessed and that bank's page is open.
The PCI bridge then drives (1) the ADS # control signal low, (2) asserts the W / R signal high to indicate a write cycle, and (3) sends the address and data information over the local bus. The write cycle is initiated by applying According to conventional technology, the MCU
BRDY # is asserted early in the first T2 cycle until the memory write actually completes that cycle. Shortly thereafter, the MCU asserts the CAS (2) line and completes the data write.

The PCI bridge sends the BRDY # signal to the MCU.
As soon as it is received from the device, it asserts the ADS # signal to start the next cycle, which is a read cycle, as indicated by the W / R line being driven low. At the same time, the PCI bridge asserts the MEMWAIT signal to slow down the memory bus. According to a preferred embodiment,
Address signals are provided to the MCU while MEMWAIT is asserted. Since the DRAM page has already been opened, the MCU is in the state shown in FIG.
It is not necessary to open the page by changing the state of the S line. However, in the preferred embodiment, the MCU asserts the CAS line (in this case CAS (2)) to drive the data to be read onto the memory bus and thus onto the local bus. When MEMWAIT is deasserted, the MCU asserts BRDY # and
Indicates that data is available and the DRAM page remains open for the next cycle.

Therefore, if the address is in the same DRAM page, the PCI bridge 80 causes the MEMWAI
The MCU 90 may loop through the wait state cycle until the T is deasserted or a refresh cycle request is issued by the MCU 90.
Decelerate 0. When MEMWAIT is deasserted,
The MCU 90 asserts BRDY # to complete the memory access. The DRAM page remains open until another master device issues a memory request for a different page or a refresh request occurs.

Referring now to FIG. 6, an accelerated memory write cycle for the same DRAM page is shown. After all, the DRAM page is opened in the initial state,
Indicates the previous visit to the page. The PCI bridge then asserts the ADS # control signal, asserts the W / R signal to indicate a write cycle, and asserts the MEMWAIT line to indicate that the PCI master is not yet ready to send data. . According to the preferred embodiment, while the MEMWAIT line is asserted, the PC
The I-bridge drives the address of the write cycle into the MCU. However, the state of the RAS line does not change because the appropriate page is already open. MEMWAIT
When the signal is deasserted by the PCI bridge, M
The CU completes the write cycle by asserting BRDY # and asserting the appropriate CAS line (CAS (2)). A subsequent read cycle without the MEMWAIT signal is shown in FIG.

Referring now to FIG. 7, an accelerated / decelerated memory read cycle for different DRAM banks is shown. In the initial state, the DRAM page of bank 3 is RAS
It has been opened from the previous memory access as indicated by the assertion of (3). The PCI bridge then asserts the ADS # control signal while holding the R / W line low to indicate a read cycle. P at substantially the same time
The CI bridge asserts the MEMWAIT signal to
Indicates that the CI master device is not yet ready to receive data. According to the preferred embodiment, the PCI bridge drives the address through the local bus, where M
Received by CU. The MCU decodes the address and changes from DRAM bank 3 to DRAM bank 2 and R
The row address strobe line RAS (2) is driven low while driving AS (3) high to drive the decoded row address to bank 2. The MCU then opens the appropriate DRAM page in bank 2 and sends the desired data through the memory bus by asserting the four CAS lines and then drives it to the local bus. MEM
The MCU waits for BRDY when the WAIT signal is deasserted to indicate that the PCI master is ready to receive data.
Asserts the # signal to indicate that a read cycle has been performed.

Therefore, if the address is for a DRAM bank having a different address, the MCU uses MEMWAIT.
Current DRA of the current bank while is asserted
Close M page and open DRAM page in new bank immediately (R because different DRAM banks are accessed
Because there is no AS precharge cycle time). M
The MCU slows down the memory bus by looping through a wait cycle until EMWAIT is deasserted or a refresh request is issued. After MEMWAIT is deasserted, MCU
Asserts BRDY # to complete the memory access. The DRAM page remains open until a subsequent memory access to another page by the master, or until a refresh request is received. In this sequence, the time (t
_RAC ) is saved by opening the page prior to accessing the data.

FIG. 8 shows an accelerated / decelerated memory read cycle to another page in memory. The first two states are MEM
A write cycle before a read cycle without WAIT is shown.
The PCI bridge then uses W /
With the R line held low, assert the ADS # control signal and MEMWAIT at the same time. M
While EMWAIT is asserted, the PCI bridge drives the address onto the MCU via the local bus.
The MCU decodes the address and opens the appropriate page in memory. When the page is opened, the MCU asserts the CAS line to drive the data to the memory bus and then to the local bus. When MEMWAIT is deasserted, the MCU asserts BRDY # to indicate that the read cycle is complete.

Therefore, if the address is in another DRAM page, the MCU closes the current DRAM page with MEMWAIT asserted and proceeds to the precharge state. When RAS precharge is completed, MCU90
Opens the DRAM page and slows down memory bus 150 by looping through a wait cycle until MEMWAIT is deasserted or a refresh request is issued. After MEMWAIT is deasserted, the MCU asserts BRDY # and C
The memory access is completed by asserting AS, allowing the particular byte of the DRAM page to be accessed. After the data transfer is complete, the DRAM page remains open until a refresh request is received or another master device issues a memory request to another page. This sequence saves the RAS precharge cycle time (t _RP ) and the time required to access the DRAM page (t
_RAC ) is saved.

Finally, FIG. 9 shows an acceleration / deceleration memory read cycle in which a refresh cycle is interposed. The initial state of FIG. 9 is a write cycle. Then the PCI bridge is ADS #
Assert the control signal, drive the W / R signal low, and at the same time assert MEMWAIT to indicate that the PCI master is not yet ready to receive data. PCI
The bridge drives an address on the local bus, where it is received by the MCU and used to access the desired page in memory. The MCU then asserts the appropriate column address strobe line CAS (2) to drive the data onto the memory bus. However,
A refresh request is received by the MCU while MEMWAIT is still asserted. MEM
With WAIT still asserted, the MCU performs a refresh cycle for bank 0 by asserting CAS before RAS for that bank. After the refresh is completed, the MCU returns to RAS
Reopen the appropriate page in memory by asserting (1) and drive the data by asserting CAS (2).

Various variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. The appended claims should be construed to cover all such variations and modifications.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a prior art computer system supporting a PCI master device.

FIG. 2 is a functional block diagram of a computer system configured according to the preferred embodiment.

FIG. 3 is a timing diagram of a typical read cycle.

FIG. 4 is a timing diagram of a typical write cycle.

5 is a timing diagram illustrating operation of the system shown in FIG.

FIG. 6 is a timing diagram illustrating operation of the system shown in FIG.

FIG. 7 is a timing diagram illustrating operation of the system shown in FIG.

FIG. 8 is a timing diagram illustrating operation of the system shown in FIG.

FIG. 9 is a timing diagram illustrating operation of the system shown in FIG.

[Explanation of symbols]

 50 integrated processor 60 CPU 65 CPU local bus 70 on-chip peripheral device 80 PCI bridge 100 PCI bus

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Victor F. Andrade United States, 78732 Texas, Austin, Van Helf Court, 12400 (72) Inventor Kelly M. Houghton United States, 78749 Texas, Austin, Salida Drive, 10317

Claims (31)

[Claims] 1. A method for optimizing the transfer of data between a system memory and a PCI master device, wherein the PCI master is connected to a PCI bridge via a PCI bus, the PCI bridge being a CPU local bus. Above, the system memory connects to a memory controller via a memory bus, said memory controller also on a local bus, said method comprising: (a) claiming ownership of the PCI bus by a PCI master; (b) driving an address signal on a PCI bus by a PCI master; (c) generating an address strobe signal on a local bus by a PCI bridge and driving the address signal via the local bus; ) A wait signal is generated by the PCI bridge,
Indicating that the PCI master cannot immediately complete the data phase of the transaction, (e) decoding the address signal by the memory controller, and (f) opening the appropriate page in system memory by the memory controller. The steps of: (g) deasserting a wait signal in response to an indication that the PCI master is ready to complete the data phase; and (h) completing the data transaction by the memory controller. Method. 2. The step of opening the appropriate memory page (step (f)) comprises: (f) (1) applying a row address signal to system memory; and (f) (2) an appropriate row address strobe ( RAS)
Asserting the line to enable the row address signal. 3. Steps (f) (1) and (f)
The method of claim 2, wherein (2) is completed while the wait signal is asserted. 4. The memory controller also provides a column address and asserts the appropriate column address strobe signal to drive data from the memory during a read cycle while the wait signal is still asserted. The method described in. 5. The method of claim 1, wherein the refresh cycle is performed while the wait signal is asserted. 6. The step of completing a data transaction (step (h)) includes: (h) (1) the appropriate column address strobe (CAS).
The method of claim 1, comprising providing a column address signal to the memory while asserting a signal; and (h) (2) asserting BRDY # to the PCI bridge. 7. The PCI bridge responds to a BRDY # from the memory controller to a PCI master by issuing a T
7. The method of claim 6, wherein RDY # is asserted. 8. The PCI bridge asserts a MEMWAIT signal if the PCI master does not assert IRDY # in response to a TRDY # signal.
The method described in. 9. A method for optimizing transfer of data between a PCI master device and system memory during a write cycle, wherein the PCI master is a PCI bus over a PCI bus.
Connecting to the bridge, the PCI bridge is on the CPU local bus, the system memory is connected to the memory controller via the memory bus, the memory controller is also on the local bus, the method is: (a) owning the PCI bus (B) the PCI master sends a burst cycle over the PCI bus, and (c) the PCI bridge sends a first address signal and a first data signal from the burst cycle. Receiving and taking ownership of the local bus; (d) the PCI bridge sending the first address signal and the first data signal over the local bus; and (e) the memory controller. Is a memory in which the first data signal corresponds to a first address signal And writing a memory ready signal to the PCI bridge, and (f) the PCI bridge issuing a target ready signal to the PCI master in response to the ready signal from the memory controller. And (g) the PCI bridge issuing a wait signal to the memory controller and providing a second address signal to the memory controller in the absence of an initiator ready signal from the PCI master. 10. The method of claim 9, wherein the memory controller generates a MEMHIT signal in response to step (d) when the first address signal is in system memory. 11. (h) The memory controller decodes the second address signal to generate a row address and a column address, and (i) the memory controller outputs the row address of the second address signal. Sending to the memory and asserting a row address strobe (RAS) signal to the memory to open the appropriate page in the memory.
The method according to claim 9. 12. Deasserting a wait signal in response to an initiator ready signal from the PCI master indicating that the PCI master has driven a second data signal over the PCI bus; and (k) the memory. A controller drives the column address of the second address signal into the memory and asserts an appropriate column address strobe (CAS) signal into the memory to cause the second data signal to be written into the memory. The step of enabling further comprising:
The method described in. 13. While the wait signal is asserted,
The method of claim 9, wherein a refresh cycle is performed on the bank of memory. 14. The method of claim 13, wherein the refresh cycle is performed on the same bank of memory in which the page is open. 15. The page is different than open,
14. The method of claim 13, wherein the refresh cycle is performed on a bank of memory. 16. The refresh cycle is pre-RAS CA.
14. The method of claim 13, comprising an S sequence. 17. The method of claim 13, wherein each bank of memory is refreshed independently. 18. A method for optimizing the transfer of data between a PCI master device and system memory during a read cycle, wherein the PCI master is a PCI bus via a PCI bus.
Connected to an I-bridge, the PCI bridge is on the CPU local bus, the system memory is connected to the memory controller via the memory bus, the memory controller is also on the local bus, and the method comprises: (a) a PCI master Taking ownership of the PCI bus; (b) sending a first address in memory by the PCI master to be read over the PCI bus; (c) the PCI bridge sending the first address signal. Receiving the local bus and taking ownership of the local bus; (d) the PCI bridge sending the first address signal over the local bus; (e) the memory controller having the first address. Receiving a signal and reading a first data signal in the memory corresponding to a first address signal; Sending a first data signal via the local bus and issuing a memory ready signal to the PCI bridge; (f) the PCI bridge in response to the ready signal from the memory controller, Issuing a target ready signal to the master, and (g) in the absence of an initiator ready signal from the PCI master, the PCI bridge issues a wait signal to the memory controller and a second address signal to the memory controller. A step of providing. 19. The method of claim 18, wherein the memory controller generates a MEMHIT signal in response to step (d) when the first address signal is located in system memory. 20. (h) The memory controller decodes a second address signal to generate a row address and a column address, and (i) the memory controller outputs the row address of the second address signal. Drive to a memory and assert a row address strobe (RAS) signal to the memory,
19. The method of claim 18, further comprising opening the appropriate page in memory. 21. (j) The memory controller drives a column address of the second address signal to the memory and asserts a column address strobe (CAS) to the memory to correspond to the second address. 21. The method of claim 20, further comprising driving a second data signal onto the local bus. 22. (k) Deasserting a wait signal in response to an initiator ready signal from the PCI master indicating that the PCI master is ready to receive the first data signal; (l) 22. The method of claim 21, further comprising: the memory controller issuing a memory ready signal; and (m) the PCI bridge asserting a target ready signal to the PCI master and initiating another read cycle. . 23. The method of claim 18, wherein a refresh cycle is performed on the bank of memory while a wait signal is asserted. 24. A system for optimizing memory access time in a computer, the system memory for storing and accessing data, and controlling access to the memory connected to the system memory. A memory controller unit, a PCI bridge connected to the memory controller unit via a local bus, and a peripheral PCI master device connected to the PCI bridge via a PCI bus, wherein the PCI master device is a system memory. Can claim ownership of the PCI bus to complete a data transaction to
The PCI bridge claims ownership of the local bus when the PCI master claims ownership of the PCI bus,
The memory controller further includes a CPU core connected to the local bus, wherein the PCI bridge asserts a wait signal to the memory controller, substantially simultaneously with delaying the completion of the data transfer by the PCI master device. The system drives the address in memory for the next data transaction over the local bus. 25. While the wait signal is asserted,
25. The system of claim 24, wherein the memory controller opens the appropriate page in memory. 26. The system of claim 25, wherein the system memory comprises up to four distinct banks of DRAM chips. 27. The system of claim 25, further comprising a system timer that issues a refresh request about every 15.625 / 4 microseconds. 28. The refresh cycle is about 15.62.
28. Generated in each bank every 5 microseconds.
The system described in. 29. The system of claim 28, wherein the refresh cycle is staggered in four banks. 30. The system of claim 24, wherein the PCI bridge asserts the wait signal in a read cycle if the PCI master does not issue a ready signal when data is sent over the PCI bus. 31. After the PCI bridge issues a ready signal, if the PCI master does not issue a ready signal with a frame cycle signal still asserted,
25. The system of claim 24, wherein the PCI bridge asserts the wait signal.