JPH0955730A - Data transmitting method, data recording device, data recording medium, and data reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it difficult to decipher a code making it easy to handle key information by performing a ciphering processing by using 1st key information and performing a ciphering processing by using 2nd key information obtained from the information through data conversion. SOLUTION: Input digital data supplied to an input terminal 1 is sent to an output terminal 4 through signal processing circuits 2 and 3. The 1st key information KE1 from a key information supply part 5 is sent to a data converting circuit 6 and converted into the 2nd key information KE2 . Further, one of the 1st and 2nd pieces KE1 and KE2 of key information are sent to a 1st signal processing circuit 2 and the other is sent to a 2nd signal processing circuit 3. Then the respective signal processing circuits 2 and 3 performs data conversion corresponding to the pieces KE1 and KE2 of key information for ciphering what are supplied for input and other signal processings are performed when necessary before output. Further, a signal led out of an output terminal 4 is recorded on and reproduced from a recording medium and sent and received through a communication medium.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission method, a data recording device, a data recording medium, and a data reproduction applicable to a copy system for digital data transmitted or recorded / reproduced, prevention of illegal use, or a billing system. Regarding the device.

[0002]

2. Description of the Related Art In recent years, with the increase in capacity and spread of digital recording media such as optical disks, prevention of illegal copying and prevention of illegal use have become important. That is, in the case of digital audio data or digital video data, a copy without deterioration can be easily generated by copying or dubbing, and in the case of computer data, the same data as the original data can be easily copied. Therefore, the actual situation is that the harmful effects of illegal copying have already occurred.

In order to avoid illegal copying of digital audio data and digital video data, for example, so-called SCMS (serial copy management system) and CGMS (copy generation management system) standards are known, which are recorded. Since a copy prohibition flag is set on a specific part of the data, there is a problem that the data is extracted by a method such as so-called dump copy.

In addition, file contents themselves such as computer data are encrypted and licensed to only authorized users. As a form of information distribution, this is to distribute a digital recording medium in which information is encrypted and recorded, or to make an encrypted digital signal easily available through a wired or wireless transmission path. It is connected to a system that allows users to pay key information about what they need, decrypt the code, and use it, but it is desirable to establish a simple and useful encryption method. There is.

[0005]

By the way, various methods have been proposed as encryption methods, and public-key encryption methods in which an encryption key is made public are also known.

However, except for the above public key encryption,
Key management is difficult, and public key cryptography has the problem of complicated processing.

Further, in public-key cryptography, since the key is open to the public, there is a risk that it will be broken in a network society by parallel decryption using many computers. This is the current situation.

The present invention has been made in view of the above-mentioned circumstances, and is a data transmission method, a data recording device, and a data recording medium that enable encryption with a simple structure and make decryption difficult. , And a data reproducing device.

[0009]

In order to solve the above-mentioned problems, the present invention uses the first key information to encrypt data when the input digital data is encrypted and transmitted. And a step of performing an encryption process on the data using the second key information obtained by converting the first key information into data.

In this case, it is preferable that the first key information and the second key information are used for encryption at different places, or switched and used. It is also possible to perform transmission such as recording only the first key information, only the second key information, or both of the key information.

Data can be encrypted more than twice with a single key information, and the first key information and the second key information are encrypted at different locations or timings to handle the key information. Makes it difficult to decipher while simplifying.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of the embodiment of the present invention. In FIG. 1, the input terminal 1
The input digital data supplied to is sent to the output terminal 4 via the signal processing circuits 2 and 3. The first key information K _E1 from the key information supply unit 5 is sent to the data conversion circuit 6 to be converted into the second key information K _E2 . One of the first and second key information K _E1 and K _E2 is sent to the first signal processing circuit 2 and the other is sent to the second signal processing circuit 3. In the example of FIG. 1, the first key information K _E1 from the key information supply unit 5 is sent to the signal processing circuit 2, and the second key information K _E2 from the data conversion circuit 6 is sent to the signal processing circuit 3. However, as indicated by a broken line in the figure, the first key information K _E1 is _supplied to the signal processing circuit 3 and the second key information K _E2 is _supplied to the signal processing circuit 2.
It may be sent to each. These signal processing circuits 2 and 3 perform data conversion according to the encryption key information K _E1 and K _E2 supplied to the input, and perform other signal processing as necessary and output. The signal extracted from the output terminal 4 is transmitted by being recorded / reproduced on / from a recording medium or transmitted / received via a communication medium.

The transmitted signal is supplied to the input terminal 7 on the reproducing side or the receiving side, and is sent to the output terminal 10 via the signal processing circuits 8 and 9. In the signal processing circuit 8, the reverse processing or decoding processing corresponding to the signal processing circuit 3 on the recording side or the transmission side is performed, and the decryption of the encryption corresponding to the second key information K _E2 from the data conversion circuit 6 is performed. The chemical treatment is applied. Further, the signal processing circuit 9 performs reverse processing or decoding processing corresponding to the signal processing circuit 2,
A decryption process for encryption according to the first key information K _E1 from the key information supply unit 5 is performed.

The data conversion in the data conversion circuit 6 may be an encryption process using another encryption key or a fixed value. For example, the above-mentioned first key information K _E1
Is set to 8 bits, and the second key information K _E2 can be obtained by performing multiplication with another 8-bit key or a fixed value. As a specific example, the 8-bit first key information K _E1
Is set to "01001100" and another 8-bit key or fixed value for data conversion is set to "10000111", these are multiplied to obtain "010011111100100" as the second key information K _E2. be able to. In addition,
8 bits may be converted into 8 bits by a logical operation or the like.

Here, in addition to transmitting both the first and second key information K _E1 and K _E2 as the key information, only the first key information K _E1 or the second key information K _{E2 is} transmitted. Only the information may be transmitted. That is, when only the first key information K _E1 is transmitted, the first key information K _E1 may be converted on the reproducing side to obtain the second key information K _E2 . If the data conversion can be decrypted or inversely converted, only the second key information K _E2 is transmitted and the reproducing side can decrypt or inversely convert the second key information K _E2. That is, the reverse processing of the conversion processing in the data conversion circuit 6 is performed to restore the first key information K _E1 .

As described above, it is possible to doubly encrypt data with a single key information. Also, the first key information K _E1
Since the second key information K _E2 and the second key information K _E2 are encrypted at different places, it is difficult to decrypt.

Further, the first key information K _E1 and the second key information K
_E2 may be switched and used for encryption, and in this case as well, decryption of the encryption can be made difficult.

Next, FIG. 2 is a block diagram showing a concrete example of a data recording apparatus to which the embodiment of the present invention is applied. In FIG. 2, the input terminal 11 is supplied with digital data such as data obtained by digitally converting an analog audio signal or video signal and computer data. This input digital data is sent to the sectorizing circuit 13 via the interface circuit 12, and is sectorized in a unit of a predetermined data amount, for example, a unit of 2048 bytes. The sectorized data is sent to the scramble processing circuit 14 and subjected to scramble processing. The purpose of the scramble process in this case is to randomize the input data so that the same byte pattern does not appear consecutively, that is, to remove the same pattern, and to read and write the signal appropriately. It is a randomization process. The data that has been scrambled or randomized is sent to the header addition circuit 15, and after the header data placed at the beginning of each sector is added, it is sent to the error correction coding circuit 16. The error correction coding circuit 16 performs data delay and parity calculation and adds parity. In the next modulation circuit 17, for example, 8-bit data is converted into 16-channel bit modulation data according to a predetermined modulation method, and the modulated data is sent to the synchronization adding circuit 18. The synchronization adding circuit 18 adds a synchronization signal of a so-called out-of-rule pattern, which breaks the modulation rule of the above-mentioned predetermined modulation method, in a predetermined data amount unit and sends it to the recording head 20 via a drive circuit, that is, a driver 19. There is. The recording head 20 performs, for example, optical or magneto-optical recording, and records the modulated recording signal on a disk-shaped recording medium 21. The disc-shaped recording medium 21 is rotationally driven by a spindle motor 22.

The scramble processing circuit 14 is
The header adding circuit 15 may be inserted after the header adding circuit 15 to perform scramble processing on the header added digital data and send the scrambled digital data to the error correction coding circuit 16.

Here, at least one of the sectorizing circuit 13, the scramble processing circuit 14, the header adding circuit 15, the error correction coding circuit 16, the modulating circuit 17, and the synchronization adding circuit 18 is connected to the input. The configuration is such that encryption processing is performed and output is performed. Preferably,
The encryption processing may be performed by two or more circuits.
The key information for this encryption processing is identification information written in an area other than the data recording area of the recording medium 21, for example, medium-specific identification information, manufacturer identification information, vendor identification information, or a recording device or encoder. Unique identification information, unique identification information of a medium manufacturing apparatus such as a cutting machine or a stamper, identification information supplied from the outside, and the like are used at least in part. As described above, the identification information written in the area other than the data recording area of the medium is, for example, the information sent from the interface circuit 12 to the terminal 24a via the TOC (Table of contents) generation circuit 23, or directly from the interface circuit 12. Terminal 24b
Information sent to. The identification information from these terminals 24a and 24b is sent to the key information supply circuit 25, the first key information K _E1 is taken out, and this first key information K _E1 is sent to the data conversion circuit 26 and the data is sent. The second key information K _E2 is obtained by the conversion. These first, second key information K _E1, K _E2 is sent to different two or more circuits of the circuit 13-18, in each circuit, these key data K _E1, K
_The input data is encrypted using _E2 .

In this case, which of the circuits 13 to 18 has been subjected to the encryption process is also one of the options, and is considered to be a key necessary for obtaining a normal reproduction signal during reproduction. That is, for one key information, if the encryption processing is performed by one circuit, it is necessary to select one of the six options, and if the encryption processing is performed by two circuits, 30 It is necessary to choose one of these options. If two pieces of key information K _E1 and K _E2 are used, and there is a possibility that encryption processing will be performed in any one of the six circuits 13 to 18, the choices will be further increased, and this combination will be used. Difficult to find by trial and error,
It fully plays the role of encryption.

The first key information K _E1 for encryption and the second key information K _E1 for encryption
The key information K _E2 may be switched at a predetermined timing, for example, a sector cycle. When the key information is switched at this predetermined timing, information such as whether or not the switching is performed, the switching cycle, and the switching order of a plurality of key information can also be used as a key, and the encryption level or the encryption difficulty level, The difficulty of solving and the difficulty of decoding can be further increased.

Next, the configuration of each of the circuits 13 to 18 and a concrete example of the encryption process will be described.

First, in the sectorizing circuit 13, for example, interleave processing of even / odd bytes as shown in FIG. 3 may be performed. That is, in FIG. 3, the output from the interface circuit 12 in FIG. 1 is sent to the 2-output changeover switch 31, and one output of the changeover switch 31 is sent to the sectorizer 34 via the even-odd interleaver 33. The other output of the changeover switch 31 is sent to the sectorizer 34 as it is. Sectorizer 3
In 4, the input data is grouped in units of 2048 bytes into one sector. The changeover operation of the changeover switch 32 of the sectorizing circuit 13 is controlled by a key 1-bit control signal. The even-odd interleaver 33
Even bytes 36a and odd bytes 3 as shown in FIG.
One sector of input data in which 6b and 6b are alternately arranged,
As shown in FIG. 4B, the data is distributed to the even-numbered data portion 37a and the odd-numbered data portion 37b and output. Further, as shown in FIG. 4C, a predetermined area 39 in one sector is specified by the key information, and only the data in this area 39 is distributed to the even data section 39a and the odd data section 39b. Good. In this case, it is possible to set a plurality of ways of specifying the area 39, and it is possible to further increase the choices of the key information and further raise the encryption level.

Next, for the scramble processing circuit 14, for example, as shown in FIG. 5, a so-called parallel block synchronous type scrambler using a 15-bit shift register can be used. To the data input terminal 35 of the scrambler, the data from the sectorizing circuit 13 is input in the order in which the LSB (least significant bit) comes first in time, so-called LSB first. The 15-bit shift register 41 for scrambling uses the exclusive OR (ExOR) circuit 42 to generate the generator polynomial x ¹⁵ + x + 1.
The preset value (or initial value) as shown in FIG. 6 is set in the 15-bit shift register 41, and the selection number of the preset value in FIG. For example, the preset value can be switched on a sector-by-sector basis in correspondence with the lower 4 bits of the sector address. The output data from the shift register 41 and the input data from the terminal 35 are exclusive ORed by the ExOR circuit 43,
It is taken out from the terminal 44 and sent to the header addition circuit 15 in FIG.

Here, the generator polynomial and the preset value (initial value) can be changed according to key information such as a predetermined identification number. That is, to change the generator polynomial, for example, the configuration shown in FIG. 7 may be used. In FIG. 7, the output from each bit of the 15-bit shift register 41 is the changeover switch 46.
Sent to each selected terminal of the ExOR circuit 4 and the changeover switch 46 is controlled by the control terminal 47, for example, by the control data of 4 bits.
2 has been sent. By changing the control data of the control terminal 47 having such a configuration, the generator polynomial x ¹⁵ + x
^{The n of n} + 1 can be changed. Further, in order to change the preset value, it is possible to perform a logical operation of each preset value in the preset value table of FIG. 6 with each byte value of the identification information of 16 bytes, for example. As the identification information in this case, the identification information unique to the medium, the manufacturer identification information, the vendor identification information, the identification information unique to the recording device or the encoder, the identification information unique to the medium manufacturing device, and the external identification information are supplied from the outside. Identification information or the like, or a combination thereof or a combination with other information can be used, and as the above logical operation, exclusive OR (ExOR), logical product (AND), logical OR (OR) , Shift operation, etc. can be used. The configuration for changing the generator polynomial is not limited to the structure of FIG. 7, and the number of stages of the shift register and the number of taps to be taken out may be arbitrarily changed.

Next, the header adding circuit 15 will be described. First, FIG. 8 shows a specific example of the sector format. One sector is a user data area 41 of 2048 bytes, a synchronization area 42 of 4 bytes, a header area 43 of 16 bytes, and an error of 4 bytes. Detection code (ED
C) area 44 is added. The error detection code of the error detection code area 44 is the user data area 41.
And a 32-bit C generated for the header area 43
Made of RC code. As the encryption processing in the header addition circuit 15, for the so-called data sync,
It may be applied to the address and CRC of the header.

As an example of performing the synchronization process of the sector, that is, the data sync, the byte pattern assigned to each byte of the 4-byte sync area 42 is represented by "A", "B", and "B" in FIG. When represented by “C” and “D” respectively, it is possible to shift or rotate the contents of 4 bytes in byte units by using 2-bit key information. That is, when the 2-bit key is “0”, “A
By switching to "BCDA" when "BCD", "1", "CDAB" when "2", and "DABC" when "3", the sector cannot be synchronized unless the keys match, and normal operation is achieved. Playback is not possible. The byte patterns “A” to “D” are, for example, ISO6.
For example, 46 character codes can be used.

In the header area 43, as shown in FIG. 8, a CRC 45 which is a so-called cyclic code, copy information 46 for permission / non-permission of copy and copy generation management,
Layer 47, which indicates which layer of the multi-layer disc, address 48,
Each area of the spare 49 is provided. Of these, the 32 bits of the address 48 are bit scrambled, and in this case, the transposition process is performed in bit units to enable encryption. Also, as the generator polynomial of CRC45, x ¹⁶
When + x ¹⁵ + x ² +1 is used, 12 bits corresponding to x ¹⁴ to x ³ may be changed according to the key instead of x ¹⁵ and x ² in the second and third terms. Also,
It is also possible to perform a logical operation of 16 bits of CRC45 and the key information.

Next, a concrete example of the error correction coding circuit 16 is shown in FIG. In FIG. 10, one frame for error correction coding consists of 148 bytes or 148 symbols of data, and the digital data from the header adding circuit 15 is collected every 148 bytes to form a first encoder C1. It is supplied to the encoder 52. In the C1 encoder 52, 8-byte P parity is added and sent to the C2 encoder 54 which is the second encoder via the delay circuit 53 for interleaving. In the C2 encoder 54, 14 bytes of Q parity is added.
The parity is fed back to the C1 encoder 52 via the delay circuit 55. P, Q from this C1 encoder 52
170 bytes including parity are taken out and output via the delay circuit 56 and the inverter group 57, as shown in FIG.
Is sent to the modulator circuit 17.

When encryption processing is performed in such an error correction coding circuit, for example, for each byte in the inverter group 57, selection is made as to whether the inverter is inserted or not, depending on the key information of the encryption. To be able to do so. That is, in the standard configuration, 22 bytes of P and Q parity are inverted and output by the inverters of the inverter group 57. However, some of these inverters are eliminated or some are added to the C1 data side. For example, inserting an inverter and inverting and outputting it. In this case, the error uncorrectability probability changes depending on the degree of difference from the reference configuration, and when the difference is small, the error occurrence probability in the final reproduction output is slightly high, whereas when there is a large difference, the error correction probability is generally high. The error correction is not performed, and the reproduction becomes almost impossible. That is, when looking at, for example, a C1 encoder, since the so-called distance, which is an index indicating the error correction capability, is 9, error detection and correction of up to 4 bytes can be performed, and correction of up to 8 bytes is possible if there is an erasure pointer. Therefore, if there are 5 or more differences, the C1 code cannot always correct. When there are four differences, it becomes a subtle state that the error cannot be corrected if an error occurs even with one byte. As the difference decreases to 3, 2, and 1, the probability of error correction increases. By using this, when providing audio or video software, it is possible to actively create a playback state in which it can be played to some extent but is not perfect, and sometimes it is disturbed, and the purpose is to inform only the outline of the software etc. Can be used for

In this case, a method of predefining, for example, about two places for changing the inverter, a method of randomly selecting a changing place according to the key information and limiting the minimum number to about two places, And a method of combining.

Further, the position where the inverter is inserted or changed is not limited to the position of the inverter group 57 shown in FIG. 10, and other positions such as the front stage and the rear stage of the C1 encoder 52, or these positions may be combined. Good.
Different keys may be used for multiple locations. Further, as the data conversion, in addition to using an inverter, bit addition or various logical operations may be used, data may be transposed according to encryption key information, or data may be encrypted as key information. You may make it replace according to.

FIG. 11 shows, as another specific example of the error correction coding circuit 16, an exclusive OR (ExOR) circuit group 61 at a position after the inverter group 57, that is, at the output side.
Is inserted, and the ExOR circuit group 66 is also inserted at the position before the C1 encoder 52, that is, at the position on the input side.

In FIG. 11, 170-bit key information is supplied to the terminal 62, which is a so-called D latch circuit 63.
Is supplied to each of the 170 ExOR circuits in the ExOR circuit group 61 via. In response to the 1-bit encryption control signal supplied to the enable terminal 64, the D-latch circuit 63 keeps the 170-bit key information from the terminal 62 as it is.
Send to ExOR circuit group 61 or all zero, ie 170
Switching control is performed to determine whether all bits are "0". ExOR
Of the 170 ExOR circuits in the circuit group 61, the ExOR circuit to which “0” is sent from the D latch circuit 63 is the inverter group 5
The data from 7 is output as it is, and the ExOR circuit to which “1” is sent from the D latch circuit 63 converts the data from the inverter group 57 and outputs. When all zero,
The data from the inverter group 57 is output as it is. The ExOR circuit group 66 has 148
The ExOR circuit group 61 is the same as the above ExOR circuit group 61 except that it has an ExOR circuit and the key information is 148 bits.
The 148-bit key information supplied to the D latch circuit 68
Are sent to the 148 ExOR circuits in the ExOR circuit group 66 respectively, and the D-latch circuit 68 is switch-controlled by the encryption control signal of the enable terminal 69 between the 148-bit key information and all zeros.

Also in the circuit of FIG. 11, the circuit shown in FIG.
Of course, it is possible to obtain the same effect as the above case.
Further, it is possible to use only one of the ExOR circuit groups 61 and 66, or to use either one or both of them as an encryption key.

In place of the ExOR circuit groups 61 and 66 as the data conversion means, AND, OR, NAND,
You may use NOR, an inversion circuit group, etc. Also,
In addition to performing a logical operation with 1-bit key information or key data in 8-bit units, logical operation may be performed with 8-bit key data on 8-bit information data,
Further, AND, OR, ExOR, are respectively applied to respective bits of 8 bits corresponding to 1 word of information data.
A NAND, NOR, and invert circuit may be used in combination. In this case, for example, for 148 bytes, that is, for 148 × 8 bit data, 148 × 8 bit key data is used, and AND,
When OR, ExOR, NAND, NOR, and invert circuits are used in combination, these combinations themselves can also be used as a key. In addition to the logical operation, transposition for changing the position of data, substitution for replacing the value of data, etc. can be used as the data conversion.

As described above, the intermediate data and the like handled in the error correction coding are subjected to data conversion by the inverter or the like for a part of the data corresponding to the key information of the encryption so that an uncorrectable error is generated. The probability of occurrence changes, and the encryption level, depth, difficulty of decryption, etc. will change according to the number of data to be converted. In other words, the depth and difficulty of encryption required according to the purpose can be set arbitrarily by the number of data to be converted, and if you want to provide a summary as a sample or make it unreproducible to non-authorized users only. Various measures can be taken depending on the case, the security level request, and the like.

Next, the encryption processing in the modulation circuit 17 of FIG. 2 will be described with reference to FIG. This FIG.
, The data from the error correction coding circuit 16 is supplied to the input terminal 71 every 8 bits (1 byte), and the input terminal 72 is supplied with 8-bit key information. The data is sent to an ExOR circuit 73, which is an example of a logical operation circuit, and an exclusive OR is taken. The 8-bit output from the ExOR circuit 73 is sent to a modulator of a predetermined modulation method, for example, an 8-16 conversion circuit 74, and converted into 16 channel bits. This 8-16
As an example of the 8-16 modulation system in the conversion circuit 74, there is a so-called EFM plus modulation system.

In the example of FIG. 12, 8 times before data modulation.
Although the encryption processing is performed using the bit key information, the number of bits of the key information is not limited to 8 bits, and 8-1
It is also possible to change the input / output correspondence of the conversion table in the 6-modulation according to the key information. It goes without saying that the above-mentioned identification information unique to the medium can be used as the key information.

Next, the synchronization adding circuit 18 will be described. The synchronization adding circuit 18 uses, for example, four types of synchronization words S0 to S3 as shown in FIG.
It is synchronized in units of modulation frames. This 8-16
A modulation frame (for example, EFM plus frame) is composed of, for example, 1360 channel bits which is 85 data symbols, and a sync word of 32 channel bits is added to each 1360 channel bits of this frame, and this frame is added with the C1 code or C2. The four types of synchronization words S0 to S3 described above are selectively used by structuring in accordance with the code and making the synchronization word of the first frame of the C1 code sequence different from the synchronization word of the other frame. These synchronization words S0 to S3 are "1" of the immediately preceding word,
It has two synchronization patterns a and b depending on the state of "0", the so-called digital sum, or the DC value.

Such four types of synchronization words S0 to S3
Is selected by using, for example, a circuit as shown in FIG.
Encryption can be performed by changing the bit key information 75. That is, the four types of synchronization words S0 to S0
Each bit of the 2-bit data 76 designating S3 and each bit of the 2-bit key information 75 are respectively exclusive-ORed by the two ExOR circuits 77 and 78 to become new synchronization word designation data 79. . As a result, the usage of the sync word in the frame structure or the use position of various sync words in the frame structure is changed, and encryption is performed.

The number of types of sync words may be further increased, and the method of taking out four types of sync words from among them may be determined by the encryption key. As the key information, the above-described identification information unique to the medium can be used.

The key information used in each of these circuits 13 to 18 is either the above-mentioned first key information K _E1 or second key information K _E2 . These two key information K _E1 ,
K _E2 is used in different places. For example, the first key information K _E1 is used for encryption in any of the circuits 13 to 18, and at least one of the circuits that is not encrypted using the first key information K _E1 The encryption may be performed using the key information K _E2 of ₂ .

Next, FIG. 15 shows a disc-shaped recording medium 101 such as an optical disc as an example of the recording medium.
This disc-shaped recording medium 101 has a center hole 10 at the center.
2 which is a program management area from the inner circumference to the outer circumference of the disc-shaped recording medium 101.
(Table of contents) area that is a lead-in (leadin
) Area 103, program area 104 in which program data is recorded, and program end area, so-called lead-out area 105 are formed. In the optical disc for reproducing an audio signal or a video signal, audio or video data is recorded in the program area 104, and time information of the audio or video data is managed in the lead-in area 103.

As a part of the key information, it is possible to use the identification information written in the area other than the program area 104 which is the data recording area. Specifically, T
In the lead-in area 103 and the lead-out area 105, which are OC areas, identification information, for example, identification information such as a production number unique to the medium, manufacturer identification information, vendor identification information, or identification information unique to the recording device or encoder is displayed. , The unique identification information of the medium manufacturing apparatus such as the cutting machine or the stamper is written, and the encryption processing is performed by at least one of the six circuits 13 to 18 described above as the first key information K _E1. Then, the second key information K _E2 obtained by data-converting the first key information K _E1 is used to perform the encryption process in at least one of the remaining circuits, and the encryption process is performed. The obtained signal is recorded in the program area 104 which is a data recording area. At the time of reproduction, the identification information is used as the first information for decrypting the encryption.
It may be used as the key information K _E1 of Alternatively, the identification information may be physically or chemically written inside the lead-in area 103, and this may be read at the time of reproduction and used as key information for decrypting the code. Further, only the second key information K _E2 is recorded at a predetermined position on the disc-shaped recording medium 101,
On the reproducing side, the second key information K _E2 may be decrypted to obtain the first key information K _E1 .

Next, an embodiment of the data reproducing method and the data reproducing apparatus of the present invention will be described with reference to FIG.

In FIG. 16, a disk-shaped recording medium 101 as an example of the recording medium is a spindle motor 108.
The recording medium is read by the reproducing head device 109 such as an optical pickup device.

The digital signal read by the reproducing head device 109 is the TOC decoder 111 and the amplifier 1.
12 is sent. From the TOC decoder 111, the TOC is transferred to the lead-in area 103 of the disc-shaped recording medium 101.
The identification information recorded as a part of the C information, for example, identification information such as a manufacturing number unique to the medium, manufacturer identification information, vendor identification information, or identification information unique to a recording device or an encoder, a cutting machine or a stamper, etc. The unique identification information of the medium manufacturing apparatus is read, and this identification information is used as at least a part of the key information for decrypting the code. In addition, from the CPU 122 inside the playback device,
The identification information unique to the playback device or the identification information from the outside may be output and this identification information may be used as at least a part of the key information. Note that the identification information from the outside includes identification information received through a communication line or a transmission path, or identification information obtained by reading a so-called IC card, ROM card, magnetic card, optical card, or the like. To be

As a specific example of this key information, in the example of FIG. 16, the output from the TOC decoder 111 and the output from the CPU 122 are sent to the key information supply circuit 125, and the key information supply circuit 125 outputs the first key. The second key information K _E2 is obtained by obtaining the information K _E1 and sending it to the data conversion circuit 126 for data conversion. These first and second key information K _E1 and K _E2 are respectively encrypted with respect to the circuits 114 to 119 corresponding to the encrypted circuits among the circuits 13 to 18 on the recording side in FIG. The information corresponding to the key information used for the encryption is used.

In FIG. 16, the reproducing head device 10 is used.
The digital signal taken out of the amplifier 9 via the amplifier 112 and the PLL (phase locked loop) circuit 113 is sent to the sync separation circuit 114 to separate the sync signal added by the sync addition circuit 18 in FIG. Is done. The digital signal from the sync separation circuit 114 is the demodulation circuit 1
The signal is sent to 15, and the process of demodulating the modulation of the modulation circuit 17 of FIG. 2 is performed. Specifically, it is a process of converting 16 channel bits into 8-bit data. The digital data from the demodulation circuit 115 is sent to the error correction decoding circuit 116 and the error correction coding circuit 1 of FIG.
A decoding process as a reverse process of the encoding in 6 is performed.
Hereinafter, the sector decomposition circuit 117 decomposes the data into sectors,
The header separation circuit 118 separates the header at the beginning of each sector. The sector disassembling circuit 117 and the header separating circuit 118 correspond to the sectorizing circuit 13 and the header adding circuit 15 shown in FIG. Next, the descramble processing circuit 119 performs descramble processing as the reverse processing of the scramble processing in the scramble processing circuit 14 of FIG. 2, and the reproduced data is taken out from the output terminal 121 via the interface circuit 120.

Here, as described above, at the time of recording, the sectorizing circuit 13 and the scramble processing circuit 1 shown in FIG.
4, at least one of the header addition circuit 15, the error correction coding circuit 16, the modulation circuit 17, and the synchronization addition circuit 18 has been subjected to encryption processing using the first key information K _E1 . The reproduction side circuits 114 to 119 corresponding to the circuits subjected to the encryption process need to perform the process of decrypting the code using the first key information K _E1 .
Further, at least one of the remaining circuits is subjected to encryption processing using the second key information K _E2 , and a circuit on the reproduction side corresponding to the circuit subjected to this encryption processing. Therefore, a process of decrypting the cipher using the second key information K _E2 is required. That is, the first key information K _E1 or the second key information K _{E2 in} the sectorizing circuit 13 of FIG.
When the encryption process using any of the above is performed, the decryption process of the cipher using the key information at the time of encryption is required in the sector decomposition circuit 117. Similarly, the encryption / decryption processing in the descramble processing circuit 119 corresponds to the encryption processing in the scramble processing circuit 14 in FIG. 1, and the header corresponding to the encryption processing in the header adding circuit 15 in FIG. The encryption / decryption processing in the separation circuit 118 corresponds to the encryption processing in the error correction encoding circuit 16 in FIG. 1, and the encryption / decryption processing in the error correction decoding circuit 116 is performed in the modulation circuit 17 in FIG. The encryption / decryption process in the demodulation circuit 115 corresponds to the encryption process in FIG. 1, and the encryption / decryption process in the sync separation circuit 114 corresponds to the encryption process in the synchronization adding circuit 18 in FIG. It is necessary to use the same key information as the key information used at the time of conversion.

The sector decomposing circuit 117 shown in FIG. 16 may be provided in the subsequent stage of the descramble processing circuit 119.

As described with reference to FIGS. 13 and 14, the encryption / decryption processing in the sync separation circuit 114 uses a plurality of types of sync words, for example, four types of sync words or positions of use of various sync words in the frame structure. Is changed according to the key information, and the encrypted information is detected according to the key information.

Next, as shown in FIG. 17, the encryption / decryption processing in the demodulation circuit 115 is performed by the sync separation circuits 114 to 16 as shown in FIG.
12 is sent to the -8 conversion circuit 131 and the 16 channel bits are converted into 8-bit data.
Send to the ExOR circuit 132 corresponding to the circuit 73, and the terminal 133
By taking the exclusive OR with the 8-bit key information from, the data corresponding to the 8-bit data supplied to the input terminal 71 of FIG. 12 is restored, and this is sent to the error correction decoding circuit 116.

Next, in the error correction decoding circuit 116, for example, the reverse process of the error correction coding process of FIG.
It is performed by the structure of 8.

In FIG. 18, the demodulation circuit 115 is used.
The 170 bytes or 170 symbols of the data demodulated in 1 are sent to the C1 decoder 144, which is the first decoder, via the inverter group 142 and the delay circuit 143. This C1 decoder 144
22 bytes out of the 170-byte data supplied to P.Q. are P and Q parity, and the C1 decoder 144 performs error correction decoding using these parity data. 170 bytes of data is output from the C1 decoder 144, is sent to the C2 decoder 146 that is the second decoder via the delay circuit 145, and is subjected to error correction decoding using parity data. Furthermore, the delay circuit 14
7 to the C3 decoder 148 which is the third decoder. Here, the delay circuit 147 and the C3 decoder 14
8 is the same as the delay circuit 143 and the C1 decoder 144, and a plurality of sets of the delay circuit and the C1 decoder may be provided. This C3 decoder 148
The final error-correction decoding is performed with 1 without parity.
48 bytes of data are retrieved. This 148-byte data corresponds to the 148-byte data input to the C1 encoder 52 shown in FIG.

If the inverter group 57 of the error correction coding circuit of FIG. 10 is encrypted by the presence or absence of an inverter, the inverter group 142 of the error correction decoding circuit of FIG. It is necessary to perform encryption / decryption. In addition to the above, it is needless to say that the encryption / decryption, which is the reverse process for deciphering the encryption, is required corresponding to the various encryption processes described with reference to FIG.

Here, FIG. 19 is a diagram showing a specific configuration of an error correction decoding circuit corresponding to the specific configuration of the error correction encoding circuit of FIG.

In FIG. 19, the ExOR circuit group 151 is provided at the input side of the inverter group 143 corresponding to the ExOR circuit group 61 inserted at the output side of the inverter group 57 of FIG.
Corresponding to the ExOR circuit group 66 inserted on the input side of the C1 encoder 52 in FIG.
An ExOR circuit group 156 is inserted on the output side of 8.

The key information of 170 bits corresponding to the key information supplied to the terminal 62 of FIG. 11 is supplied to the terminal 152 of FIG. 19, and the so-called D latch circuit 153 is used.
It is supplied to each of the 170 ExOR circuits in the ExOR circuit group 151. In response to the 1-bit encryption control signal supplied to the enable terminal 154, the D-latch circuit 153 keeps the 170-bit key information from the terminal 152 as it is.
Send to ExOR circuit group 151 or all zero, ie, 17
Switching control is performed to determine whether all 0 bits are "0". The ExOR circuit group 156 is the same as the ExOR circuit group 151 except that it has 148 ExOR circuits and the key information is 148 bits similar to the key information supplied to the terminal 67 in FIG. Is the same as the above, and the 148-bit key information supplied to the terminal 157 is passed through the D latch circuit 158 to Ex.
It is sent to each of the 148 ExOR circuits in the OR circuit group 156, and the D latch circuit 158 is connected to the enable terminal 15
The encryption control signal 9 controls switching of 148 bits of key information or all zeros.

Next, in the sector decomposition circuit 117,
As described with reference to FIGS. 3 and 4, when the sectoring circuit 13 performs encryption by the interleave of the even / odd bytes at the time of recording, the reverse processing for solving the even-odd interleave, that is, the so-called de-interleaving. Interleave processing is performed.

In the header separation circuit 118,
At the time of recording, when the header adding circuit 15 performs the encryption processing as described with reference to FIG. 8 and FIG. 9, that is, the transposition of the byte pattern of the data sync for the sector synchronization and the change of the address and the CRC are performed. The encryption / decryption processing is performed to restore this.

Next, in the descramble processing circuit 119, encryption / decryption processing is performed to restore the encryption processing described with reference to FIGS.

As described above, the information indicating which of these circuits 114 to 119 requires the encryption / decryption process also becomes the encryption key information. Further, the encryption key information can be switched at a predetermined cycle, for example, the sector cycle, and the degree of difficulty of encryption can be increased by using the key as to whether or not this switching is performed and the switching cycle.

As described above, the first key information K
_E1 and second key information K _E2 obtained by data conversion of _E1
And are used for encryption, and the first and second key information K _E1 and K _E2 are used for encryption and decryption, which makes decryption complicated and difficult to break. With
The handling of the encryption key information can be simplified.

Further, manufacturer identification information, seller identification information,
By combining device identification information, copy protection information, and billing information that are set separately, and encrypting and recording the data, copy protection, pirated copy prevention, unauthorized use prevention, etc. are realized at the physical format level. I am trying to get it done. Further, information on the data security function, for example, copy permission / non-permission information and paid / grant information is implemented in the physical format of the recording medium and the recording / reproducing system.

That is, the security / billing information is recorded in the medium in advance, the identification information recorded or not recorded in the medium is used, and the identification information is combined with the data encryption. Prevents use. Also, having it in the physical format makes it difficult to decipher. Also, it is safe because it remains encrypted even if it is dump copied. In addition, sector units, file units, zone units,
It can be changed in units of layers. Furthermore, communication and IC
The key can be controlled with a card or remote control. Furthermore, a history can be recorded for the pirated board.

The present invention is not limited to the above embodiments. For example, an example of an inverter or an ExOR is shown as the data conversion, but in addition to this, bit addition, various logical operations, etc. It goes without saying that the data conversion may be performed according to. Further, it is needless to say that the present invention can be applied to general data transmission including not only recording / reproduction of data on / from a recording medium but also transmission / reception via a communication medium. In addition, various changes can be made without departing from the spirit of the present invention.

[0071]

According to the present invention, the encryption processing is performed using the first key information, and the second key information obtained by converting the data of the first key information is used for the encryption processing. Since the processing is performed, it is possible to duplicately encrypt the data with a single key information, and the first key information and the second key information are encrypted at different places. , It is possible to make the decryption of the encryption difficult while simplifying the handling of the key information, and to enhance the data security.

Further, by transmitting the first key information, when the identification information or the authentication information is used for the first key information, the authentication can be performed without the need for the encryption / decryption processing, and the speed can be increased. After authentication, a secure encryption / decryption process using the second key information can be performed.

Further, by transmitting only the second key information, even if the second key information is leaked, the cipher is not broken and the decryption can be made more difficult.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a data recording device to which an embodiment of the present invention can be applied.

FIG. 3 is a block diagram showing a configuration example for realizing even / odd byte interleaving in the sectorization circuit.

FIG. 4 is a diagram for explaining interleaving of even / odd bytes.

FIG. 5 is a diagram showing an example of a scrambler.

FIG. 6 is a diagram showing preset values of a scrambler.

FIG. 7 is a diagram showing an example of a scrambler whose generator polynomial is variable.

FIG. 8 is a diagram showing an example of a sector format.

FIG. 9 is a diagram for explaining an example of encryption in a synchronization area in a sector.

FIG. 10 is a diagram showing an example of an error correction coding circuit.

FIG. 11 is a diagram showing another example of the error correction coding circuit.

FIG. 12 is a diagram for explaining an example of encryption processing in a modulation circuit.

FIG. 13 is a diagram showing a specific example of a synchronization word added to a modulation signal.

FIG. 14 is a diagram for explaining an example of encryption in the synchronization adding circuit.

FIG. 15 is a diagram showing an example of a data recording medium.

FIG. 16 is a block diagram showing a schematic configuration of an embodiment of a data reproducing apparatus of the present invention.

FIG. 17 is a diagram for explaining an example of encryption processing in a demodulation circuit.

FIG. 18 is a diagram showing an example of an error correction decoding circuit.

FIG. 19 is a diagram showing another example of the error correction decoding circuit.

[Explanation of symbols]

 5, 25, 125 Key information supply circuit 6, 26, 126 Data conversion circuit 13 Sectorization circuit 14 Scramble processing circuit 15 Header addition circuit 16 Error correction coding circuit 17 Modulation circuit 18 Synchronization addition circuit 57, 142 Inverter group 61, 66 , 151, 156 ExOR circuit group 114 synchronization separation circuit 115 demodulation circuit 116 error correction decoding circuit 117 sector decomposition circuit 118 header separation circuit 119 descramble processing circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Isao Kawashima 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (9)

[Claims] 1. A data transmission method for performing encryption processing on input digital data for transmission, and a step of performing encryption processing using first key information, and obtaining the first key information by data conversion. And a step of performing an encryption process using the obtained second key information. 2. The data transmission method according to claim 1, wherein the first key information and the second key information are used for different encryptions. 3. The data transmission method according to claim 1, wherein the first key information and the second key information are switched and used for encryption. 4. The data transmission method according to claim 1, wherein at least a part of the first key information includes identification information. 5. The data transmission method according to claim 1, wherein at least the first key information is transmitted together with a data signal. 6. The data transmission method according to claim 1, wherein only the second key information is transmitted together with a data signal. 7. A data recording device for performing encryption processing on input digital data and recording the same on a recording medium, the first key information for encryption and a second key information obtained by data conversion of the first key information. And a key information output means for outputting the key information of the key information and a means for performing the encryption processing according to the first and second key information from the key information output means. apparatus. 8. An encryption process according to first key information for input digital data, and an encryption process according to second key information obtained by data conversion of the first key information. A data recording medium, characterized in that a signal obtained by applying the above is recorded. 9. A data reproducing apparatus for reproducing a signal recorded on a recording medium by performing encryption processing on input digital data, and first key information used at the time of the encryption processing, and Key information output means for outputting second key information obtained by converting the first key information, and encryption according to the first key information and the second key information from the key information output means. And a decryption means for performing the decryption process of 1. in the data reproducing device.