JPH0951079A - Semiconductor element and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element having excellent charge storage unit of a boundary between a lower electrode and a ferroelectric layer. SOLUTION: The semiconductor element comprises a charge storage unit 27 having a lower electrode 17, a ferroelectric layer 24 and an upper electrode 26 on a substrate 11 containing Si element, wherein the lower electrode is formed by providing at least a Pt-Ti allow layer, a Pt-Ta alloy layer or a Pt-Zr alloy layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Along with the high integration of semiconductor memories, research has been progressing to provide a capacitor insulating film having a high dielectric constant in its charge storage portion. Therefore, as a specific material, lead zirconate titanate (PZT), which is a crystalline oxide dielectric, is used.
Barium strontium titanate (BST) and the like are attracting attention. As the lower electrode in the charge storage portion in which the capacitor insulating film is composed of the crystalline oxide dielectric layer,
A platinum electrode that is chemically stable to the crystalline oxide dielectric is used. Further, when the lower electrode is directly connected to the source or drain region of the transistor provided on the Si substrate, Si and Pt react with each other and an impurity oxide (for example, an impurity oxide) is formed at the interface between Pt and the crystalline oxide dielectric layer. Since SiO ₂ ) is formed, there is a problem that the characteristics of the crystalline oxide dielectric layer are deteriorated. Therefore, conventionally, the Ti layer is used as a barrier layer between the Pt and the Si substrate.

[0003]

However, also in the case of a Ti layer which is considered to be usable as a barrier layer, for example, reference I (Jpn. J. Appl. Phys. Vol.
33, 1994, pp. 5207-5210), it has become clear in recent years that the following problems occur.

When a titanium layer is provided between the platinum layer and the poly-Si layer, the heat treatment causes Ti and Si to react with each other to cause T
iSi is formed.

Furthermore, since Si in poly-Si is diffused into the platinum layer, PtSi is formed in the platinum layer. When PtSi is formed on the platinum layer, Si on the surface of the platinum layer reacts with oxygen (O ₂ ) to form a silicon oxide (SiO ₂ ) film. Therefore, when a semiconductor element is operated to accumulate charges in a crystalline oxide dielectric layer (hereinafter referred to as a ferroelectric layer), SiO having a dielectric constant smaller than that of the ferroelectric layer is used.
_{2 When} electric charge is accumulated in the film and the semiconductor element is operated,
Since charges are accumulated in the SiO ₂ film and the amount of charges is reduced,
It may cause malfunction.

In addition, Si is formed at the interface between the platinum layer and the ferroelectric layer.
When the O ₂ film is formed, there is a problem in that the interface consistency also deteriorates.

Further, when the titanium layer is provided between the platinum layer and the poly-Si layer, the platinum layer cannot be thinned. The reason is that, when the heat treatment is performed in an oxygen atmosphere, if the platinum layer is thin, oxygen diffuses into the platinum layer and reacts with the underlying Ti layer to form a TiO _x layer. Since this TiO _x layer has a low dielectric constant, when the semiconductor element is operated, electric charges are not accumulated in the ferroelectric layer but are accumulated in the TiO _x layer, which causes deterioration of semiconductor element characteristics. Becomes

In order to solve such a problem, conventionally, Document II (Extended Abstracts of) has been proposed.
the 1993 International C
onence on Solid State
Devices and Materials, 199
3, pp. 871-873),
The platinum (Pt) layer has a thick film thickness of about 200 nm, and a Ti layer is provided on the lower surface of the platinum layer to prevent Si diffusion or to set the temperature when forming the ferroelectric layer as low as possible. Therefore, a method has been taken so that Si in poly-Si does not diffuse to the surface of the Pt layer. But P
If the thickness of the t layer is increased, the cost becomes higher, and the charge accumulated in the ferroelectric layer is increased due to the influence of α rays emitted from Pt, causing a soft error problem. To do.

[0009]

Therefore, according to the first invention, in a semiconductor element having a charge storage portion composed of a lower electrode, a ferroelectric layer and an upper electrode on a base containing a silicon element, It is characterized in that the lower electrode is composed of at least a Pt—Ti alloy layer, a Pt—Zr alloy layer, or a Pt—Ta alloy layer.

According to the second invention, in manufacturing the semiconductor device of the first invention, the lower electrode is formed by sequentially forming a first metal layer made of titanium, tantalum or zirconium and a platinum layer on a base. The method is characterized by including a step, a step of converting the first metal layer into a platinum-based alloy layer by heat treatment in a non-oxidizing atmosphere, and a step of forming a ferroelectric layer on the platinum-based alloy layer.

According to the third aspect of the invention, the charge storage portion is formed by a method including the following steps.

(A) A step of forming a first metal layer made of titanium or zirconium on the underlayer. (B) A step of forming a platinum layer on the first metal layer and then etching the platinum layer into a lower electrode shape to form a platinum pattern.

(C) A step of converting the portion of the first metal layer facing the platinum pattern into a platinum alloy layer by heat treatment in a non-oxidizing atmosphere.

(D) A step of converting the exposed first metal layer into a metal oxide layer by thermal oxidation of the sample on which the platinum alloy layer has been formed.

(E) A step of forming a ferroelectric layer on the surface of the platinum pattern and the metal oxide layer.

According to the fourth aspect of the invention, the second and third aspects are provided.
In carrying out the invention, a structure including a silicon substrate, a polysilicon plug provided on a part thereof, and a group IV-based metal oxide provided around the polysilicon plug is used as a base, Pb as a ferroelectric layer
(Zr _1-x Ti _x ) O ₃ layer, PbTiO ₃ layer, SrTi
An O ₃ layer or a (Ba _1-y Sr _y ) TiO ₃ layer is used.

According to the first aspect of the present invention, at least the platinum-titanium (Pt-Ti) alloy layer, the platinum-tantalum (Pt-Ta) alloy layer or the platinum-zirconium (P) is used as the lower electrode.
t-Zr) alloy layer is used. Below, platinum-
Titanium (Pt-Ti) alloy layer, platinum-tantalum (Pt-
Ta) alloy layer or platinum-zirconium (Pt-Zr)
The alloy layer is called a platinum alloy layer. Since such a platinum-based alloy layer is provided, the platinum-based alloy layer serves as a barrier layer against heat treatment after the platinum-based alloy layer is formed. Therefore, since the platinum-based alloy layer as the barrier layer is formed on the lower electrode, it is possible to prevent the diffusion of oxygen in the oxygen atmosphere to the underlayer, and to prevent the underlying silicon element from diffusing to the surface of the lower electrode. It can be prevented.

According to the second invention, when the semiconductor element of the first invention is manufactured, the platinum layer is formed after the first metal layer made of titanium, tantalum or zirconium is formed on the underlayer. By heat treatment in a non-oxidizing atmosphere, the first metal layer is changed to a platinum alloy layer (platinum-titanium (Pt-Ti) alloy,
It is changed to one kind of alloy layer selected from a platinum-tantalum (Pt-Ta) alloy and a platinum-zirconium (Pt-Zr) alloy. By such a treatment, the platinum alloy layer is already formed before the heat treatment in the oxygen atmosphere. Therefore, by forming the ferroelectric layer on the platinum-based alloy layer, the platinum-based alloy layer serves as a barrier layer when the underlying Si element diffuses, so that the interface between the platinum-based alloy layer and the dielectric layer is increased. Improves consistency.

Further, since the metal element of the first metal layer is also diffused into a part of the platinum layer by the heat treatment in the non-oxidizing atmosphere to form the platinum alloy layer, the thickness of the platinum layer can be reduced.

According to the third invention, the exposed first metal layer is changed to the metal oxide layer by the thermal oxidation method. If a metal such as titanium (Ti) or zirconium (Zr) is used as the first metal layer, TiO _x is used.
Alternatively, it is changed to a metal oxide layer made of ZrO _x . A ferroelectric layer (Pb) is formed on the metal oxide layer and the platinum pattern.
(Zr _1-x Ti _x ) O ₃ layer, SrTiO ₃ layer, PbTi
O ₃ layer or _{(Ba 1-y Sr y)} TiO 3 layer) to form a. Therefore, the crystal structures of the materials of the metal oxide layer and the ferroelectric layer are close to each other even if heat treatment is performed in an oxygen atmosphere,
Therefore, stress relaxation occurs in the ferroelectric layer and the generation of cracks is suppressed.

According to the fourth aspect of the invention, a silicon substrate as a base, a polysilicon plug provided on a part of the silicon substrate, and an I provided around the polysilicon plug.
A structure containing a group V metal oxide is used, and a Pb (Zr _1-x Ti _x ) O ₃ layer and PbTiO ₃ are used as a ferroelectric layer.
Layer, SrTiO ₃ layer or (Ba _1-y Sr _y ) TiO ₃
Use layers. For this reason, both the group IV-based gold oxide layer as the base and the ferroelectric layer formed on the upper side of the base are made of crystalline oxide, and therefore even if heat treatment is performed in an oxygen atmosphere. The crystal structures of the material of the underlayer and the material of the ferroelectric layer are similar to each other, so that stress relaxation occurs in the ferroelectric layer and the generation of cracks is suppressed.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device structure of the first invention and a manufacturing method of the second to fourth inventions will be described below with reference to the drawings.
An embodiment applied to the charge storage unit of AM will be described.
It should be noted that FIGS. 1 to 9 merely schematically show the shapes, sizes, and arrangement relationships of the respective constituent components to the extent that the present invention can be understood.

1. 1. Semiconductor device structure of first invention 1-1. First Embodiment FIG. 1 is a sectional view for explaining the structure of a first embodiment of a semiconductor device.

The DRAM comprises a transistor portion (not shown) and a charge storage portion (capacitor portion) 27. However, in FIG. 1, the charge storage section is mainly shown, and the transistor section is omitted. In this embodiment, the base 11, the charge storage portion 27, and the interlayer insulating layer 28 form a part of the DRAM.

The underlayer 11 is composed of a silicon (Si) substrate 10 and a silicon oxide layer 14 having a poly-Si plug 16. Incidentally, here, the poly-Si plug 1
6 is also called a poly-Si pillar.

In the first embodiment, the Si substrate 10 is, for example, a p-type conductive silicon substrate (hereinafter referred to as a substrate).
Is used. A storage node diffusion layer 12 is provided on the substrate 10. A silicon oxide layer 15 with poly-Si is provided on the substrate 10 having the diffusion layer 12. The silicon oxide layer 15 with poly-Si is formed on the poly-Si pillar 16
And the silicon oxide layer 14 provided around the poly-Si pillar 16. Further, the storage node diffusion layer 12 and the poly-Si pillar 16 are electrically connected.

Further, in the first embodiment, the lower electrode 17, the ferroelectric layer 24 and the upper electrode 26 are provided on the silicon oxide layer 15 with poly-Si, respectively. Here, the lower electrode 17 is the titanium nitride (TiN) layer 18 here.
And a Pt-Ti alloy layer 20 and a platinum (Pt) layer 22 have a three-layer structure. TiN in the first embodiment
The reason for forming the layer 18 is to suppress diffusion of the metal (for example, Pt) of the lower electrode, which is a known technique, into the poly-Si pillar 16 (Extended Abstract).
s of the 1994 International
al Conference on Solid St
ate Devices and Material
s, Yokohama, 1994, pp. 721-72
3).

As the material of the ferroelectric layer, one kind of material selected from lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT) or lead titanate (PTO) is used. . Here, PZT, which is relatively easy to handle, is used. Further, platinum (Pt) is used as the material of the upper electrode 26. In the first embodiment, the lower electrode 17, the ferroelectric layer 24 and the upper electrode 26 are collectively referred to as the charge storage section 27.

Furthermore, in the first embodiment, the entire surface of the silicon oxide layer 15 with poly-Si including the charge storage portion 27 is covered with the interlayer insulating layer 28. The material of the interlayer insulating layer 28 is SiO ₂ .

1-2. Second Example Further, a Pt-Ta alloy layer is used instead of the Pt-Ti alloy layer 20. The other structure is similar to that of the first embodiment (FIG. 1), and detailed description thereof will be omitted.

1-3. Third Example Further, a Pt-Zr alloy layer is used instead of the Pt-Ti alloy layer 20. The other structure is the same as that of the first embodiment, and detailed description thereof will be omitted.

2. Manufacturing method of second invention 2-1. Manufacturing Method of First Embodiment Next, a method of manufacturing the semiconductor device of the first embodiment of the second invention will be described with reference to FIGS. Incidentally, FIG. 2 (A)
3A to 3C and FIGS. 3A to 3C are cross-sectional views for explaining the manufacturing process of the first embodiment.

First, a storage node diffusion layer 12 is formed on a p-type conductive Si substrate (hereinafter referred to as a substrate) 10.

Next, silicon oxide (S
After forming the iO ₂ ) layer 14, a contact hole is formed in the SiO ₂ layer 14 (not shown). At this time, it is preferable to penetrate the contact hole so as to reach the storage node diffusion layer 12. Next, poly-Si pillars 16 are formed by filling the contact holes with poly-Si (FIG. 2A). The silicon oxide layer 14 having poly-Si pillars is referred to as a silicon oxide layer 15 with poly-Si here. In addition, the silicon oxide layer 15 with poly-Si and the substrate 1
0 is collectively referred to as the base 11.

Next, a titanium nitride (TiN) layer 18 is formed on the SiO ₂ layer 15 with poly Si by a reactive sputtering method. Although the reactive sputtering method is used in this embodiment, the titanium nitride layer 18 may be formed by using the titanium rapid nitriding (RTN) method.

Next, the first metal layer 19 is formed on the TiN layer 18 by using the sputtering method (FIG. 2B).
In the first embodiment, titanium (T
Since i) is used, it is also called a Ti layer. This Ti layer 1
As a method of forming 9, the vapor deposition method may be used instead of the sputtering method. However, in any method, the Ti layer 19 is formed at room temperature (25 ° C.).
The thickness of the Ti layer 19 is about 100 Å here. However, the film thickness of the Ti layer 19 here is a preferable value in this embodiment, and the film thickness may be in the range of 50 to 100 Å.

Next, a platinum (Pt) layer 22 is formed on the Ti layer 19 by using, for example, an evaporation method ((C) in FIG. 2).
In the first embodiment, the thickness of the platinum layer 22 is about 500Å
And

Next, heat treatment is performed in a non-oxidizing atmosphere to perform T
The i layer 19 is changed to the platinum alloy layer 20 ((A) of FIG. 3). In this example, the heat treatment conditions for forming the Pt-Ti alloy layer are as follows.

Atmosphere gas: Nitrogen (N ₂ ) gas or Argon (Ar) gas Heat treatment temperature: 600 to 800 ° C. Treatment time: 10 to 30 minutes By performing the heat treatment described above, a part of the Ti layer and the Pt layer are separated from each other. The Ti layer is diffused and converted into the Pt—Ti alloy layer 20.

Next, the ferroelectric layer 24 is formed on the platinum layer 22. The material of the ferroelectric layer 24 is, for example, Pb.
(Zr _1-x Ti _x ) O ₃ , PbTiO ₃ , SrTiO ₃
Or the like _{(Ba 1-y Sr y)} TiO 3. In addition, x and y described in the material of the ferroelectric layer represent a composition ratio. In addition, when the ferroelectric layer 24 is formed,
A heating temperature of about 700 ° C is required.

Next, this ferroelectric layer 24 is formed by using the vapor deposition method.
The upper electrode 26 is formed on the upper surface (FIG. 3B). Here, the upper electrode 26 is a platinum (Pt) electrode.

Next, any suitable selective etching method is used.
Platinum layer 26, ferroelectric layer 24, platinum layer 22, Pt-T
A part of the i layer 20 and the TiN layer 18 is etched to remove electric charge.
The load storage unit 27 is formed. After that, the charge storage unit 27 is covered.
SiO with poly Si ₂ Interlayer insulation on the surface of layer 15
The layer 28 is formed (FIG. 3C). Such a process
After that, the semiconductor device of the first embodiment is completed.

FIGS. 10A and 10B show a sample in which a TiN layer and a Ti layer are formed on a Si substrate, and a platinum layer (film thickness: about 500Å) is formed on the Ti layer. It is the figure which measured surface roughness with the atomic force microscope. In the figure, the horizontal axis represents the distance (nm) and the vertical axis represents the surface roughness (nm). Also, (A)
Shows the surface roughness of the platinum layer without annealing, and (B) shows the surface roughness when annealed at about 700 ° C. in nitrogen gas.

As can be understood from the measurement results of FIGS. 10A and 10B, the surface roughness (height difference of unevenness) is 1 to 2 nm without annealing. However, when annealed (700 ° C., nitrogen gas), the surface roughness is 3
It becomes 0-40 nm. Incidentally, FIG. 10B corresponds to a conventional semiconductor element.

FIG. 10C shows Ti as in the present invention.
A platinum alloy (Pt-Ti alloy, P
It is a figure which shows the surface roughness at the time of providing a (t-Ta alloy or Pt-Zr alloy) layer and annealing (700 degreeC, nitrogen gas).

As can be understood from FIG. 10C,
The surface roughness of the present invention is about 5 nm, and the surface roughness of the Pt layer is ⅙ to ⅛ as compared with the prior art. Charge storage unit 27
Since a heating temperature of 600 to 700 ° C. is required for forming the above, the semiconductor element of the present invention can reduce the unevenness of the surface of the Pt layer due to annealing from the measurement result of the surface roughness described above. Therefore, the ferroelectric layer 2 is formed on the Pt layer 22.
When No. 4 is formed, it can be expected that the interface at the interface between the Pt layer 22 and the ferroelectric layer 24 becomes extremely good.

In addition, the annealing treatment (6
(00 to 800 ° C.), the Ti layer diffuses and reacts with the Pt layer to form the Pt—Ti alloy layer 20, and at the same time,
Since the elements of the Ti layer diffuse into the platinum layer 22, the initial P
It becomes thinner than the film thickness of the t layer.

Further, since the Pt-Ti alloy layer 20 is provided on the lower electrode, the Pt layer 22 of Si element from the base 11 is formed.
Can be prevented from spreading. Therefore, the thickness of the Pt layer 22 can be reduced. Therefore, as the Pt layer 22 can be made thinner, the cost of the product can be reduced. In addition, the Pt layer 22
Since the film thickness can be reduced, the charge emission from the ferroelectric layer due to α-rays can be reduced, and the soft error can be reduced. Also, Pt
Since the Ti layer 19 having the same element as TiN is formed between the layer 22 and the TiN layer 18, the film forming process and the etching process can be simplified.

2-2. Manufacturing Method of Second Embodiment Further, a method of manufacturing the semiconductor device of the second embodiment of the second invention will be described.

In the second embodiment, a manufacturing method for forming a tantalum (Ta) layer on the TiN layer 18 instead of the Ti layer 19 will be described.

First, the TiN layer 18 is formed on the base.
A Ta layer is formed on the TiN layer 18. When the Ta layer is used, the thickness is about 100Å. Then T
The Pt layer 22 is formed on the a layer under the same film forming conditions as in the first embodiment.

Next, the same temperature as that of the first embodiment (600-8)
Heat treatment in a non-oxidizing atmosphere at 00 ° C. to form a Ta layer,
Change to a Pt-Ta alloy layer. Therefore, when the Ta layer has the same thickness as the Ti layer of the first embodiment, the alloy layer is a Pt ₃ Ti alloy in the first embodiment, while the P layer is P in the second embodiment.
Since it is a t ₂ Ta alloy, Pt is
The thickness of the layer is 2/3 that of the case where the Ti layer is used, that is, 1
Can be /1.5.

FIG. 11 is an X-ray diffraction diagram when measuring an X-ray diffraction distribution curve when heat treatment is performed using a tantalum layer. The sample used for this measurement was SiO ₂ on the substrate.
After sequentially forming the layer, the Ta layer, and the platinum layer, heat treatment (700 ° C.) is performed in a nitrogen gas atmosphere. This sample is measured by an X-ray diffractometer. In the figure, the horizontal axis is 2θ (angle)
Is plotted and the vertical axis shows the X-ray intensity.

As can be understood from FIG. 11, Ta appears near 32 degrees, Pt ₂ Ta appears near 38 degrees, and 4
Pt appears near 0 degrees and Pt ₂ Ta appears near 42 degrees. From this measurement result, it was confirmed that a Pt ₂ Ta alloy was formed.

However, since the Ta element is shown in this X-ray diffraction curve, it is necessary to control the heating temperature and the holding time during the actual film formation to change to a Pt-Ta alloy containing no Ta element.

2-3. Manufacturing Method of Third Embodiment Next, a manufacturing method of the third embodiment of the second invention will be described.

In the third embodiment, the Pt layer 22 and the TiN layer 1
8 is a manufacturing method in the case of forming a zirconium (Zr) layer instead of the Ti layer.

First, the TiN layer 18 is formed on the underlayer 11. A Zr layer is formed on this TiN layer 18. In addition, Zr
The layer thickness is about 100Å.

Next, heat treatment is performed in a non-oxidizing atmosphere.
The heat treatment temperature is the same as that of the first embodiment (600 to 8).
00 ° C). By such heat treatment, the Zr layer becomes Pt.
_{An 11} Zr ₉ alloy layer is formed. Therefore, even if the Zr layer has the same film thickness as that of the Ti layer, which is already described, compared with Ti, Zr
Since the diffusion of Al is slow, the number of atoms diffusing into the Pt layer is reduced. Therefore, the film thickness of the Pt layer can be made smaller than that when the Ti layer is used. In the third embodiment, the film thickness of the Pt layer can be reduced to 1 / 1.6 as compared with the first embodiment.

2-4. Manufacturing Method of Fourth Embodiment Further, in the manufacturing methods of the second, first, second and third embodiments of the present invention, a Ti layer, Ta,
Although a layer or a Zr layer was formed respectively, in the fourth embodiment, instead of the Ti layer, the Ta layer or the Zr layer, a platinum-based alloy layer (Pt-Ti) was directly formed on the TiN layer 18 by using a sputtering method.
Layer, Pt—Ta layer or Pt—Zr layer). In this case, an alloy target of Pt and Ti is used as the target of the sputtering device. When used with Ta, Pt
When using Zr and an alloy target of Ta and Ta, P
An alloy target of t and Zr is used.

The fourth embodiment does not require a heat treatment step as in the first to third embodiments, and therefore has an advantage that the manufacturing process can be simplified.

3. Manufacturing Method of Third Invention Next, a manufacturing method of the third invention will be described with reference to FIG. Prior to the description of the manufacturing method of the third invention, the structure of the embodiment of the third invention will be described first. FIG.
It is sectional drawing for demonstrating the semiconductor element structure of 3rd invention.

In the semiconductor device of this embodiment, the underlayer 11 has the same structure as that of the first embodiment of the first invention described above.

Further, the structure in which the lower electrode 17 is provided on the SiO ₂ layer 15 with poly-Si is similar to that of the first embodiment. In this embodiment, the first interlayer insulating layer 30 is provided on the sidewall surfaces of the TiN layer 18 and the platinum-based alloy layer 20 and the silicon oxide layer 14 on these surfaces. In this embodiment, the material of the first interlayer insulating layer 30 is TiO _x or ZrO _x .

Further, an upper electrode 34 is provided on the ferroelectric layer 32. A second interlayer insulating layer 36 is formed on the upper electrode 34.
Is provided. The ferroelectric layer 32 and the upper electrode 34
The material is the same as that of the first embodiment of the first invention. The material of the second interlayer insulating layer is SiO ₂ .

Next, the manufacturing method of the third embodiment of the present invention will be described with reference to FIGS.

5A to 5C and 6A to 6C.
(B), (A) to (C) of FIG. 7, and (A) to (B) of FIG.
[FIG. 8] A sectional view for illustrating the manufacturing process for the embodiment of the third invention.

The storage node diffusion layer 12 is formed on the Si substrate 10, and the silicon oxide layer 15 with poly-Si is formed on the substrate 10 (FIG. 5A). A TiN layer 18 is formed on the silicon oxide layer 15 with poly Si (FIG. 5).
(B)). The steps up to this point are the same as the steps of the first embodiment described above. Therefore, detailed description is omitted. In this embodiment, TiN layer 18 is etched using any suitable method to form TiN pattern 18a.

Next, poly S containing the TiN pattern 18a is formed.
A Ti layer 19 is formed on the i-attached silicon oxide layer 15 so as to cover the TiN pattern ((A) of FIG. 6). still,
Here, the film thickness of the Ti layer 19 is set to about 100 Å.

Next, the platinum layer 22 is formed on the Ti layer 19 by using, for example, a vapor deposition method (FIG. 6B). The thickness of the platinum layer 22 is about 500Å here.

Next, the platinum layer 22 is etched by etching to form a platinum pattern 22a ((A) of FIG. 7). In addition, the platinum layer pattern 22a at this time is Ti
It is preferable that the shape is substantially the same as the shape of the N pattern 18a.

Next, the structure shown in FIG. 7A is heat-treated under the following conditions.

Atmosphere gas in the furnace: nitrogen (N ₂ ) gas or argon (Ar) gas Heat treatment temperature: 600 to 800 ° C. Heat treatment time: 10 to 30 minutes By such heat treatment, the Ti layer 19 and the platinum pattern 22 are formed.
Mutually diffuses with a to form a Pt-Ti alloy layer 20 (FIG. 7B). By this heat treatment, the Ti layer 19 in the portion where the platinum pattern 22a is laminated on the Ti layer 19 is
Instead of the Pt-Ti alloy layer 20, the platinum pattern 22a
The Ti layer 19 other than that in contact with is left as it is as a Ti layer. At this time, the remaining Ti layer is represented by the symbol 19a.

Next, the structure shown in FIG. 7B is thermally oxidized in an oxygen atmosphere. The conditions of the thermal oxidation treatment are as follows.

Heat treatment temperature: 500 to 600 ° C. Heat treatment time: 5 to 30 minutes By such heat treatment, the Ti layer 19a in the portion not covered with the platinum pattern is changed to the TiO _x layer 30 (FIG. 7).
(C)).

Next, TiO _x containing the platinum pattern 22a is formed.
A ferroelectric layer 32 is formed on the layer 30 ((A) of FIG. 8). The material of the ferroelectric layer 32 used in this embodiment is the same as the material of the first embodiment already described.

Next, the ferroelectric layer 3 is formed by using, for example, a vapor deposition method.
The upper electrode 34 is formed on the surface 2. Here, the upper electrode 34 similar to that of the first embodiment is a platinum layer.

Next, the second interlayer insulating layer 36 is formed on the platinum layer 34.
Are formed ((B) of FIG. 8). The semiconductor device of this embodiment is completed through the steps described above.

In this embodiment, the lower electrode 17 (platinum pattern 22a / Pt-Ti) is formed before the ferroelectric layer 32 is formed.
Since the alloy layer 20 / TiN pattern 18a) is formed,
It is not necessary to etch the ferroelectric layer and the Pt layer as in the first embodiment of the first invention. Therefore, damage to the ferroelectric layer due to etching can be reduced. In addition, TiO _x is formed between the silicon oxide layer 14 of the base 11 and the ferroelectric layer 32.
Since the layer 30 is formed, cracks generated in the ferroelectric layer 32 are reduced. The reason why the cracks in the ferroelectric layer are reduced is that the material of the ferroelectric layer 32 and the structure of the crystal lattice of the first interlayer insulating layer 30 are similar to each other, and the stress relaxation of the ferroelectric layer is caused by the annealing treatment. It is thought to be caused.

In the embodiment of the third invention described above, the Ti layer was used as the metal layer sandwiching the TiN layer and the platinum layer, but a zircon (Zr) layer may be used instead of the Ti layer. When the Zr layer is used, the first interlayer insulating layer 30 is a ZrO _x layer.

4. Manufacturing Method of Fourth Invention Next, prior to description of the manufacturing method of the fourth invention, the structure of the semiconductor element of the fourth invention will be described with reference to FIG.

FIG. 9 is a sectional view for explaining the structure of the semiconductor device of this embodiment.

This embodiment is different from the structure of the first embodiment of the first invention in that a group IV oxide layer 52 is provided in place of the silicon oxide layer 14 forming the underlayer 11. . The other structure is similar to that of the first embodiment. Therefore, detailed description is omitted.

[0084] Further, in this embodiment, IV group series titanium oxide (TiO _x) as the material of the oxide layer 52, zirconium oxide (ZrO _x), or hafnium oxide (HfO _X)
Is used. Such a titanium oxide (TiO _x ) layer, zirconium oxide (ZrO _x ) layer or hafnium oxide (HfO _x ) layer is used.

Next, the manufacturing method of the fourth embodiment of the present invention will be described with reference to FIG.

In this embodiment, after the storage node diffusion layer 12 is formed on the Si substrate 10, a Ti layer (not shown) is formed on the Si substrate 10.

Next, the Ti layer is formed into TiO _x by using the thermal oxidation method.
Change to layer 52. After that, a contact hole is formed in the TiO _x layer 52 (not shown).

Next, poly-Si pillars 16 are formed by burying poly-Si in the contact holes and performing predetermined heating.

Lower electrode 17 and ferroelectric layer 2 after the next step
4, the method of forming the upper electrode 26 and the interlayer insulating layer 28 is the same as in the first embodiment of the first invention. Therefore, detailed description is omitted here. In this embodiment, a TiO _x layer is used instead of the SiO ₂ layer as the insulating film of the underlayer 11, and this T
Since the ferroelectric layer 24 is formed on the upper side of the iO _x layer, cracks generated in the ferroelectric layer can be reduced. The reason for reducing cracks in the ferroelectric layer is that the material of the group IV oxide layer has a crystal lattice structure similar to that of the material of the ferroelectric layer.
It is also considered that stress relaxation occurs due to annealing.

In the second, third and fourth inventions, the first metal layer formed on the lower electrode is a platinum layer and a Ti layer.
Since it also diffuses into the N layer, the adhesion between the platinum layer and the TiN layer is improved.

[0091]

As is apparent from the above description, according to the first aspect of the invention, at least the lower electrode of the semiconductor element is made of P.
It is composed of a t-Ti alloy layer, a Pt-Ta alloy layer or a Pt-Zr alloy layer. Therefore, even if the sample including the alloy layer is heat-treated, the alloy layer functions as a barrier layer, so that the underlying Si element can be prevented from diffusing into the platinum layer. Therefore, when the semiconductor element is operated to charge or output electric charge to the ferroelectric layer, the electric charge is sufficiently supplied into the ferroelectric layer, so that the operation of the semiconductor element is stabilized.

According to the second invention, when the semiconductor element is manufactured, after the first metal layer made of titanium, tantalum or zirconium and the platinum layer are formed on the base,
Heat treatment in a non-oxidizing atmosphere is performed to convert the first metal layer into a platinum alloy layer. Then, a ferroelectric layer is formed on the platinum alloy layer. For this reason, even if the heat treatment for forming each layer is performed after the lower electrode is formed, the alloy layer is a base Si layer.
Therefore, the diffusion of Si into the platinum layer is suppressed. Therefore, the thickness of the platinum layer can be reduced. Since the platinum layer can be made thinner, the cost of the product can be reduced,
In addition, it is possible to reduce so-called soft error, in which the charge accumulated in the ferroelectric layer is released under the influence of α rays emitted from Pt. Furthermore, the matching of the interface between the platinum layer and the ferroelectric layer is improved.

Further, according to the third aspect of the invention, when the semiconductor element is manufactured, the metal oxide (titanium oxide or zirconium oxide) layer is provided between the base and the ferroelectric layer. Therefore, when heat treatment is performed, the metal oxide layer and the ferroelectric layer have similar crystal lattice structures, and the stress in the ferroelectric layer is relieved to occur in the ferroelectric layer. Cracks can be reduced.

According to the fourth aspect of the invention, when a semiconductor element is manufactured, a group IV group metal oxide layer is formed around the Si pillar provided on the base, and then a ferroelectric layer is formed on the base. Since it is formed, when heat treatment is performed, the metal oxide layer and the ferroelectric layer have a similar crystal lattice structure, and the stress of the ferroelectric layer is relieved, so that it is generated in the ferroelectric layer. It is possible to reduce the number of cracks.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining a structure of a semiconductor device of a first invention.

2A to 2C are process drawings provided for explaining the manufacturing method of the second embodiment of the first invention.

3A to 3C are process diagrams provided for explaining the manufacturing method following the process of FIG.

FIG. 4 is a sectional view for explaining the structure of a semiconductor device of a third invention.

5A to 5C are process drawings provided for explaining a method for manufacturing a semiconductor device of the third invention.

6A to 6B are process diagrams provided for explaining the manufacturing method following the process of FIG.

7A to 7C are process drawings provided for explaining the manufacturing method, following the process of FIG.

8A to 8B are process diagrams provided for explaining the manufacturing method subsequent to the process of FIG.

FIG. 9 is a cross-sectional view for explaining the structure of the semiconductor device of the fourth invention.

10 (A) to (C) are diagrams showing the surface roughness of the platinum layer depending on the presence or absence of the annealing treatment.

FIG. 11 is an explanatory diagram for explaining an X-ray diffraction distribution curve of a Pt-Ta alloy.

[Explanation of symbols]

10: Si substrate 11: Underlayer 12: Storage node diffusion layer 14: Silicon oxide layer 15: Silicon oxide layer with poly-Si 16: Poly-Si plug 17: Lower electrode 18: TiN layer 18a: TiN pattern 19: Ti layer 20: Platinum System alloy layer 22: Platinum layer 22a: Platinum pattern 24: Ferroelectric layer 26: Upper electrode 27: Charge storage part 28: SiO ₂ layer

Claims (6)

[Claims] 1. A semiconductor device comprising a charge storage portion composed of a lower electrode, a ferroelectric layer and an upper electrode on a base containing a silicon element, wherein the lower electrode comprises at least a Pt—Ti alloy layer and Pt—Ta. A semiconductor device comprising an alloy layer or a Pt-Zr alloy layer. 2. In manufacturing the semiconductor device according to claim 1, the lower electrode is formed by a step of (a) sequentially forming a first metal layer made of titanium, tantalum or zirconium and a platinum layer on a base. , (B) converting the first metal layer into a platinum-based alloy layer by heat treatment in a non-oxidizing atmosphere,
(C) forming a ferroelectric layer on the platinum-based alloy layer. 3. The method of manufacturing the semiconductor device according to claim 1, wherein the charge storage portion includes (a) a step of forming a first metal layer made of titanium or zirconium on a base, and (b) the first metal layer.
Forming a platinum layer on the metal layer, and then etching the platinum layer into a lower electrode shape to form a platinum pattern,
(C) a step of converting the first metal layer portion facing the platinum pattern into a platinum alloy layer by heat treatment in a non-oxidizing atmosphere, and (d) thermal oxidation of the sample on which the platinum alloy layer has been formed. And changing a portion of the first metal layer not covered with the platinum pattern into a metal oxide layer,
(E) A method of manufacturing a semiconductor device, which comprises forming a ferroelectric layer on the surface of the platinum pattern and on the metal oxide layer. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the ferroelectric layer is a Pb (Zr _1-x Ti _x ) O ₃ layer and Pb (Zr _1-x Ti _x ) O ₃ layer.
TiO ₃ layer, SrTiO ₃ layer or (Ba _1-y Sr y)
A method of manufacturing a semiconductor device, which comprises a TiO ₃ layer. 5. The method of manufacturing a semiconductor device according to claim 2, wherein a silicon substrate as a base, a polysilicon plug provided on a part of the silicon substrate, and a periphery of the polysilicon plug are provided. A structure including a group IV metal oxide layer is used, and Pb (Zr _1-x Ti _x ) O ₃ is used as the ferroelectric layer.
Layer, PbTiO ₃ layer, SrTiO ₃ layer or (Ba _1-y
Sr _y) The method of manufacturing a semiconductor device, which comprises using a TiO ₃ layer. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the Group IV metal oxide layer is titanium oxide (TiO _x ).
A method of manufacturing a semiconductor device, which is characterized by being formed of a material of zirconium oxide (ZrO _x ) or hafnium oxide (HfO _x ).