JPH0950420A - Arbitration method and arbiter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily constitute a logic circuit even when the frequency of an operation clock becomes a high speed and to prevent the transfer throughput of a bus from being reduced by performing state transition by plural clocks at all times for the state of signals outputted on a bus. SOLUTION: This arbiter 214 checks the state of bus request signals, performs arbitration by a round robin system and outputs bus grant signals. In the case of using the bus, bus connection devices 211-213 output bus request signals and monitor the bus grant signals and bus right transition signals. At the time of detecting a clock cycle in which the bus grant signals are outputted and the bus right transition signals are outputted, it means that the bus connection devices 211-213 obtain the bus using right, and address data and bus busy signals are outputted after two cycles, for instance. Also, the arbiter 214 stops the output of the bus grant signals after the two cycles and outputs the bus grant signals to the bus connection device to which the bus using right is to be given next by the arbitration and the bus connection device using the bus outputs the bus right transition signals in the last cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronous information processing device bus arbitration method and a bus arbiter.

[0002]

2. Description of the Related Art An arbitration method of a clock synchronous information processing device bus used in a conventional information processing device is as follows.
For example, PCI Local Bus Specification (PCI Spe
cial Interest Group: retail version, 2.0 version: April 30, 1993), pages 37 to 4
The PCI local bus arbitration method described on page 6 is known.

[0003]

Since the above-mentioned prior art is basically based on performing the state transition in one clock,
There is a problem that the configuration of the logic circuit becomes difficult when the frequency of the operating clock of the bus becomes high. For example, in the related art, when a bus connection device acquires the bus right in a certain clock cycle, the bus connection device outputs address data from the next cycle, and the arbiter transfers the bus connection device from the next cycle. The output of the bus grant signal is stopped, and the bus grant signal is output to the bus connection device to which the bus use right should be given next by arbitration. In this case, in the bus connection device and the arbiter, it is necessary to detect the state on the bus and output the next state to the state for the same clock edge. That is, the next state calculated by performing a logical operation on the state detected at a certain clock edge must be fixed on the bus by the next clock edge. For this reason, when the frequency of the bus clock becomes high, it becomes impossible to secure the time for the logical operation and it becomes difficult to implement the arbitration protocol.

It is an object of the present invention to provide an arbitration method for a clock synchronous information processing device bus in which the logic circuit can be easily constructed even when the operating clock frequency is high and the bus transfer throughput is not reduced. .

[0005]

In order to achieve the above object, the present invention is based on the principle that arbitration is always performed in a plurality of clocks. For example, when a bus connection device acquires the bus use right in a certain clock cycle, the bus connection device outputs the address data after two cycles, and the arbiter outputs the bus grant signal to the bus connection device after two cycles. The output was stopped and the bus grant signal was output to the bus connection device to which the bus use right should be given next by arbitration.

Further, according to the present invention, as the bus control signal, the bus connection transition signal indicating the transition timing of the bus right is provided by the bus connection device using the bus.

Further, according to the present invention, the arbiter outputs the bus right transition signal when the bus right changes from the idle state of the bus.

[0008]

According to the present invention, in arbitration, the state transition is always performed with a plurality of clocks. Therefore, the bus connection device and the arbiter output the next state relative to the state in response to the state detection on the bus. Should be performed for the next clock edge and subsequent clock edges. That is, for example, in the case of basically performing a state transition with a clock, for a state detected at a certain clock edge, a logical operation is performed by the next clock edge to calculate the next state, and the next clock is calculated. It can be confirmed on the bus by the edge. For this reason, even when the frequency of the bus clock becomes high, it is possible to always secure a time of one clock cycle or more for the logical operation, so that it is not difficult to implement the arbitration protocol.

Further, according to the present invention, as the bus control signal, the bus connection transition signal indicating the transition timing of the bus right is provided by the bus connection device using the bus.
By indicating the transition timing of the bus right in accordance with the arbitration in which the bus connection device makes the state transition in a plurality of clocks, the state transition can be made in a plurality of clocks without reducing the transfer throughput of the bus.

In the present invention, since the arbiter outputs the bus right transition signal when the bus right is changed from the idle state of the bus, the signal state on the bus is not changed even when the bus right is changed from the idle state. This is the same as the transition of the bus right from the idle state, and the bus connection device can always perform the bus right transition in the same sequence operation.

[0011]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing a configuration example of a bus system using an arbitration method according to the present invention, FIG. 2 is a timing chart of arbitration according to the related art, FIGS. 3 and 4 are timing charts of arbitration according to the present invention, and FIG. 3 is a state transition diagram showing an example of an internal configuration of an arbiter according to the present invention. FIG.

The present invention can be applied to a bus system having a centralized arbitration structure as shown in FIG.
In FIG. 1, 211 to 213 are three bus connection devices, 214 is an arbiter according to the present invention, and 101 to 10.
3 is a bus request line connected to the arbiter 14 from each of the three bus connection devices 211 to 213;
1 to 113 are bus grant lines connected from the arbiter 214 to each of the three bus connection devices 211 to 213, 121 is an address / data bus, 122 is a control bus, 215 is a clock generator, and 123 is a bus clock line, Reference numeral 124 is a bus right transition signal line.

In FIG. 1, three bus connection devices use the bus according to arbitration by the arbiter 214. The number of bus connection devices is arbitrary as long as it is plural, and CPU unit, memory unit, file system /
It may be an I / O unit such as a display system / network system, or an arbitrary combination such as a bridge with another bus. Further, the arbiter 214 may be mounted in a form included in any of the bus connection devices. Address / data bus 1
21 may be an address / data separation type / multiplex type. The control bus 122 uses the bus right transition signal line 12
Except for 4, the control bus can be configured in the same manner as the control bus of the conventional clock synchronous bus. In this embodiment, the entire bus system operates in synchronization with the clock distributed from the clock generator 215 by the bus clock line 123. In this embodiment, a general split transfer protocol is used as the bus transfer protocol. However, the present invention can be applied to any transfer protocol independent of the arbitration protocol.

The structure of FIG. 1 can be considered to be almost the same as the structure of the bus system according to the prior art except for the bus right transition signal line 124. In the prior art, another signal on the control bus is used as the bus right transition signal. FIG. 2 shows a timing chart when the conventional technique is applied to the bus system of FIG. In the timing chart of the present embodiment, n at the end of the signal name indicates that the signal has a negative polarity, and all signals operate synchronously in such a manner that the state is fixed at the rising edge of the clock CLK. The numbers at the top of the timing chart are clock cycle numbers given for explanation.

In FIG. 2, REQ (1) to (3) are bus request signals on the bus request signal line from the three bus connection devices (1) to (3) to the arbiter, GRT.
(1) to (3) are bus grant signals on the bus grant signal lines from the arbiter to the three bus connection devices (1) to (3), A / D is address data on the address / data multiplex bus, BUSY is a busy signal on the signal line in the control bus, which indicates that the bus is in use, and is a signal that is diverted as a bus right transition signal. In FIG. 2, the arbiter looks at the states of REQ (1) to (3) and performs arbitration by a general round robin method, and outputs a bus grant signal to at least one of GRT (1) to (3). . When the bus connection device wants to use the bus, it outputs each bus request signal a
Then, each bus grant signal and bus busy signal are monitored. When a bus grant signal is output b and c clock cycle 7 in which the bus busy signal is not output at the same time is detected, the bus connection device has acquired the right to use the bus, and the address data and the bus busy signal are output from the next cycle 8. Output d · e. At the same time, the arbiter stops the output of the bus grant signal to the bus connecting device f and outputs the bus grant signal to the bus connecting device to which the bus use right should be given next by arbitration.

In the prior art, the state of arbitration is that the state transition is always performed in one clock. That is, in FIG. 2, for example, when a clock cycle 7 in which a certain bus grant signal is output b and a bus busy signal is not output at the same time is detected, the bus connection device outputs address data and a bus busy signal from the next cycle 8. In addition, the arbiter stops the output of the bus grant signal to the bus connecting device from the next cycle f, and outputs the bus grant signal to the bus connecting device to which the bus use right should be given next by arbitration. In this case, in the bus connection device and the arbiter, it is necessary to detect the state on the bus and output the next state to the state for the same clock rising edge 7. That is, the next state calculated by performing a logical operation on the state detected at a certain clock rising edge 7 needs to be determined on the bus by the next clock rising edge 8. For this reason, when the frequency of the bus clock becomes high, it becomes difficult to secure the time for the logical operation, which makes it difficult to implement the arbitration protocol.

Next, FIG. 3 shows an example of a timing chart when the present invention is applied to the bus system of FIG. R in Figure 3
EQ (1) to (3), GRT (1) to (3),
A / D and BUSY are signals similar to those in FIG.
ANS is a bus right transition signal on the bus right transition signal line.
In FIG. 3, the arbiter looks at the states of REQ (1) to (3) and performs arbitration by a general round robin method, and outputs a bus grant signal to at least one of GRT (1) to (3). The point to do is the same as that of FIG.
However, in FIG. 2, the bus grant signal is output from the next cycle at the shortest with respect to the output of the bus request signal, whereas in FIG. 3, in the case of the present embodiment, the bus grant signal is output at the shortest. It has been two cycles since. The bus connection device outputs each bus request signal when it wants to use the bus, and monitors each bus grant signal and bus right transition signal. Bus grant signal output b
When the clock cycle 7 in which the bus right transition signal is output c is detected at the same time, the bus connection device has acquired the right to use the bus. In the present embodiment, the address data and the bus busy signal are sent from 9 after two cycles. Output d · e. Further, in the present embodiment, the arbiter stops outputting the bus grant signal to the bus connection device from 9 after 2 cycles f,
Outputs a bus grant signal to a bus connection device which should be given the right to use the bus next by arbitration.
I do. Further, the bus connection device using the bus outputs the bus right transition signal h in the last cycle of outputting the bus busy signal. Further, in FIG. 3, when the bus is in the idle state, the arbiter outputs the bus grant transition signal n simultaneously with the output m of the bus grant signal to the bus connection device. As a result, the operation sequence on the bus connection device side is the same even when the bus right transitions from the idle state.

In the present invention, regarding arbitration,
Basically, the state transition is always performed in multiple clocks. In this embodiment, the state transition is basically performed in 2 clocks. That is, in FIG. 3, for example, when a clock cycle 7 in which a certain bus grant signal is output b and a bus right transition signal is simultaneously output c is detected, the bus connection device starts addressing
The data and the bus busy signal are output d · e, and the arbiter stops outputting the bus grant signal to the bus connecting device after 9 cycles f, and the bus connecting device to which the bus use right should be given next by arbitration Output a grant signal. In this case, in the bus connection device and the arbiter, for the state detection 7 on the bus,
The output of the next state with respect to this state may be performed with respect to the next clock rising edge (8). That is, for example, for the state detected at a certain clock rising edge (7), a logical operation is performed by the next clock rising edge (8) to calculate the next state, and the next clock rising edge (9).
You can confirm it on the bus by. Therefore, even if the frequency of the bus clock becomes high, one clock cycle time can always be ensured for the logical operation, so that implementation of the arbitration protocol does not become difficult. Although the state transition is performed in two clocks in this embodiment, it can be easily understood that the state transition in three clocks or more can be basically used by using the present invention.

Next, the application of the present invention to the address / data separation type bus and another mounting method of the bus right transition signal will be described with reference to FIG. FIG. 4 is an example of a timing chart when the present invention is applied to an address / data separation type bus. REQ (1) to (3) and G in FIG.
RT (1) to RT (3) are signals similar to those in FIG.
DR is an address signal, A-STB is an address strobe signal on the control bus, DATA is a data signal, D
-STB is a data strobe signal on the control bus. In FIG. 4, the arbiter is REQ (1) to (3).
As in the case of FIG. 3, the arbitration is performed by a general round-robin method by observing the state (1) and the bus grant signal is output to at most one of the GRTs (1) to (3). When the bus connection device wants to use the bus, it outputs each bus request signal a.A and monitors each bus grant signal, address strobe signal and data strobe signal. In the address / data separation type bus of FIG. 4, when a general split transfer protocol is used, there are transfers using both address and data buses and transfers such as read requests using only the address bus.
When transferring a read request or the like using only the address bus, the bus connection device that has output the bus request signal outputs a bus grant signal B at the same time as a clock cycle 8 in which an address strobe signal is output C. When you detect it, you have acquired the right to use the bus,
In this embodiment, the address and the address strobe signal are output DE after 2 cycles. When the bus connection device that outputs the bus request signal performs a transfer using both the address and data buses, it detects the clock cycle 3 in which the bus grant signal is output b and the address strobe signal is output c at the same time. When the d clock cycle 7 in which the data strobe signal is not output at the same time or thereafter is detected, it means that the bus use right is acquired, and in this embodiment, the address, the address strobe signal, the data, and the data Strobe signal e ・ C ・
Output f / g. Further, in this embodiment, the arbiter stops outputting the bus grant signal to the bus connection device from 5 after 2 cycles after the address strobe signal is output c,
Outputs a bus grant signal to the bus connection device to which the bus use right should be given next by arbitration B
I do. Further, the bus connection device using the bus does not output the data strobe signal in the last cycle 6 for outputting the data when using the data bus. Further, in FIG. 4, when the bus is in the idle state, the arbiter outputs the address strobe signal n at the same time as the output m of the bus grant signal to the bus connection device and does not output the data strobe signal o. As a result, the operation sequence on the bus connection device side is the same even when the bus right transitions from the idle state.

Similar to FIG. 3, FIG. 4 is basically based on performing the state transition in two clocks for arbitration, and it is understood that the present invention can be applied to the address / data separation type bus. Further, in FIG. 4, the bus right transition signal is not an independent signal but is implemented using the address strobe signal and the data strobe signal, and it can be understood that the present invention can be implemented without the bus right transition signal as an independent signal.

Next, the internal structure of the arbiter according to the prior art and the present invention will be described with reference to FIG. FIG. 5 shows the internal structure of the arbiter 214 in FIG.
And (b) is a configuration according to the related art, and (c) is a configuration according to the present invention. In FIG. 5, 101 to 103 are bus request lines connected from the three bus connection devices to the arbiter 214, 111 to 113 are bus grant lines connected from the arbiter 214 to the three bus connection devices,
123 is a bus clock line, 124 is a bus right transition signal line,
Reference numerals 52 to 54 are latch circuits, and 51 is a logical operation circuit.

In the arbiter according to the conventional technique, since the state transition is performed in one clock, the state of the request signal and the bus right transition signal detected at a certain rising edge of the clock is next to the grant signal calculated by performing the logical operation. The state must be established on the bus by the next rising clock edge. Therefore, the internal configuration is such that the request signals 101 to 103 and the bus right transition signal 124 are latched by the latch circuits 52 and 53, respectively, as shown in FIG. The calculation is performed in step 51, and the signal is output as it is, or as shown in FIG.
The inputs 1 to 103 and the bus right transition signal 124 are input to the logical operation circuit 51 as they are, and the grant signal 111 is input.
To 113, the next state is calculated, and the calculation result is latched by the latch circuit 54 and output. In this case, in any case, if the bus operation clock becomes faster, it becomes difficult to secure the operation time of the logical operation circuit 51.

On the other hand, in the arbiter according to the present invention,
In order to perform the state transition in a plurality of clocks, for example, when performing the state transition in two clocks, a logical operation is performed by the next clock rising edge for the state of the request signal and the bus right transition signal detected by a certain clock rising edge. The next state of the grant signal may be calculated and determined on the bus by the next rising edge of the clock. Therefore, the internal structure of the request signal 101 is as shown in FIG.
Through 103 and the bus right transition signal 124 by the latch circuits 52 and 53, respectively, and then the grant signal 111
To the next state of 113 to 113 by the logical operation circuit 51,
The calculation result can be latched by the latch circuit 54 and output. Therefore, even if the frequency of the bus clock becomes high, one clock cycle time can always be ensured for the logical operation, so that implementation of the arbitration protocol does not become difficult.

[0024]

As described above, according to the present invention, it is possible to always perform a state transition with a plurality of clocks in arbitration, and it is not difficult to implement an arbitration protocol even when the frequency of a bus clock becomes high. .

Further, according to the present invention, the transition timing of the bus right can be indicated in accordance with the arbitration in which the bus connection device performs the state transition in a plurality of clocks, and the bus throughput can be reduced in a plurality of clocks without reducing the transfer throughput of the bus. State transition can be performed.

Further, according to the present invention, the arbiter outputs the bus right transition signal when the bus right is changed from the idle state of the bus, so that the bus connecting device can always change the bus right in the same sequence operation. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a bus system using an arbitration method according to the present invention.

FIG. 2 is a timing chart of arbitration according to the related art.

FIG. 3 is a timing chart of arbitration of an address / data multiplexed bus according to the present invention.

FIG. 4 is a timing chart of arbitration of the address / data separation type bus according to the present invention.

FIG. 5 is a state transition diagram showing an example of the internal configuration of an arbiter according to the related art and the present invention.

[Explanation of symbols]

211-213 ... Bus connection device, 214 ... Arbiter, 101-103 ... Bus request line, 111-11
3 ... Bus grant line, 121 ... Address / data bus,
122 ... control bus, 215 ... clock generator,
123 ... Bus clock line, 124 ... Bus right transition signal line,
52 to 54 ... Latch circuit, 51 ... Logical operation circuit.

Claims (6)

[Claims] 1. An arbitration method for a clock-synchronized information processing device bus, wherein a state transition of a signal output on the bus is always performed in a plurality of clocks. 2. The bus control signal according to claim 1,
An arbitration method in which a bus connection device using a bus provides a bus right transition signal indicating a bus right transition timing. 3. The arbitration method according to claim 2, wherein the arbiter outputs a bus right transition signal when the bus right transitions from the idle state of the bus. 4. In the arbiter of the clock synchronous information processing device bus, regarding the state of the signal output on the bus,
An arbiter characterized by performing arbitration by a method that constantly performs state transitions with multiple clocks. 5. The bus control signal according to claim 4,
An arbiter that performs bus arbitration by a method in which a bus-connected device that uses the bus uses a bus right transition signal that indicates a bus right transition timing. 6. The arbiter according to claim 5, wherein the arbiter outputs a bus right transition signal when the bus right changes from an idle state of the bus.