JPH0946350A - Physical loop-back control circuit and atm exchange - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain execution of physical loop-back by simple circuit constitution without generating an abnormal cell. SOLUTION: A loop-back start instruction from a CPU 5 is temporarily stored in an instruction register 33 and an instruction storing signal is applied to a synchronization control part 32. The control part 32 generates a physical loop signal from the instruction storing signal by the use of a synchronizing signal synchronous with an up input cell signal and applies the generated signal to a physical loop selector 31. The selector 31 selectively outputs a cell signal inputted from a down input line and the synchronizing signal based upon the physical loop signal and starts physical loop-back operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a physical loopback control circuit and an ATM (asynchronous transfer mode) switch, and more particularly to a physical loopback.

[0002]

2. Description of the Related Art Generally, loopback processing of an ATM switch is performed in an ATM layer processing circuit portion as shown in FIG. 2, and a cell flow as shown in loop 1 of FIG. By folding back, the faulty part can be isolated.

In a line using an ATM network, an up line and a down line are usually composed of a pair. An ATM layer processing circuit for performing the ATM layer processing is provided for each of the upstream and the downstream, and the processing is performed independently. Also, these ATM cell streams are
AT for identifying the beginning of M cell data and ATM cells
It is composed of an M cell synchronization signal (SYNC).

Further, the phase relationship between these upstream and downstream ATM cells is generally not fixed. Conventionally, in this physical loopback, the instruction holding signal in which the instruction from the CPU or the microprocessor is held in the instruction holding register R is directly used as the select signal of the physical loop selector S as shown in FIG. Signal and ATM
I was looping back the cell.

[0005]

However, when the physical loopback start start command or the loopback end command is issued in the above-mentioned conventional configuration, as shown in the timing chart of FIG. First ATM
At the time point A of the ATM cell data until the cell synchronization signal arrives, that is, the upstream output ATM cell flow, the ATM cells are interrupted, and the upstream ATM cell flow is formed and transmitted as abnormal data.

Further, the first AT after the end command is issued
ATM cell data until the M cell synchronization signal arrives, that is,
At the time of the upstream output ATM cell flow, the ATM cell was interrupted and was transmitted to the upstream ATM flow as abnormal data.

When these abnormal data are sent to the upstream output line, the abnormal cell data is detected at the receiving point (for example, the terminal device) of the loopback signal in the subsequent stage, and the error is recognized. It was

From the above, a physical loopback control circuit and an ATM switch which can realize a circuit in which an abnormal cell as described above does not occur when a physical loopback is performed with a simple structure. Offer is requested.

[0009]

Therefore, according to the present invention, a "physical loopback control signal" is used to combine a cell signal from an uplink input line with a synchronization signal A synchronized with this cell signal, or a downlink input line. "Physical loop select means" for selectively outputting any one of a set signal of the cell signal from the above and the synchronizing signal B synchronized with this cell signal to the up output line or the down output line, and the above physical loopback control signal. In the "physical loopback control circuit" including the "control means" provided to the "physical loop select means", the above-mentioned problems are solved by the following characteristic configurations.

That is, in the present invention, the "control means" is provided with "first physical loopback control means" for controlling the physical loopback from the downlink input line to the uplink output line. "Physical loopback control means" fetches the synchronization signal A from the uplink input line and the synchronization signal B from the downlink input line, and inquires of the "physical loop select means" from the downlink input line. When the cell signal / synchronization signal B is selectively output to the uplink output line to perform physical loopback to the uplink output line, the synchronization signal A is used to generate the physical loopback control signal. Then, the "physical loop selection means" is caused to selectively output the cell signal / synchronization signal A from the uplink input line to the uplink output line, and the cell signal / sync signal B from the downlink input line is output. When releasing the physical loopback to the upstream output line, the synchronization signal B is used to generate the physical loopback control signal.

[0011]

According to the above-mentioned structure of the present invention, the first physical loopback control means is provided for performing the physical loopback from the downlink input line to the uplink input line without generating an abnormal cell. The first physical loopback control means takes in the synchronization signal A synchronized with the cell signal from the uplink input line and the synchronization signal B synchronized with the cell signal from the downlink input line, and outputs the cell signal from the downlink input line. When performing the physical loopback of the synchronizing signal B to the upstream output line, the physical loopback control signal is generated by using the synchronizing signal A synchronized with the cell signal of the upstream input line and given to the physical loop selecting means.

As a result, the physical loop selection means uses the synchronization signal A synchronized with the cell signal of the uplink input line in the switching selection output from the cell signal from the uplink input line to the cell signal of the downlink input line. Therefore, the cell signal is not cut off in the middle of the cell signal from the uplink input line as in the prior art, and the cell signal from the downlink input line is immediately output after the cell signal for one cell is output from the physical loop select means. It is possible to selectively output to the upstream output line.

Further, after starting the physical loopback of the cell / sync signal B of the downlink input line to the uplink output line, this physical loopback is released and the cell signal / sync signal of the uplink input line is selectively output to the uplink output line. To return to
By generating the physical loopback control signal by using the synchronization signal B from the downlink input line and giving it to the physical loop select means, the cell signal is changed during the selective output of the cell signal from the downlink input line as in the conventional case. Never break, 1
Immediately after the cell signal for the cells is output from the physical loop selection means, the cell signal from the upstream input line can be returned to be selectively output to the upstream output line.

Therefore, when the physical loopback is performed, an abnormal cell as in the above-described conventional case does not occur, and it can be realized with a simple circuit configuration.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention applied to an ATM exchange will be described below with reference to the drawings.

Therefore, in this embodiment, in the ATM switch, an instruction holding register section for holding a switching instruction by software processing, a selector section for selecting a normal ATM cell flow and a loopback ATM cell flow, and the above-mentioned instruction. A synchronization control unit configured to control switching of the selector unit in response to a switching instruction from the holding register unit, is synchronized with an uplink input ATM cell synchronization signal at loopback activation,
At the time of cancellation, it is configured to loop back in synchronization with the downlink input ATM cell synchronization signal.

FIG. 5 is a functional block diagram of the ATM exchange of this embodiment. The characteristic of FIG. 5 is that the ATM layer processing circuit 21 performs physical loopback.
A physical loopback circuit 21a, and a physical loopback instruction from the CPU 5 (instruction by software processing)
By this, switching control is performed so that no abnormality occurs in the ATM cell flow.

The CPU 5 is composed of a microprocessor, a program ROM, a working RAM, etc., and controls the entire inside of the ATM switch, and a physical loopback instruction (eg software processing) to the physical loopback circuit 21a. Command is generated and given.

(Specific Circuit Configuration of Physical Loopback Circuit 21a): Therefore, FIG. 1 is a specific circuit configuration diagram of the physical loopback circuit 21a. In FIG. 1, the physical loopback circuit 21a includes a physical loop selector 31, a synchronization control unit 32, and an instruction holding register 33.
It is composed of In FIG. 1, characteristically, a new synchronization control unit 32 is provided to solve the above-mentioned conventional problems.

The synchronization control unit 32 takes in the upstream synchronization signal and the downstream synchronization signal, generates an optimal timing physical loop signal by the instruction holding signal from the instruction holding register 33, and gives it to the physical loop selector 31. As a result, the physical loop selector 31 selects the downlink input cell flow and the downlink synchronization signal and outputs them as the uplink output cell flow and the uplink synchronization signal.

(Detailed functional configuration of the synchronization control unit 32):
FIG. 6 is a detailed functional configuration diagram of the synchronization control unit 32 described above. 6, the synchronization control unit 32 is composed of a switching timing selector 32a and a register 32b.

The switching timing selector 32a fetches the upstream synchronization signal and the downstream synchronization signal, selects either the upstream synchronization signal or the downstream synchronization signal according to the instruction holding signal from the instruction holding register 33, and selects this. The signal is given to the register 32b as a switching timing signal. Specifically, the register 32b is composed of a flip-flop circuit, samples the above-mentioned instruction holding signal with a switching timing signal, and gives the result to the physical loop selector 31 as a physical loop signal.

(Physical Loop Start Operation): Next, the physical loop back start operation in the above-mentioned ATM switch will be described with reference to the operation timing chart of FIG. Figure 7
(A) is an upstream input synchronization signal synchronized with the upstream input cell flow. FIG. 7B shows the upstream input cell flow. FIG. 7 (c)
Is a downlink input synchronization signal synchronized with the downlink output cell flow. FIG. 7D shows the downlink cell flow. FIG. 7E shows C
Physical loopback start instruction (software instruction) from PU5
Signal. FIG. 7F shows an instruction holding signal from the instruction holding register 33. FIG. 7G shows a switching timing signal from the switching timing selector 32a.
FIG. 7H shows a physical loop signal from the synchronization control unit 32. FIG. 7I shows an upstream output synchronization signal of the physical loop selector 31. FIG. 7 (j) shows an upstream output cell flow of the physical loop selector 31.

First, when the CPU 5 gives a physical loopback start instruction signal (FIG. 7 (e)) to the instruction holding register 33 as a pulse signal, the instruction holding register 33 outputs the instruction holding signal (FIG. 7 (f)) at a low level. From the high level to the switching timing selector 32a of the synchronization control unit 32,
It is given to the register 32b. When receiving the instruction holding signal (FIG. 7 (f)), the switching timing selector 32a switches the upstream input synchronization signal to the switching timing signal (FIG. 7).
(G)) and outputs it to the register 32b.

Further, since the instruction holding signal (FIG. 7 (f)) is given to the register 32b, the switching timing signal (FIG. 7 (g)) is replaced with the switching timing signal (FIG. 7 (g)). Is sampled to generate a physical loop signal (FIG. 7 (h)) and the physical loop selector 3
Give to 1. As a result, the physical loop selector 31
Switching from the upstream input cell flow / synchronization signal (FIGS. 7 (b) and (a)) to the downstream input cell flow / synchronization signal (FIGS. 7 (d) and (c)) is performed to select the cell flow from the downlink. The synchronization signal and the loop signal are output by looping back to the uplink (Fig. 7).
(I), (j)).

What is particularly important here is that at the timing of the upstream output cell flow in FIG.
, The physical loop selector 31 performs switching selection immediately after sending a 54-byte or 53-byte cell to the upstream output line normally based on the upstream output synchronization signal without interruption. ~~, ...
Is transmitted as an upstream output cell, the receiving side or the like cannot determine the abnormal cell data. Here, the cell in the timing chart of FIG. 7 (j) is switched and output in the middle of the regular cell, so the cell length is short, but this cell is regarded as invalid data on the receiving side. By discarding it, it is possible to avoid being judged as abnormal.

Therefore, cell A at the start of physical loopback
The length of the cell including the cell and the cell becomes long, but no problem occurs on the receiving side.

(Physical loop end operation): Next, end (release) of the physical loopback in the above-mentioned ATM switch.
The operation will be described with reference to the operation timing chart of FIG. FIG. 8A shows an upstream input synchronization signal synchronized with the upstream input cell flow. FIG. 8B shows the upstream input cell flow. FIG. 8C shows a downlink input synchronization signal synchronized with the downlink input cell flow. FIG. 8D shows the downlink input cell flow. FIG. 8E shows a physical loopback end instruction (software processing instruction) from the CPU 5. FIG. 8F shows an instruction holding signal from the instruction holding register 33. Figure 8 (g)
Is a switching timing signal from the switching timing selector 32a. FIG. 8H shows a physical loop signal from the synchronization control unit 32. FIG. 8 (i) shows an upstream output synchronization signal of the physical loop selector 31. FIG. 7 (j) shows an upstream output cell flow of the physical loop selector 31.

Therefore, after the physical loopback is started, when the loopback is finished (released) next time, the CPU 5
Gives a physical loopback end instruction signal (FIG. 8 (e)) to the instruction holding register 33 as a pulse signal, the instruction holding register 33 changes the instruction holding signal (FIG. 8 (f)) from a high level signal to a low level signal. Change the synchronization control unit 32
Switching timing selector 32a and register 32
Give to b and. The switching timing selector 32a is
When the instruction holding signal (FIG. 8 (f)) is given, the downlink input synchronizing signal is output as the switching timing signal (FIG. 8 (g)) and given to the register 32b.

Furthermore, since the instruction holding signal (FIG. 8 (f)) is given to the register 32b, the instruction holding signal (FIG. 8 (g)) is used by the switching timing signal (FIG. 8 (g)).
By sampling (f), a physical loop signal (FIG. 8 (h)) is generated and given to the physical loop selector 31. As a result, the physical loop selector 31 stops the loopback and returns from the downlink input cell flow / synchronization signal (FIGS. 8 (d) and 8 (c)) to return to the original loop. (B) / (a)) is switched and selected, and the cell flow from the uplink input line and the synchronization signal are returned so as to be output to the uplink (FIG. 8 (i),
(J)).

What is particularly important here is that at the timing of the upstream output cell flow shown in FIG. 8 (j), the upstream output cells are not interrupted on the way and have 54 bytes or 53 bytes based on the upstream output synchronization signal. Immediately after the cells are normally sent to the uplink, the physical loop selector 31 performs the switching selection and sends the cells H to L, ... From the uplink input lines as the uplink output cells. Is no longer judged. Here, since the cell H in the timing chart of FIG. 8 (j) is switched and output in the middle of the regular cell,
Although the length of the cell is short, it is possible to prevent the cell H from being judged as abnormal by discarding it as invalid data on the receiving side.

Therefore, the cell length of the cell at the end of the physical loopback and the cell H becomes long, but no problem occurs on the receiving side.

(Effects of Embodiment): According to the physical loopback control circuit and the ATM switch of the above embodiments, an abnormal cell is generated and a loopback signal is generated when a conventional physical loopback is performed. Loopback can be performed without causing the receiving side device to recognize the error.

Specifically, the physical loopback circuit 21a for controlling the physical loopback from the downlink input line to the uplink output line is provided.
a captures the sync signal from the uplink input line and the sync signal from the downlink input line, and causes the physical loop selector 31 to selectively output the cell signal / sync signal from the downlink input line to the uplink output line. When the physical loopback to the output line is performed, the physical loop signal is generated using the uplink input line synchronization signal, and the physical loop selector 3
For 1, the cell signal / synchronization signal from the uplink input line is selectively output to the uplink output line to cancel the physical loopback to the uplink output line. Since it is a configuration that generates
The cell signal is not cut off in the middle of the cell signal from the uplink input line as in the conventional case, and the cell signal from the downlink input line is output immediately after the cell signal for one cell is output from the physical loop selector 31. It is possible to selectively output to the line.

Further, even when the physical loop is terminated (released), the cell signal is not cut off in the middle of the selective output of the cell signal from the downlink input line as in the conventional case, and the cell signal for one cell is the physical loop selector. Immediately after being output from 31, the cell signal from the upstream input line can be returned to be selectively output to the upstream output line.

Therefore, it is possible to realize a physical loopback circuit and an ATM switch having a simple circuit configuration without generating an abnormal cell when a physical loopback is performed.

Further, by adopting the circuit configuration as shown in FIGS. 1 and 6, the circuit can be downsized, and the line circuit can be downsized when applied to an ATM switch. Further, it can contribute to reduction of power consumption.

(Other Embodiments): (1) In the above embodiments, the cell signal and the synchronization signal from the downlink input line are physically looped back and selectively output to the uplink output line. As described above, in the case of performing physical loopback for outputting the cell signal and the synchronization signal from the uplink input line to the downlink output line, it can be realized by adopting the configuration shown in FIG. .

That is, in FIG. 9, a physical loop selector 35 is further provided, and the synchronization control unit 32A selectively outputs the cell signal / synchronization signal A from the upstream input line to the downstream output line and the physical loop to the downstream output line. When the back is performed, the physical loopback signal C is generated by using the synchronization signal B, and the physical loop selector 35 selects the cell signal / synchronization signal B from the downlink input line to the downlink output line. When outputting and canceling the physical loopback to the downlink output line, it can be realized by using the synchronization signal A to generate a physical loopback signal and giving it to the physical loop selector 35.

(2) It is also preferable to install the above-mentioned physical loopback circuit 21a in the line circuit 4 of the ATM switch 1.

(3) Further, the above-mentioned physical loop selector 3
1. The switching timing selector 32a is specifically
It can be realized by a composite gate circuit such as an AND gate, an OR gate, and a NOT gate. In addition, the register 32
Since b can be realized by a flip-flop circuit, it is possible to easily miniaturize the circuit and make it into an LSI.

[0042]

As described above, the present invention is the "control means".
First physical loopback control means for controlling physical loopback from downlink input line to uplink output line
Takes in the sync signal A from the up input line and the sync signal B from the down input line, and sends the cell signal / sync signal B from the down input line to the "physical loop select means". When the physical loopback to the upstream output line is performed by selectively outputting to the output line, the synchronization signal A is used to generate the physical loopback control signal, and the "physical loop select means" is used. On the other hand, the cell signal / synchronization signal A from the upstream input line is selectively output to the upstream output line, and the physical loopback of the cell signal / synchronization signal B from the downstream input line to the upstream output line is released. In this case, since the physical loopback control signal is generated by using the synchronization signal B, the abnormal cell like the conventional one when the physical loopback is performed is performed. Without causing, it is possible to realize a physical loopback control circuit and the ATM switching system of the simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a functional configuration diagram of a physical loopback circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional ATM switch.

FIG. 3 is a configuration diagram of a conventional physical loopback circuit.

FIG. 4 is a timing chart of a physical loopback for explaining the problem of the conventional example.

FIG. 5 is a configuration diagram of an ATM exchange according to an embodiment.

FIG. 6 is a specific circuit configuration diagram of a synchronization control unit according to the embodiment.

FIG. 7 is an operation timing chart for starting a physical loopback according to the embodiment.

FIG. 8 is an operation timing chart of termination (cancellation) of a physical loopback according to the embodiment.

FIG. 9 is a functional configuration diagram of a physical loopback circuit of another embodiment.

[Explanation of symbols]

1 ... ATM switch, 2, 4 ... Line circuit, 3 ... ATM cell switching unit, 5 ... CPU, 21 ... ATM layer processing circuit, 21a ... Physical loopback circuit, 22 ... Physical layer processing circuit, 31 ... Physical loopback selector , 32
... Synchronization control unit, 32a ... Switching timing selector,
32b ... Register, 33 ... Instruction holding register.

Claims (4)

[Claims] 1. A physical loopback control signal for pairing a cell signal from an uplink input line and a synchronization signal A synchronized with this cell signal, or a cell signal from a downlink input line and synchronization synchronized with this cell signal. A physical loop select means for selectively outputting either one of the paired signal with the signal B to the upstream output line or the downstream output line, and a control means for generating the physical loopback control signal and giving it to the physical loop select means. In the physical loopback control circuit, the control means includes a first physical loopback control means for controlling a physical loopback from the downlink input line to the uplink output line, and the first physical loopback control means comprises: The synchronization signal A from the upstream input line and the synchronization signal B from the downstream input line are fetched, and the physical loop select operation is performed. The synchronization signal A is used when the cell signal / synchronization signal B from the downlink input line is selectively output to the upstream output line and the physical loopback to the upstream output line is performed. To generate the physical loopback control signal, and cause the physical loop select means to selectively output the cell signal / synchronization signal A from the upstream input line to the upstream output line, and to output the cell signal / synchronization signal A from the upstream input line. Cell signal
A physical loopback control circuit, wherein the physical loopback control signal is generated by using the synchronous signal B when releasing the physical loopback of the synchronous signal B to the upstream output line. 2. The physical loopback control circuit according to claim 1, wherein said control means further comprises second physical loopback control means for controlling physical loopback from the upstream input line to the downstream output line. The second physical loopback control means is provided for selectively outputting the cell signal / synchronization signal A from the uplink input line to the downlink output line to perform a physical loopback to the downlink output line. Generating the physical loopback control signal using the synchronization signal B, and causing the physical loop select means to selectively output the cell signal / synchronization signal B from the downlink input line to the downlink output line. , The cell signal from the uplink input line
A physical loopback control circuit having a configuration for generating the physical loopback control signal using the synchronization signal A when releasing the physical loopback of the synchronization signal A to the downlink output line. 3. The physical loopback control circuit according to claim 1, wherein the physical loopback control means generates and outputs a physical loopback start instruction signal and a physical loopback cancellation instruction signal, and the CPU. A switching timing selector that takes in a register for temporarily holding and outputting the output signal from the device and the synchronization signals A and B, and selectively outputs one of the synchronization signals A and B as a switching timing signal according to the output signal from the register And a flip-flop circuit that samples the output signal of the register according to the switching timing signal to generate the physical loopback signal. 4. The physical loopback according to claim 1, wherein in an ATM switch equipped with an input / output line corresponding part and an ATM cell switching part, the ATM layer processing circuit of the input / output line corresponding part has a physical loopback. An ATM switching system comprising a control circuit, wherein the physical loopback is performed by a physical loopback start command signal and a physical loopback cancellation command signal from the control means.