JPH0944472A - Arithmetic processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the use efficiency of the computing element in the interior of a processor and to improve performance by a parallel processing. SOLUTION: When an inter-memory sum of products operation detection part 12 detects an inter-memory sum of products operation, a bus switch 13 divides the part where a data memory 4 and a product sum arithmetic unit 10 are connected and the part where an ALU 14 and a register 15 are connected in a bus 8 or divides the part where a data memory 5 and the product sum arithmetic unit 10 are connected and the part where the ALU 14 and a register 16 are connected. As a result, the parallel operation of the product sum arithmetic unit 10 and the ALU 14 becomes possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in an arithmetic processing unit for digital signal processing formed on a semiconductor substrate such as a digital signal processor (hereinafter referred to as DSP), and efficiently operates a plurality of arithmetic units inside the processor. The present invention relates to an arithmetic processing device that is often used to perform parallel processing.

[0002]

2. Description of the Related Art In recent years, a DSP may employ a structure having an independent product-sum calculator separate from the ALU in order to speed up the product-sum calculation and reduce power consumption.

A conventional arithmetic processing unit of this type is shown in FIG.
This will be described with reference to FIG. In FIG. 9, 1 is an instruction memory for storing an instruction code, 2 is an instruction register for temporarily storing the instruction code read from the instruction memory 1, and 3 is an instruction decoder, which decodes the instruction code and sends various control signals to the bus 8.
Output to Data memories 4 and 5 store data, and output the data to the buses 8 and 9, respectively. 6 and 7
Is an address generator, which is the data memory 4 and 5 respectively.
Address. A product-sum calculator 10 performs a product-sum operation on the data on the buses 8 and 9 and outputs the result to the accumulator 11. Reference numeral 14 is an ALU, which performs an arithmetic logic operation on the data on the buses 8 and 9 and outputs the result to the register 15 or 16. Registers 15 and 1
6 is connected to buses 8 and 9, respectively.

Next, the operation of the conventional arithmetic processing device having the above-mentioned configuration when performing various arithmetic operations will be described. (1) Inter-memory product sum operation When performing the product sum operation on the data stored in the data memories 4 and 5, the data memory 4 first reads the data in accordance with the address designated by the address generator 6,
Output to bus 8. Similarly, the data memory 5 reads data according to the address designated by the address generator 7 and outputs the data to the bus 9. The product-sum calculator 10 multiplies the data of the buses 8 and 9 and cumulatively adds the data, and stores the result in the accumulator 11. By repeating such an operation, the product-sum operation can be performed on the series of data stored in the data memories 4 and 5. (2) Arithmetic and logical operation between memory registers When performing arithmetic and logical operation on the data stored in the data memory 4 and the data stored in the register 16, first, the data memory 4 receives an address designated by the address generator 6. Then, the data is read out and output to the bus 8. At the same time, the register 16 outputs data to the bus 9. The ALU 14 performs an arithmetic logic operation on the data on the buses 8 and 9 and stores the result in the register 15. (3) Registers arithmetic logic operation between registers When performing arithmetic logic operation on the data stored in the registers 15 and 16, the data is output from the registers 15 and 16 to the buses 8 and 9, respectively. The ALU 14 performs an arithmetic logic operation on the data on the buses 8 and 9 and stores the result in the register 15.

As described above, even in the conventional arithmetic processing device, arithmetic between memories, between memory registers, and between register registers can be flexibly performed.

[0006]

However, the above conventional arithmetic processing device has a problem that the utilization efficiency of the arithmetic unit is not high. For example, when multiply-accumulate between memories, the sum-of-products calculator is used, but the register and ALU
Was unused but unused.

The present invention solves such a conventional problem, and an object of the present invention is to provide an excellent arithmetic processing device in which a plurality of arithmetic units can be efficiently used in parallel.

[0008]

In order to achieve the above object, an arithmetic processing unit according to the present invention comprises an instruction storage means for storing an instruction code, an instruction decoder for decoding the instruction code output from the instruction storage means, A data memory and a register for storing data, a data bus connected to the data memory and the register, a first arithmetic unit for arithmetically operating on the data on the data bus, and an arithmetic operation on the data on the data bus for registering the result. A second arithmetic unit to be stored in the memory, an inter-memory arithmetic detecting means for detecting that the instruction decoded by the instruction decoder is an instruction for arithmetically operating the data in the data memory in the first arithmetic unit, and an inter-memory arithmetic detection The data bus is divided into a portion connected to the data memory and the first arithmetic unit and a portion connected to the register and the second arithmetic unit based on the detection result of the means. The first has a configuration that includes a bus switch that.

In order to achieve the above object, the arithmetic processing unit of the present invention comprises an instruction storing means for storing an instruction code,
An instruction decoder for decoding an instruction code output from the instruction storage means, a data memory and a register for storing data, a data bus connected to the data memory and the register, and a first operation for data on the data bus. An arithmetic unit, an inter-memory arithmetic operation detecting unit for detecting that the instruction decoded by the instruction decoder is an instruction for arithmetically operating the data in the data memory in the first arithmetic unit, and an address generating unit for supplying an address to the data memory. The address generator is connected to the address register and the inter-memory operation detection means, stores the address register output, and supplies the address to the data memory while incrementing or decrementing the address register and the address register are modified. It is configured to include an address calculation unit for doing so.

[0010]

With such a configuration, in the arithmetic processing unit of the present invention, the inter-memory arithmetic operation detecting means detects that the instruction is an instruction for arithmetically operating the data of the data memory by the first arithmetic unit, and By dividing the data bus by the bus switch, the inter-memory operation by the first arithmetic unit and the inter-register operation by the second arithmetic unit can be processed in parallel.

Further, in the arithmetic processing apparatus of the present invention, the address counter supplies the address to the data memory while incrementing or decrementing the address counter, so that the address arithmetic unit can perform arithmetic processing in parallel.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the arithmetic processing unit of the present invention will be described in detail below with reference to the drawings. (Embodiment 1: Corresponding to claims 1 and 2) FIG.
FIG. 10 is a block diagram showing the configuration of the arithmetic processing unit in the embodiment of the present invention, in which elements similar to those of the conventional example shown in FIG. In FIG. 1, 1 is an instruction memory as an instruction storage unit for storing an instruction code, 2 is an instruction register for temporarily storing the instruction code read from the instruction memory 1, and 3 is an instruction decoder (first program control device). , Decodes the instruction code and outputs various control signals.
Data memories 4 and 5 store data, and output the data to the buses 8 and 9, respectively. Address generators 6 and 7 supply addresses to the data memories 4 and 5, respectively. Reference numeral 10 denotes a product-sum calculation unit as a first calculation unit, which performs a product-sum calculation on the data on the buses 8 and 9.
The result is output to the accumulator 11. Reference numeral 12 denotes an inter-memory product-sum operation detection unit as an inter-memory operation detection means,
According to the instruction decoded by the instruction decoder 3, the data memory 4
It is detected that the product-sum calculation unit 10 performs the product-sum calculation on the data stored in 5 and 5. Reference numeral 13 denotes a bus switch as a first bus switch, which connects the data memory 4 and the product-sum calculator 10 on the bus 8 when the memory-memory product-sum calculation detector 12 detects the memory-memory product-sum calculation. The part connected to the ALU 14 and the register 15 described later is divided, and the part connected to the data memory 5 and the product-sum calculator 10 on the bus 9 is connected to the ALU 14 and the register 16 described later. And divide the part. 14 is A as the second arithmetic unit
It is an LU and performs an arithmetic logic operation on the data of the buses 8 and 9 and outputs the result to the register 15 or 16. Registers 15 and 16 are connected to buses 8 and 9, respectively. A sequence control unit 25 is connected to the instruction decoder 3 and the inter-memory product-sum operation detection unit 12 and outputs a control signal for instructing repeated execution of the product-sum operation.

Next, in the configuration of the present embodiment, an operation for simultaneously executing an arithmetic and logical operation between registers in parallel with an inter-memory product sum operation will be described with reference to FIG.
An inter-memory product sum operation instruction is input from the instruction memory 1 to the instruction decoder 3 via the instruction register 2. The instruction decoder 3 outputs a control signal instructing an inter-memory product sum operation to each unit. The address generators 6 and 7 generate an address in which the data of the product-sum operation target is stored and supply it to the data memories 4 and 5, respectively. Data memory 4 and 5
Outputs the product-sum operation target data to the buses 8 and 9, respectively. The product-sum calculator 10 inputs the data on the buses 8 and 9 to perform a product-sum calculation, and outputs the result to the accumulator 11. The sequence control unit 25 uses the address generators 6 and 7, the data memories 4 and 5, and the product-sum calculator 1 so that the product-sum calculation as described above is executed a predetermined number of times.
0 and accumulator 11 are controlled.

On the other hand, the inter-memory product-sum operation detecting section 12 which has detected the control signal instructing the inter-memory product sum operation from the instruction decoder 3 instructs the bus switch 13 to divide the bus 8 and the bus 9. The buses 8 and 9 are divided at the position of the bus switch 13. Therefore, the inter-register arithmetic logic operation instruction is read from the instruction memory 1 via the instruction register 2 and input to the instruction decoder 3. The instruction decoder 3 in turn outputs a control signal instructing the arithmetic logic operation between registers. Then from registers 15 and 16 to bus 8 respectively
And the data is output to the bus 9. ALU14 is bus 8
And an arithmetic logic operation of the data on the bus 9 and output the result to the register 15.

In this way, the inter-memory product-sum operation and the inter-register arithmetic logic operation are executed in parallel. At this time, since the buses 8 and 9 are divided at the position of the bus switch 13 as described above, the data output from the data memories 4 and 5 and the data output from the registers 15 and 16 may collide with each other. There is no.

As described above, in the present embodiment, when the inter-memory product-sum operation detection unit 12 detects the inter-memory product-sum operation, the bus switch 13 connects the bus 8 and the data memory 4 to each other.
And the part to which the product-sum calculator 10 is connected and the ALU1
4 and register 15 are connected to each other, and the bus 9 is divided into a data memory 5 and a product-sum calculator 1
0 is connected to ALU14 and register 1
6 is connected to the connected portion, the data output from the data memories 4 and 5 and the data output from the registers 15 and 16 do not collide with each other, and the product-sum calculation between the data memories and the register The arithmetic logic operations of can be executed in parallel. Therefore, the arithmetic processing unit according to the present embodiment can improve the efficiency of use of the arithmetic unit, can execute the predetermined processing in a short time, and can execute the processing at a low operating frequency so that it can be executed with low power consumption. Has the effect.

Example 2 (corresponding to claims 3 and 8) Next,
A second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a schematic block diagram of an arithmetic processing unit according to the second embodiment of the present invention, and the same elements as those in the first embodiment are designated by the same reference numerals. In FIG. 2, reference numerals 17 and 18 denote CPU registers forming the first CPU register file, which are connected to the buses 8 and 9 and the output of the ALU 14, respectively. Reference numeral 19 denotes a bus switch as a second bus switch, which is connected to the inter-memory product-sum operation detection unit 12 and a CPU bus 20 described later. Reference numeral 21 denotes a CPU memory, which is connected to the CPU bus 20 and stores instructions and data necessary for CPU processing. Reference numeral 22 denotes a CPU control unit (second program control device), which outputs a control signal necessary for CPU processing when the memory-memory product-sum calculation processing unit 12 indicates that the memory-memory product-sum calculation is being executed. Output. A CPU processing unit 24 is controlled by the CPU control unit 22 when performing CPU processing. The other constituent elements are the same as those in the first embodiment, and the description thereof will be omitted.

Next, in the configuration of the present embodiment, the operation when the CPU processing is simultaneously executed in parallel with the inter-memory product sum operation will be described with reference to FIG. An inter-memory multiply-accumulate operation instruction from the instruction memory 1 passes through the instruction register 2,
It is input to the instruction decoder 3. The instruction decoder 3 outputs a control signal instructing an inter-memory product sum operation to each unit. The address generators 6 and 7 generate an address in which the data to be subjected to the sum-of-products operation are stored, respectively
And supply to 5. The data memories 4 and 5 output the data of the product sum operation target to the buses 8 and 9, respectively. The product-sum calculator 10 inputs the data on the buses 8 and 9 to perform a product-sum calculation, and outputs the result to the accumulator 11. The sequence controller 25 controls the address generators 6 and 7, the data memories 4 and 5, the product-sum calculator 10 and the accumulator 11 so that the product-sum calculation is executed a predetermined number of times as described above. To do.

On the other hand, the inter-memory product-sum operation detecting section 12 which has detected the control signal instructing the inter-memory product-sum operation from the instruction decoder 3 instructs the bus switch 13 to divide the bus 8 and the bus 9. The buses 8 and 9 are divided at the position of the bus switch 13. With the bus 8 and the bus 9 divided at the position of the bus switch 13, the CPU processing unit 24
Performs CPU processing under the control of the CPU control unit 22.

The inter-memory product-sum operation detection unit 12 outputs the inter-memory product-sum operation detection result to the CPU control unit 22 and instructs the bus switch 19 to connect the bus 8 or the bus 9 and the CPU bus 20. . When transferring data between the CPU memory 21 and the CPU register 17,
The bus 8 and the CPU bus 20 are connected. CPU memory 2
When data is transferred between 1 and the CPU register 18, the bus 9 and the CPU bus 20 are connected. When operating on the data transferred from the CPU memory 21 to the CPU registers 17 and 18, the CPU registers 17 and 18
To output data to buses 8 and 9, respectively. ALU
14 performs arithmetic and logic operations on the data on the buses 8 and 9 and outputs the result to the CPU register 17.

In this way, the product-sum operation between memories and the CP
U processing is executed in parallel. At this time, since the buses 8 and 9 are divided at the position of the bus switch 13 as described above, the data output from the data memories 4 and 5 and the data output from the registers 17 and 18 and the CPU bus 20 are divided. Do not collide.

As described above, in the present embodiment, when the inter-memory product-sum operation detector 12 detects the inter-memory product-sum operation, the bus switch 13 connects the bus 8 and the data memory 4
And the part to which the product-sum calculator 10 is connected and the ALU1
4 and the portion to which the CPU register 17 is connected, and the bus 9 is connected to the portion to which the data memory 5 and the product-sum calculator 10 are connected, the ALU 14 and the CPU.
Since it is divided into the part to which the register 18 is connected,
The data sum output between the data memories and the CPU processing can be executed in parallel without the data output from the CPU registers 17 and 18 colliding with the data output from the data memories 4 and 5. CPU memory 21 and CPU
Data transfer with the registers 17 and 18 becomes possible.

Therefore, the arithmetic processing unit of this embodiment is
Since the DSP processing and the CPU processing can be processed in parallel by the common arithmetic unit, the use efficiency of the arithmetic unit is improved, the predetermined processing can be executed in a short time, and the operating frequency is low. Since it can be executed, it has an effect that it can be executed with low power consumption. ALU14 to C
ALU dedicated to the CPU by also serving as the PU processing unit
Since there is no need to install the device, there is an effect that the chip size of the LSI can be reduced and the cost can be reduced.

(Third Embodiment: Corresponding to Claim 4) Next, a third embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a schematic block diagram of an arithmetic processing unit according to the third embodiment of the present invention, and the same elements as those in the first embodiment are designated by the same reference numerals. FIG. 4 is a schematic block diagram of the address generator 6 in FIG. In FIG. 4, 601
Is an address register, which is connected to the bus 8 and the input and output of an address ALU 603 described later. Reference numeral 602 denotes an increment register, which is a bus 8 and an address ALU described later.
It is connected to the input and output of 603. An address ALU 603 calculates the value of the address register 601 and the value of the increment register 602, and stores the result in the address register 601. An address counter 604 stores the output of the address register 601, supplies the address to the data memory 4, and increments or decrements according to an instruction from the sequence control unit 25. Reference numeral 60 is an address calculation unit for modifying the address register 601, and is composed of an address register 601, an increment register 602, and an address ALU 603.

Next, in the configuration of this embodiment, the operation of performing the address operation in the address operation unit 605 in parallel with the inter-memory product sum operation will be described with reference to FIGS. 3 and 4. An inter-memory product sum operation instruction is input from the instruction memory 1 to the instruction decoder 3 via the instruction register 2. The instruction decoder 3 outputs a control signal instructing an inter-memory product sum operation. The address generators 6 and 7 generate an address in which the data of the product-sum operation target is stored and supply it to the data memories 4 and 5, respectively. At this time, the address generator 6
Then, the initial address is loaded from the address register 601 in FIG. 4 to the address counter 604 and output to the data memory 4. The data memories 4 and 5 output the data of the product sum operation target to the buses 8 and 9, respectively.
The product-sum calculator 10 inputs the data on the buses 8 and 9 to perform a product-sum calculation, and outputs the result to the accumulator 11. The sequence controller 25 controls the address generators 6 and 7, the data memories 4 and 5, the product-sum calculator 10 and the accumulator 11 so that the product-sum calculation as described above is executed a predetermined number of times. To do.

On the other hand, in the address generator 6, the address counter 60 is instructed by the sequence controller 25.
4 sequentially supplies the address to the data memory 4 while incrementing or decrementing the value initially loaded from the address register 601. Therefore,
In parallel with this, the address calculation unit 60 can perform another address calculation. That is, the address register 60
The addition of the address value stored in 1 and the modification value stored in the increment register 602 is added to the address ALU 603.
Then, the result is stored in the address register 601.

As described above, in the present embodiment, the address counter 604 in the address generator 6 independently supplies the address required for the product-sum operation to the data memory 4 when the memory-memory product-sum operation is executed. In parallel with this, the address calculation unit 601 can perform an address calculation for updating the value of the address register 601, which has the advantages that the utilization efficiency of the address ALU 603 is increased and the processing can be performed at high speed.

In the present embodiment, if the address generator 7 is also constructed in the same manner as the address generator 6 shown in FIG. 4, the same effect can be obtained in the address generator 7.

The address calculation unit 605 shown in FIG.
Although a simple structure is shown in FIG. 6 for the sake of simplicity, various design changes such as increasing the number of address registers are possible.

(Example 4: Corresponding to claims 5 and 9) Next,
A fourth embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a schematic block diagram of an arithmetic processing unit according to the fourth embodiment of the present invention, and the same elements as those in the first embodiment are designated by the same reference numerals. FIG. 6 is a schematic block diagram of the address generator 600 in FIG. In FIG. 6, reference numerals 601 to 604 are the same as those in the third embodiment of FIG. Also 601 to 60
The same applies to the case where the address calculation unit 60 is configured by 3. Reference numerals 605 and 606 are CPU registers forming the second CPU register file. Reference numeral 607 denotes a second CPU processing unit, which has the addresses ALU 603 and C described above.
CPU including PU registers 605 and 606
It is controlled by the CPU controller 22 when processing is performed.

Next, in the configuration of the present embodiment, the operation of simultaneously executing the CPU processing in parallel with the inter-memory product sum operation will be described with reference to FIGS. The operation of the CPU processing in the first CPU processing unit 24 is the same as that of the second embodiment described with reference to FIG. In this embodiment,
Further, an operation of performing CPU processing in parallel in the second CPU processing unit 607 shown in FIG. 6 will be described. When performing the memory sum-of-products calculation, the address counter 604 sequentially supplies the addresses to the data memory 4 while incrementing or decrementing the initial address initially loaded from the address register 601 under the control of the sequence controller 25. The second CPU processing unit 607 is controlled by the CPU control unit 22 in parallel with this to perform the CPU processing. That is, the address ALU 603 performs arithmetic logic operation on the data stored in the CPU registers 605 and 606, and stores the result in the CPU register 605. Data transfer between the CPU registers 605 and 606 and the CPU memory 21 can be performed via the CPU bus 20, the bus switch 19 and the bus 8.

As described above, in the present embodiment, not only the CPU processing can be executed by the ALU 14 in parallel during the execution of the product sum calculation between memories, but also the CPU processing can be executed in parallel by the address ALU 603 in the address generator 600. It can be carried out. Thus, for example, while the CPU address calculation is being performed by the second CPU processing unit 607, the CPU
The data processing can be performed in parallel by the first CPU processing unit 24. Further, since the address ALU 603 is also used as the CPU processing unit, it is not necessary to install an ALU dedicated to the CPU, so that the chip size of the LSI can be reduced and the cost can be reduced.

In the address generator 600, as shown in FIG. 8, the CPU registers 605 and 606 are not the bus 8 but the
By connecting to the CPU bus 20, the parallelism of processing can be further increased. Because the first CPU
In the processing unit 24, while the bus 8 is being used to perform calculations on the CPU register 17, the CPU
This is because data can be transferred from the CPU memory 21 to the second CPU processing unit 607 via the bus 20.

(Fifth Embodiment: Corresponding to Claims 6 and 7)
A fifth embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a schematic block diagram of an arithmetic processing unit according to the fifth embodiment of the present invention. In FIG. 7, 1 to 5 and 7 to 16 and 25 are the same as those in the first embodiment shown in FIG. A memory access detector 23 detects whether the instruction decoded by the instruction decoder 3 is an instruction to access the data memory 4. Reference numeral 800 is an address generator, which is configured as shown in FIG.
In FIG. 8, reference numerals 601 to 606 are the same as those in the fourth embodiment.
Is the same as The same applies to that the address calculation unit 60 is composed of 601 to 603. The difference from FIG. 6 is that the CPU as the second CPU register file
Registers 605 and 606 are CPU bus 2 instead of bus 8.
It is connected to 0. Reference numeral 801 constitutes a second CPU processing section.

In the arithmetic processing device configured as described above, the operation for performing the inter-register operation using the ALU 14 and the registers 15 and 16 in parallel with the inter-memory product sum operation is the first operation.
This is the same as the embodiment. The operation of performing CPU processing using the second CPU processing unit 801 in parallel with the inter-memory product sum operation is the same as in the case of the fourth embodiment. In the present embodiment, further, the second CPU processing unit 801 is operated in parallel with an operation that does not use the data memory 4, that is, an arithmetic logical operation using the ALU 14 for the data of the data memory 5 and the data of the register 15, for example. The operation of performing CPU processing by using will be described. First, an instruction instructing the arithmetic logic operation as described above is input from the instruction memory 1 to the instruction decoder 3 via the instruction register 2. The inter-memory product sum operation detection unit 12 puts the bus switch 13 into a state in which the buses 8 and 9 are not divided. The data read from the data memory 5 is input to the ALU 14 via the bus 9. The data in the register 15 is input to the ALU 14 via the bus 8. The ALU 14 performs arithmetic logic operation on the above two data and stores the result in the register 16. At this time, since the memory access detection unit 23 does not detect the memory access to the data memory 4, the CPU control unit 2
2 becomes a state in which the second CPU processing unit 801 in FIG. 8 can be controlled. That is, for example, the CPU register 60
The data of 5 and 606 are added by the address ALU 603, and the result is stored in the CPU register 605. Alternatively, via the CPU bus 20, the CPU memory 21 and C
Data is transferred between the PU registers 606.

As described above, the arithmetic processing unit according to the present embodiment can perform the inter-register operation using the ALU 14 and the registers 15 and 16 in parallel with the inter-memory product sum operation. In parallel with the above, CPU processing can be performed using the second CPU processing unit 801, and in addition, the memory access detection unit 23 detects whether or not the data memory 4 is accessed, so that the data memory 4 can be accessed. The CPU processing can be performed by using the second CPU processing unit 801 in parallel with the execution of the non-instruction. Therefore, the address generator 800
It is possible to further improve the use efficiency of the address ALU 603 in FIG. Also the address AL
By using U603 as the CPU processing unit,
Since there is no need to install a dedicated ALU, there is an effect that the chip size of the LSI can be reduced and the cost can be reduced.

In this embodiment, if the address generator 7 has the same structure as the address generator 800, the address generator 7 can obtain the same effect.

In the above five embodiments, the address generating unit of the data memory is also used as the CPU processing unit, but the instruction memory address generating unit (not shown) is also used as the CPU processing unit. You may.

[0039]

As is apparent from the above description, the arithmetic processing unit of the present invention can improve the efficiency of use of arithmetic units to achieve high speed by parallel processing, and can be integrated with a CPU to form an LSI. In this case, since the arithmetic unit can be shared, the chip area can be reduced and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an arithmetic processing unit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an arithmetic processing unit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of an arithmetic processing unit according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of an address generator in a third embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of an arithmetic processing unit according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of an address generator in a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of an arithmetic processing unit according to a fifth embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of an address generator in a fifth embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of an arithmetic processing unit in a conventional example.

[Explanation of symbols]

1 Instruction Memory 2 Instruction Register 3 Instruction Decoder (First Program Control Unit) 4, 5 Data Memory 6, 7 Address Generator 8, 9 Bus 10 Sum of Products Calculator 11 Accumulator 12 Memory Sum of Products Calculation Detecting Unit 13 1st Bus switch 14 ALU 15, 16 registers 17, 18 CPU register (first CPU register file) 19 second bus switch 20 CPU bus 21 CPU memory 22 CPU controller (second program controller) 23 memory access detection Unit 24 CPU processing unit 25 sequence control unit 60 address calculation unit 600 address generation unit 601 address register 604 address counter 605, 606 CPU register (second CPU register file)

Claims (9)

[Claims] 1. An instruction storage means for storing an instruction code,
An instruction decoder that decodes the instruction code output from the instruction storage unit, a data memory and a register that stores data, an address generator that supplies an address to the data memory, and data connected to the data memory and the register. A bus, a first arithmetic unit that operates on the data of the data bus, a second arithmetic unit that operates on the data of the data bus and stores the result in the register, and the instruction decoder decodes The inter-memory operation detecting means for detecting that the instruction is an instruction to operate on the data of the data memory by the first arithmetic unit, and the data bus based on the detection result of the inter-memory operation detecting means. It is divided into a portion to which the data memory and the first arithmetic unit are connected and a portion to which the register and the second arithmetic unit are connected. First arithmetic processing unit and a bus switch. 2. The arithmetic processing unit according to claim 1, further comprising a product-sum arithmetic unit as a first arithmetic unit and an ALU as a second arithmetic unit. 3. A CPU for storing instructions and data of the CPU
The memory, the CPU bus connected to the CPU memory, and the C based on the detection result of the inter-memory operation detecting means.
A second bus switch connecting the PU bus and the data bus, a first CPU register file connected to the data bus and the output of the second arithmetic unit, and at least the first CPU register file connected to the inter-memory arithmetic operation detecting means. The arithmetic processing unit according to claim 1 or 2, further comprising a CPU register file and a CPU control unit for controlling the second arithmetic unit. 4. An instruction storage means for storing an instruction code,
An instruction decoder that decodes the instruction code output from the instruction storage unit, a data memory and a register that stores data, an address generator that supplies an address to the data memory, and data connected to the data memory and the register. A bus, a first arithmetic unit that operates on the data of the data bus, and an instruction decoded by the instruction decoder is an instruction that operates on the data of the data memory by the first arithmetic unit. An inter-memory operation detecting means for detecting, the address generating section stores an address register, an output of the address register, an address counter for supplying an address to the data memory while incrementing or decrementing, and the address. An operation including a register and an address operation unit for modifying the register Management apparatus. 5. An address register, an address counter that stores an output of the address register and supplies an address to a data memory while incrementing or decrementing the address register, and an address operation unit that includes the address register and modifies the address register. 3. An address generator having a second CPU register file connected to the input and output of the address calculator.
Or the arithmetic processing unit according to 3. 6. A memory access detection means for detecting that the instruction decoded by the instruction decoder is an instruction for accessing data in a data memory, a CPU memory for storing CPU instructions and data, and a CPU memory connected to the CPU memory. And a CPU control unit connected to the memory access detection unit and the inter-memory operation detection unit to control the address generation unit, the address generation unit storing an address register and an output of the address register. And an address counter that supplies an address to the data memory while incrementing or decrementing,
3. The address arithmetic unit including the address register for modifying the address register, the input / output of the address arithmetic unit, and a second CPU register file connected to the CPU bus. Processing unit. 7. An instruction storage means for storing an instruction code,
An instruction decoder that decodes an instruction code output from the instruction storage unit, a data memory and a register that stores data, a data bus connected to the data memory and the register, and an operation on the data of the data bus. A first arithmetic unit, memory access detection means for detecting that the instruction decoded by the instruction decoder is an instruction for accessing data in the data memory, an address register for supplying an address to the data memory, and the address An address arithmetic unit including a register for modifying the CPU, a CPU memory for storing CPU instructions and data, a CPU bus connected to the CPU memory, an input / output of the address arithmetic unit and the CPU bus. Second CPU register file connected, and the memory access detection means Preliminary the arithmetic processing device and a CPU control unit connected to the memory operation between the detection means for controlling at least said second CPU register file and the address calculation unit. 8. A data memory for storing data, a data bus connected to the data memory, an arithmetic unit including a multiplier connected to the data bus, and an arithmetic logic operation unit connected to the data bus. An arithmetic processing unit for digital signal processing formed on a semiconductor substrate comprising: a first program control unit for controlling the arithmetic processing unit; and the first program control unit including the arithmetic logic operation. Controlling means for controlling whether to use the unit, and controlling the arithmetic logic operation unit when the detection means indicates that the first program controller does not use the arithmetic logic operation unit An arithmetic processing unit equipped with a second program control unit to be used as described above. 9. A data memory for storing data, an address generator having an address calculator for supplying an address to the data memory, a data bus connected to the data memory, and a data bus connected to the data bus. An arithmetic processing unit for digital signal processing, which is formed on a semiconductor substrate and includes an arithmetic unit including a multiplier and an arithmetic logic operation unit connected to the data bus, the arithmetic processing unit controlling the arithmetic processing unit. No. 1 program control device, detection means for detecting whether or not the first program control device controls and uses the address arithmetic unit, and the detection unit is the first program control device for the address arithmetic unit. An arithmetic processing unit comprising a second program control unit for controlling and using the address arithmetic unit when it is indicated that is not used.