JPH0944463A - Data transfer controller and data transfer method using this - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of instruction and the number of times of interruption and to improve data transfer processing performance. SOLUTION: This controller is provided with first transfer instruction storage means 52 and second transfer instruction storage means 53 separating transfer instructions and storing these instructions when the decoding results of an instruction decoding means 51 are designated instruction classifications, a shared memory access means 55 performing the writing/reading of data for the shared memory 3 within the cluster to which data belongs, taking the synchronization from the first and second transfer instruction storage means 52 and 53 for every data transfer processor, an extension memory access means 57 performing the data reading/writing in the extension memory 7 within the cluster to which data belongs and a data transfer means 56 performing a data transfer via a local network 14 and an intercluster network 6. Thus, the data transfer between the extension memory 7 and the shared memory 3 which are divided into two instructions is made into an instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device and a data transfer control method for controlling data transfer in an information processing system for transferring data from an extended memory of a certain cluster to a shared memory of another cluster.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration example of an information processing system using a conventional data transfer control device.

Referring to FIG. 3, the conventional information processing system comprises a plurality of clusters 1 and an inter-cluster network 6, and the cluster 1 is shared by a plurality of arithmetic processing units 2 and these arithmetic processing units 2. It is located between the shared memory 3, the local network 4 having an interface between the plurality of processing units 2 and the shared memory 3, the local network 4 and the cluster network 6, and the extended memory 7 of its own cluster and the sharing of other clusters. The data transfer control device 50 controls transfer of data to and from the memory.

The data transfer control device 50 decodes the instruction storage means 520 for storing the transfer instruction sent from the arithmetic processing device 2 in its own cluster and the transfer instruction read from this instruction storage means 520. Instruction decoding means 510
Via the shared memory access means 550 for writing / reading to / from the shared memory 3 of its own cluster, the extended memory access means 570 for writing / reading to / from the extended memory 7 of its own cluster, and the inter-cluster network 6. Data transfer means 560 for transferring data
And a transfer control means 540 for controlling the shared memory access means 550 and the data transfer means 560 according to an instruction from the instruction decoding means 510.

Next, in the information processing system using the conventional data transfer control device thus configured, the operation of transferring data from the extended memory of the self cluster to the shared memory of another cluster will be described.

First, the instruction storage means 520 of the data transfer control device 50 receives a data transfer instruction from the expansion processor 7 of the own cluster to the shared memory 3 of the own cluster from the arithmetic processing unit 2 in the own cluster. Then, the instruction decoding unit 510 reads the transfer instruction from the instruction storage unit 520 and decodes the instruction content. The transfer control means 540 reads out the extended memory 7 data of its own cluster via the instruction decoding means 510, receives the information of the start address and the transfer length, and sends the extended memory 7 to the extended memory access means 570 for each data transfer processing unit. Issue a read instruction. The extended memory access unit 570 transfers the data read from the extended memory 7 to the data transfer unit 560, and
The completion of reading is notified to the transfer control means 540.

Then, the transfer control means 540 issues a write instruction to the shared memory 3 to the shared memory access means 550 and sends it to the local network 4 together with the data already passed to the data transfer means 560 (at this time). , Cluster identifier, write address to shared memory, and transfer length are added). The local network 4 writes data to the shared memory 3 according to this instruction. After that, the end interrupt of the instruction is issued to the arithmetic processing unit 2 in the own cluster.

Next, the instruction storage unit 520 receives a data transfer instruction from the shared memory 3 of its own cluster to the shared memory of another cluster from the arithmetic processing unit 2 in its own cluster. The instruction decoding unit 510 reads the transfer instruction from the instruction storage unit 520 and decodes the content of the instruction. The transfer control unit 540 reads the shared memory 3 of its own cluster from the instruction decoding unit 510, receives the information of the start address and the transfer length, and instructs the shared memory access unit 550 to read the shared memory 3 for each data transfer processing unit. Give out. As a result, the shared memory access unit 550 transfers the data read from the shared memory 3 to the data transfer unit 56.
0, and at the same time read completion is read by the transfer control means 540.
To notify.

Next, the transfer control means 540 issues an instruction to the data transfer means 560 to send the data sent from the shared memory access means 550 to the data transfer means 560 to the inter-cluster network 6. At this time, a cluster identifier, a write address to another cluster, a transfer length, and an operation instruction to the data transfer control device of another cluster are added. Then, the inter-cluster network 6 transfers these received data to the data transfer control device of another cluster indicated by the cluster identifier according to this instruction.

The data transfer control device of another cluster separates the additional information from the data received by the data transfer means and transfers it to the transfer control means. The transfer control means instructs the data transfer means and the shared memory means to write the data in the data transfer means to the shared memory based on the additional information. The data transfer means reads the write data according to this instruction and passes it to the shared memory access means. The shared memory access means writes the write data sent from the data transfer means into the shared memory. After that, an instruction end interrupt is issued to the arithmetic processing unit 2.

[0011]

In this conventional data transfer control device, when data is transferred from the extended memory between clusters to the shared memory, it is divided into two instructions, so that the number of instructions increases and the number of interrupts increases. Therefore, there is a drawback that the processing time increases.

Furthermore, the performance of the entire information processing system is
There is a drawback that the number of instructions decreases and the number of interrupts increases, resulting in a decrease.

[0013]

SUMMARY OF THE INVENTION The present invention is directed to a plurality of arithmetic processing devices, a shared memory shared by these arithmetic processing devices, a data transfer control device for controlling data transfer, and an extended memory of the data transfer control device. And a plurality of clusters each having a local network connecting the plurality of arithmetic processing units, the shared memory and the data transfer control device, and an inter-cluster network connecting these clusters, The data transfer control device has an instruction decoding means for decoding a transfer instruction instructing the transfer sent from the arithmetic processing device in the cluster to which the data transfer control apparatus belongs, and the result of the instruction decoding means is the instruction type designated in advance. First storing the transfer instruction separately when the case condition is satisfied;
Transfer instruction storage means, and second transfer instruction storage means for separately storing the transfer instruction when the condition that the result decoded by the instruction decoding means is a prespecified instruction type is satisfied. Transfer control means for synchronizing the instructions from the first transfer instruction storage means and the second transfer instruction storage means for each data transfer processing unit and reading the transfer instructions, and within the cluster to which the transfer control means directs Shared memory access means for writing / reading data to / from the shared memory, extended memory access means for writing / reading data to / from the extended memory in the cluster to which the shared memory belongs, and the local network according to an instruction from the transfer control means. And a data transfer means for transferring data via the inter-cluster network. To.

A data transfer buffer may be provided for temporarily holding data when accessing the expansion memory.

Further, in the data transfer method using this data transfer control device, in the data transfer between the extended memory of the cluster and the shared memory of the other cluster, a data transfer area is provided on the shared memory to extend the data. It is a composite instruction of data transfer from memory to shared memory and data transfer from the shared memory to shared memory of another cluster, the composite instruction is received by the data transfer control device, the request is discriminated, and the shared memory is sent from the extended memory. Shared memory that separates the data transfer instruction to the requester and the data transfer instruction from the shared memory to the shared memory of another cluster, synchronizes each instruction processing, and issues an end interrupt to the requester when both instruction processing is completed. It is characterized by interposing.

Further, the data transfer buffer is provided with the data transfer buffer, and a composite command of data transfer from the extended memory to the data transfer buffer and data transfer from the buffer to the shared memory of another cluster is provided. , And separates the request to separate the data transfer instruction from the extended memory to the data transfer buffer and the data transfer instruction from the data transfer buffer to the shared memory of another cluster, and synchronizes the respective instruction processing, It is characterized by interposing a data transfer buffer that issues an end interrupt to the requester when both instruction processing is completed.

[0017]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an information processing system showing an embodiment of the present invention. Referring to FIG. 1, this information processing system comprises a plurality of clusters 1 and an inter-cluster network 6 as in the conventional case.
A plurality of arithmetic processing devices 2, a shared memory 3 shared by these arithmetic processing devices 2, a local network 4 having an interface between the plurality of arithmetic processing devices 2 and the shared memory 3, a local network 4, and a cluster network 6. And a data transfer control device 5 for controlling data transfer between the extended memory 7 of the own cluster and the shared memory of another cluster.

The data transfer control device 5 comprises the arithmetic processing device 2
From the extended memory 7 of the transfer source cluster to the shared memory of the transfer destination cluster via the local network 4;
When the instruction decoding unit 51 detects a type of instruction designated in advance, the instruction is separated, and the separated instruction is written into the first instruction storage unit 52 and the second instruction storage unit 5.
3 and write to the shared memory 3 in its own cluster
Shared memory access means 55 for reading, extended memory access means 57 for writing / reading to / from the extended memory 7 in the self cluster, shared memory access means 55 or extended memory access means 57, and between the local network 4 and the cluster. The data transfer means 56 for transferring data to and from the network 6, the transfer instruction from the first instruction storage means 52 and the second instruction storage means 53, and the shared memory access control means 55 according to the instruction of the content of the transfer instruction. It comprises an extended memory access means 57 and a transfer control means 54 for controlling the data transfer means 56.

Next, a transfer instruction (hereinafter, transfer instruction A) for transferring data from the extended memory 7 of its own cluster (hereinafter, transfer source cluster) to the shared memory of another cluster (hereinafter, transfer destination cluster) Is called)
The operation of data transfer when issued from the data transfer control device 5 will be described.

First, the instruction decoding means 51 of the data transfer control device 5 receives a transfer instruction A, and this transfer instruction A is an inter-cluster data transfer instruction from the extended memory 7 of the own cluster to the shared memory of another cluster. When this is detected, the transfer instruction A is decomposed into the data transfer instruction (transfer instruction A1) from the extended memory 7 in the own cluster to the shared memory 3 in the own cluster and is written in the first instruction storage means 52.
Further, the transfer instruction A is a data transfer instruction from the shared memory 3 of its own cluster to the shared memory of another cluster (transfer instruction A
It is decomposed into 2) and written in the second instruction storage means 53.

The transfer control means 54 reads the transfer instruction from the first instruction storage means 52 and the second instruction storage means 53, and transfers the data from the extension memory 7 to the extension memory access means 57 according to the content of the instruction. And instruct the data transfer means 56 to send the read data.

Then, the transfer control means 54 instructs the data transfer means 56 to operate the transfer destination (for example, a command indicating the type of transfer, the start address to the shared memory, the transfer length, etc.), the transfer destination cluster. Identifier, destination device identifier,
In the case of the transfer source cluster identifier, the transfer source device identifier, and the ID method, the ID is added to the data sent from the extended memory access means 57, and an instruction is sent to the local network 4. Then, the data is written to the shared memory of the transfer destination via the local network 4 according to the content of the additional information, and the transfer control means 54 is notified of the completion of reading.

Further, the transfer control means 54 instructs the shared memory access means 55 to read the data from the shared memory 3 and send the read data to the data transfer means 56, and instructs the data transfer means 56. Operation instruction to transfer destination (for example, command indicating transfer type, start address to shared memory 3, transfer length, etc.), transfer destination cluster identifier, transfer destination device identifier, transfer source cluster identifier, transfer source device identifier and ID In the case of the system, the ID is added to the data sent from the shared memory access means 55, and it is instructed to send it to the inter-cluster network 6.

Then, the data and the additional information are transferred to the data transfer control device of the other cluster of the transfer destination through the inter-cluster network 6, and are written and read in the shared memory of the transfer destination cluster according to the content of the additional information. The transfer control means 54 is notified of the completion. As a result, when both instruction processes are completed, an end interrupt is issued to the requesting arithmetic processing unit 2.

FIG. 2 is a block diagram of an information processing system showing another embodiment of the present invention.

Referring to FIG. 2, this information processing system has the same configuration as the information processing system described above.
The cluster 1 includes a plurality of clusters 1 and an inter-cluster network 6, and the cluster 1 includes a plurality of arithmetic processing devices 2, a shared memory 3 shared by the plurality of arithmetic processing devices 2, a plurality of arithmetic processing devices 2 and a shared memory 3. And a data transfer control device 5a located between the local network 4 and the cluster network 6 for controlling data transfer between the extended memory 7 of the own cluster and the shared memory of another cluster. To be done.

The data transfer control device 5a includes an instruction decoding means 51a for receiving and decoding a transfer command to be transferred from the expansion memory 7 of the transfer source to the shared memory 3 of the transfer destination from the arithmetic processing device 2 via the local network 4. When the instruction decoding means 51a detects the type of the instruction designated in advance, the transfer instruction is separated, and the separated instruction is written into the first instruction storing means 52a and the second instruction storing means 5.
3a, a shared memory access means 55 for writing / reading to / from the shared memory 3 in the own cluster, an extended memory access means 57a for writing / reading to / from the extended memory 7 in the own cluster, and an extended memory 7. A data transfer buffer 58 for temporarily holding data when accessing the data, a data transfer means 56 for transferring data between the shared memory access means 55 or the extended memory access means 57a and the local network 4 and the inter-cluster network 6, The shared memory access control means 5 reads the transfer instruction from the first instruction storage means 52a and the second instruction storage means 53a, and instructs the content of the transfer instruction.
5, it comprises an extended memory access means 57a and a transfer control means 54 for controlling the data transfer means 56.

Next, a transfer instruction (hereinafter referred to as a transfer instruction B) for transferring data from the extended memory 7 of the own cluster to the shared memory of another cluster is issued from the arithmetic processing unit 2 to the data transfer control unit 5a. The operation of data transfer in the event of a failure is described.

First, the instruction decoding means 51a of the data transfer control device 5a receives the transfer instruction B, and this transfer instruction B is an inter-cluster data transfer instruction from the extended memory 7 of the own cluster to the shared memory of another cluster. Is detected, the transfer instruction B is transferred to the data transfer buffer 58 from the extended memory 7 in the local cluster (transfer instruction B
It is divided into 1) and written in the first instruction storing means 52a.
Further, a transfer instruction B is transferred from the data transfer buffer 58 to the shared memory 3 of the own cluster (transfer instruction B
It is decomposed into 2) and written in the second instruction storage means 53a.

The transfer control means 54 reads the transfer instruction from the first instruction storage means 52a and the second instruction storage means 53a, and reads the data from the extended memory 7 to the extended memory access means 57a according to the content of the instruction. , To send the read data to the data transfer buffer 58.

Then, the transfer control means 54 instructs the data transfer means 56 to operate the transfer destination (command indicating transfer type, start address to shared memory, transfer length) transfer destination cluster identifier, transfer destination A device identifier, a transfer source cluster identifier, a transfer source device identifier, and in the case of the ID method, an ID is added to the data held in the data transfer buffer 58, and an instruction is sent to the intercluster network 6. Then, the data and the additional information are transferred to the data transfer control device of the transfer destination cluster via the inter-cluster network 6. The transferred data is written in the shared memory of the transfer destination cluster according to the content of the additional information.
When the processing of both instructions is completed, an end interrupt is issued to the arithmetic processing unit 2 of the request source.

[0033]

As described above, according to the present invention, in the data transfer between the extended memory and the shared memory between the clusters, the number of instructions is changed from 2 to 1, and the processing time is reduced by reducing the number of interrupts to the request source. Can be reduced and the increase in hardware can be suppressed. In addition, in the data transfer from the extended memory to the shared memory between the clusters, the number of instructions is reduced from two to one, and the number of interrupts to the request source is reduced, so that the processing time can be reduced.

Further, by using the data transfer buffer, the shared memory does not need to be intervened when executing the instruction, so that it is possible to pass the shared memory to another area and reduce the processing time. This has the effect of improving the overall performance.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an information processing system showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of an information processing system showing another embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 cluster 2 arithmetic processing device 3 shared memory 4 local network 5, 5a, 50 data transfer control device 6 inter-cluster network 7 extended memory 51, 51a, 510 instruction decoding means 52, 52a first instruction storage means 53, 53a second Storage means 54,540 transfer control means 55,550 shared memory access means 56,560 data transfer means 57,57a, 570 extended memory access means 58 data transfer buffer 520 instruction storage means

Claims (4)

[Claims] 1. A plurality of arithmetic processing devices, a shared memory shared by these arithmetic processing devices, a data transfer control device for controlling data transfer, an extended memory of the data transfer control device, and the plurality of arithmetic processing devices. In an information processing system comprising a plurality of clusters each having a local network connecting the shared memory and the data transfer control device, and an inter-cluster network connecting the clusters, the data transfer control device belongs to When the condition that the instruction decoding means for decoding the transfer instruction instructing the transfer sent from the arithmetic processing unit in the cluster and the result decoded by the instruction decoding means are the instruction types designated in advance are satisfied. A first transfer instruction storage unit for storing the transfer instruction separately; and an instruction decoding unit for storing the transfer instruction. Second transfer instruction storage means for separately storing the transfer instruction when the condition that the read result is the instruction type designated in advance is satisfied; and the first transfer instruction for each data transfer processing unit Transfer control means for synchronizing the instructions from the storage means and the second transfer instruction storage means to read the transfer instructions, and writing / reading data to / from the shared memory in the cluster to which the transfer control means belongs are instructed. Shared memory access means, extended memory access means for writing / reading data to / from the extended memory in the cluster to which it belongs, and data transfer via the local network and the inter-cluster network according to instructions from the transfer control means. A data transfer control device, comprising: a data transfer means for performing. 2. The data transfer control device according to claim 1, further comprising a data transfer buffer that temporarily holds data when accessing the expansion memory. 3. A data transfer method using the data transfer control device according to claim 1, wherein in the data transfer between the extended memory of the cluster and the shared memory of the other cluster, the data transfer is performed on the shared memory. Area for
It is a composite instruction of data transfer from the extended memory to the shared memory and data transfer from the shared memory to the shared memory of another cluster, and the composite instruction is received by the data transfer control device, and the request is discriminated and shared from the extended memory. Separate the data transfer instruction to the memory and the data transfer instruction from the shared memory to the shared memory of another cluster, synchronize each instruction processing, and issue an end interrupt to the requester when both instruction processing ends A data transfer method characterized by interposing a memory. 4. A data transfer method using the data transfer control device according to claim 2, wherein in the data transfer between the extended memory of the cluster and the shared memory of the other cluster, the extended memory is transferred to the data transfer buffer. Data transfer instruction from the extended memory to the shared memory of another cluster, and the data transfer control device receives the composite instruction and determines a request to transfer the data from the extended memory to the data transfer buffer. And a data transfer instruction from the data transfer buffer to the shared memory of another cluster to synchronize each instruction processing, and when both instruction processing is completed, interpose a data transfer buffer that issues an end interrupt to the requester. A data transfer method characterized by the above.