JPH0944118A - Interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent disorder of a display screen and characteristic deterioration of an LCD panel by providing a decision circuit which decides the presence of a horizontal synchronizing signal and controls a PLL circuit according to the decision result, and stopping the PLL operation of the PLL circuit unless the horizontal synchronizing signal is outputted and then generating a clock signal within a specific frequency range by the PLL circuit. SOLUTION: The PLL circuit 6 consists of a loop of a phase comparing circuit PC 12, a low-pass filter LF 13, a switch SW 14, a voltage-controlled oscillation circuit VCO 15, a 2nd frequency dividing circuit 16, and a 1st frequency dividing circuit 17, and the phase comparing circuit 12 makes a phase comparison between the frequency division output of the 1st frequency dividing circuit 17 and the horizontal synchronizing signal AHSYNC to generate a clock signal CLK which is locked to the horizontal synchronizing signal AHSYNC. Namely, the decision circuit 7 decides whether or not there is the horizontal synchronizing signal AHSYNC applied to the interface circuit and controls switching from the operation of the PLL circuit 6 to mere oscillation operation according to the decision result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit for displaying on a digital display device using a video signal for an analog display device.

[0002]

2. Description of the Related Art In recent years, multimedia information processing apparatuses have been actively developed, and as a result, so-called personal computers have rapidly become popular not only for business use but also for personal use. These personal computers include a portable type using an LCD as a display device and a stationary type using a CRT display device.

On the other hand, in the LCD display device, a monitor display device with a built-in digital driver using a large panel of 10-inch and 11-inch class has been developed and commercialized for personal computer applications. However, C
R, G of personal computer using RT display device as monitor
Since the B output is an analog signal, such an LCD display device with a built-in digital driver could not be used as a monitor. Therefore, in order to convert the analog signal output of a personal computer into a digital signal, an interface circuit of an A / D conversion circuit is provided in a color LCD display device with a built-in digital driver so that both a digital signal output personal computer and an analog signal output personal computer are provided. I am able to deal with.

FIG. 3 is a block diagram showing a conventional interface circuit. From a personal computer, VGA (Vid
analog color signals based on eo Graphics Array), AR, AG, AB and vertical sync signal AV
The SYNC and the horizontal synchronizing signal AHSYNC are supplied. On the other hand, a color LCD display device (not shown) has a built-in VGA compatible LCD panel, a digital driver and a controller, and an interface circuit allows a vertical synchronization signal VSYNC and a horizontal synchronization signal HSYNC required for display control.
C, dot clock DCLK, control signal ENABLE
And digital color signals DR, DG for gradation display,
DB is supplied.

The interface circuit is the PLL circuit 1,
A timing signal generation circuit 2 and an A / D conversion circuit 3,
It consists of 4 and 5. The PLL circuit 1 uses a horizontal synchronizing signal AHSYNC supplied from a personal computer as a reference signal, and generates a clock signal CLK locked to this signal by a voltage controlled oscillator circuit (VCO). The timing signal generation circuit 2 uses the clock signal CL from the PLL circuit 1.
K, A / D conversion circuit 3, based on the vertical synchronizing signal AVSYNC and the horizontal synchronizing signal AHSYNC from the personal computer.
4, 5 sampling control signal FS and color LC
A vertical synchronizing signal VSYNC and a horizontal synchronizing signal HSYNC for the D display device are created and output.

That is, this interface circuit reproduces the reference clock signal CLK from the horizontal synchronizing signal AHSYNC from the personal computer, and by this clock signal CLK, the dot clock DCLK corresponding to the number of horizontal pixels of the KCD display device is generated. The digital color signals DR, DG, DB that are synchronized with the dot clock DCLK are created.

[0007]

However, in the interface circuit shown in FIG. 3, a color LCD is used.
When the power of the personal computer is turned off while the power of the display device is turned on, the horizontal synchronization signal AHSYN from the personal computer is sent.
C is not output, and the VCO of the PLL circuit 1 is in a so-called free-run state in which it oscillates at the maximum or minimum frequency in the variable frequency range. Or, even if the power of the personal computer is turned on, the horizontal sync signal A
Even if HSYNC is no longer applied to the interface circuit, the same state will occur. When the timing signal generating circuit 2 operates by the clock signal CLK in the free-run state, the sampling signal FS and the dot clock DCL are generated.
K, horizontal sync signal HSYNC, vertical sync signal VSYNC
Etc. become too high or too low compared to the frequency that should be originally supplied to the LCD. In this case, a non-standard frequency is applied to the LCD display device that should be driven at an appropriate frequency, so that the screen may be disturbed, the display may not be normally performed, and the liquid crystal characteristics may be deteriorated. .

[0008]

The present invention was made in view of the above-mentioned problems, and is an interface for generating a plurality of timing signals based on a horizontal synchronizing signal output from an analog video device. A circuit,
A PLL circuit that generates a clock signal with a frequency locked to the horizontal synchronization signal, a timing signal generation circuit that creates a plurality of timing signals based on the clock signal from the PLL circuit, and the presence of the horizontal synchronization signal are determined. ,
A discrimination circuit for controlling the PLL circuit based on the discrimination result is provided, and when the horizontal synchronizing signal is not output, the PLL operation of the PLL circuit is stopped and a clock signal in a predetermined frequency range is supplied to the PLL circuit. It is solved by generating from.

Further, the PLL circuit includes a voltage controlled oscillator circuit, a frequency divider circuit for dividing the output of the voltage controlled oscillator circuit,
A phase comparison circuit for comparing the frequency division output of the frequency division circuit and the phase of the horizontal synchronization signal; a low-pass filter for applying a control voltage based on the output of the phase comparison circuit to the voltage controlled oscillation circuit; A switch circuit that is controlled by the output of the determination circuit and that controls the supply of the control voltage to the voltage controlled oscillation circuit, and an output of the determination circuit that controls the oscillation frequency of the voltage controlled oscillation circuit in the free-run state. The second that divides the frequency and outputs the frequency in a predetermined range
This is solved by outputting the output of the second frequency dividing circuit as the clock signal in a state in which the horizontal synchronizing signal is not applied to the interface circuit.

Further, the PLL circuit compares a voltage-controlled oscillation circuit, a frequency-dividing circuit for frequency-dividing the output of the voltage-controlled oscillation circuit, and a frequency-divided output of the frequency-dividing circuit with the phase of the horizontal synchronizing signal. Controlled by a phase comparison circuit, a low-pass filter for applying a control voltage based on the output of the phase comparison circuit to the voltage controlled oscillator circuit, and an output of the determination circuit, the control voltage and a predetermined voltage are switched to switch A solution is provided by providing a switch circuit for applying to the voltage controlled oscillator circuit, and oscillating the voltage controlled oscillator circuit at a frequency within a predetermined range in a state where the horizontal synchronizing signal is lost.

[0011]

1 is a block diagram of an interface circuit showing an embodiment of the present invention. From the personal computer, the analog color signals AR, AG, and AB of each color are output in synchronization with the vertical sync signal AVSYNC and the horizontal sync signal AHSYNC. The interface circuit is composed of a PLL circuit 6, a discrimination circuit 7, a timing signal generation circuit 8, and A / D conversion circuits 9, 10, 11.

The timing signal generating circuit 8 includes a vertical synchronizing signal AVSYNC, a horizontal synchronizing signal AHSYNC, and
The clock signal CLK of the PLL circuit 6 is applied. As is well known, the timing signal generating circuit 8 is composed of a counter that divides the clock signal CLK and a logic circuit that creates various timing signals based on the count value of the counter. The dot clock DCLK is a clock for transferring data displayed in the pixels of each line, and in the case of VGA, its frequency is about 20 MHZ. Further, since the A / D conversion circuits 9, 10 and 11 generate digital data synchronized with the dot clock DCLK, the sampling signal FS thereof needs to have the same frequency of about 20 MHz as the dot clock DCLK. Therefore, the clock signal CLK needs to have a frequency of 20 MHz or higher.

The PLL circuit 6 has a horizontal synchronizing signal AHSYN.
A circuit for generating a clock signal CLK locked to C, a phase comparison circuit (PC) 12, a low-pass filter (LF) 13, a switch (SW) 14, a voltage controlled oscillation circuit (VC0) 15, and a second component. It is composed of a loop of the frequency dividing circuit 16 and the first frequency dividing circuit 17, and in the phase comparison circuit 12, the frequency division output of the first frequency dividing circuit 17 and the horizontal synchronizing signal AH.
By comparing the phases of SYNC, the horizontal synchronization signal AHS
A clock signal CLK locked to YNC is generated. The feature of this PLL circuit 6 is that a switch 14 controlled by the output of the determination circuit 7 is provided between the low-pass filter 13 and the voltage controlled oscillation circuit 15, and further the output of the voltage controlled oscillation circuit 15 and the first frequency division. The second frequency dividing circuit 16 controlled by the output of the discriminating circuit 7 is provided between the circuit 17 and the second frequency dividing circuit 1
6 is output to the timing signal generation circuit 8 as the clock signal CLK. That is, the presence / absence of the horizontal synchronization signal AHSYNC applied to the interface circuit is determined by the determination circuit 7, and the PL is determined based on the determination result.
The operation of the L circuit 6 is controlled to be switched between a PLL operation and a simple oscillation operation.

The discriminating circuit 7 applies a horizontal synchronizing signal A applied thereto.
A method of integrating HSYNC and determining that there is no horizontal sync signal AHSYNC when the integrated value is below a predetermined level, or counting the clock signal CLK, predicts the timing at which the horizontal sync signal AHSYNC is applied. , The gate is opened during that period, and the horizontal synchronization signal AHSYN
There is a method of checking the existence of C.

In the PLL circuit 6, the horizontal synchronizing signal AH
In a state in which the determination circuit 7 detects that SYNC is applied to the interface circuit, the switch 14 applies a control voltage according to the phase difference output by the low pass filter 13 to the voltage controlled oscillator circuit 15, In addition, the second frequency dividing circuit 16 includes the voltage controlled oscillator circuit 1
The oscillation output of 5 is output as it is without frequency division. Therefore,
In this state, the PLL operation is performed, and the voltage controlled oscillator circuit 15 is locked to the horizontal synchronizing signal AHSYNC. Here, in the case of VGA, the clock signal CL
Since K is required to be 25.175 MHZ as a standard, the oscillation frequency of the voltage controlled oscillator circuit 15 is set to 25.175 MHZ. On the other hand, the reference signal is the horizontal sync signal 31.5.
Since KHZ is used, the oscillation frequency of the voltage controlled oscillator circuit 15 is 31.5 KH by the first frequency divider circuit 17.
It is divided into Z and the divided output is compared with the reference signal.
Therefore, the dividing ratio 1 / N of the first dividing circuit 17 is VGA
In the case of N, N is set to 800 including the blanking period.

Next, in a state where the horizontal synchronizing signal AHSYNC is not applied to the interface circuit, the switch 14 cuts off the output voltage of the low-pass filter 13 by the detection output of the discrimination circuit 7, and the voltage control oscillator circuit 15 receives the control voltage. Is no longer applied. Therefore, in this case, the voltage controlled oscillator circuit 15 is in the free-run state and oscillates at the maximum oscillation frequency fVCOmax. On the other hand, the second frequency dividing circuit 16 divides the frequency of the voltage controlled oscillator circuit 15 into 1 / M in order to lower the maximum oscillation frequency within the allowable frequency range of the LCD display device. That is, the minimum allowable frequency of the LCD display device is fLCDnim and the maximum allowable frequency is fLCDnim.
If LCDmax, the value of M is fVCOmax / fLCDmax
To fVCOmax / fLCDmin,
Clock signal CLK output from the second frequency dividing circuit 16
Is within the allowable frequency range of the LCD display device. As a result, the various timing signals output from the timing signal generation circuit 8 fall within the allowable drive frequency range of the LCD display device, and the characteristic deterioration of the LCD panel can be prevented.

In the embodiment of FIG. 1, the output of the second frequency dividing circuit 16 is applied to the first frequency dividing circuit 17, but the output of the voltage controlled oscillator circuit 15 is applied to the first frequency dividing circuit. Circuit 17
May be applied. FIG. 2 is a block diagram of an interface circuit showing another embodiment of the present invention. 2 is different from FIG. 1 in that a fixed voltage generation circuit 18 is provided, and a fixed voltage generated by the fixed voltage generation circuit 18 and the output voltage of the low-pass filter 13 are switched by a changeover switch 19 to a voltage controlled oscillator circuit 15. The second frequency dividing circuit 16 is not provided as shown in FIG.
The output of is directly output as the clock signal CLK and is also applied to the first frequency dividing circuit 17.

In FIG. 2, when the horizontal synchronizing signal AHSYNC is output from the personal computer, the changeover switch 19 supplies the output voltage of the low-pass filter 13 to the voltage controlled oscillator circuit 15 according to the detection output of the determination circuit 7. Therefore, in this case, the PLL circuit 6 operates normally P
The LL operation is performed, and the clock signal CLK becomes a signal locked to the horizontal synchronization signal AHSYNC.

On the other hand, when the horizontal synchronizing signal AHSYNC is not applied to the interface circuit, the changeover switch 19 applies the fixed voltage of the fixed voltage generating circuit 18 to the voltage controlled oscillator circuit 15 according to the output of the determination circuit 7. Therefore, in this case, the voltage controlled oscillator circuit 15 oscillates at the frequency determined by the fixed voltage. That is, the fixed voltage value is set so that the oscillation frequency of the voltage controlled oscillator circuit 15 is within the allowable frequency range of the LCD display device. As a result, even when the horizontal synchronizing signal AHSYNC is not present, the clock signal CLK falls within the allowable frequency range of the LCD display device, and the characteristic deterioration of the LCD panel can be prevented.

[0020]

As described above, according to the present invention, in the interface circuit for analog input of the LCD display device with the built-in digital driver, even if the horizontal synchronizing signal from the personal computer is not supplied, the LCD display device It is possible to generate a timing signal having a frequency within a specified range, and there is an advantage that disturbance of the display screen and deterioration of the characteristics of the LCD panel can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 6 PLL circuit 7 Discrimination circuit 8 Timing signal generation circuit 9, 10, 11 A / D conversion circuit 12 Phase comparison circuit 13 Low-pass filter 14 Switch 15 Voltage controlled oscillation circuit 16 Second frequency divider circuit 17 First frequency divider circuit 18 Fixed voltage generation circuit 19 Selector switch

Claims (3)

[Claims] 1. An interface circuit for generating a plurality of timing signals based on a horizontal synchronizing signal output from an analog video device, the PLL circuit generating a clock signal having a frequency locked to the horizontal synchronizing signal. A timing signal generating circuit for generating a plurality of timing signals based on a clock signal from the PLL circuit, and a discriminating circuit for discriminating the presence of the horizontal synchronizing signal and controlling the PLL circuit based on the discrimination result. And when the horizontal synchronizing signal is no longer output, the PLL
An interface circuit characterized in that a PLL operation of the circuit is stopped and a clock signal in a predetermined frequency range is generated from the PLL circuit. 2. The PLL circuit includes a voltage controlled oscillator circuit, a frequency divider circuit for dividing the output of the voltage controlled oscillator circuit,
A phase comparison circuit for comparing the frequency division output of the frequency division circuit and the phase of the horizontal synchronization signal; a low-pass filter for applying a control voltage based on the output of the phase comparison circuit to the voltage controlled oscillation circuit; A switch circuit that is controlled by the output of the determination circuit and that controls the supply of the control voltage to the voltage controlled oscillation circuit, and an output of the determination circuit that controls the oscillation frequency of the voltage controlled oscillation circuit in the free-run state. The second that divides the frequency and outputs the frequency in a predetermined range
2. The interface circuit according to claim 1, wherein the frequency divider circuit is provided, and the output of the second frequency divider circuit is output as the clock signal when the horizontal synchronizing signal is not output. 3. The PLL circuit comprises a voltage controlled oscillator circuit, a frequency divider circuit for dividing the output of the voltage controlled oscillator circuit,
A phase comparison circuit for comparing the frequency division output of the frequency division circuit and the phase of the horizontal synchronization signal; a low-pass filter for applying a control voltage based on the output of the phase comparison circuit to the voltage controlled oscillation circuit; A switch circuit that is controlled by the output of the discrimination circuit and switches the control voltage and a predetermined voltage to apply the voltage control oscillation circuit to the voltage control oscillation circuit is provided. The device is oscillated at a frequency.
Interface circuit described.