JPH0936923A - Digital signal transmitting method and digital signal demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To modulate a data clock and the digital signals of plural systems synchronized with it to the digital signal of one system for transmission and to transmit it with a simple method. SOLUTION: The pulse width of mutually different lengths corresponding to the combination of the binary levels of digital signals d11 and d12 is previously decided within the range of a term T of a data clock ϕ1. Each time the data clock ϕ1 rises, the digital signals d11 and d12 almost simultaneously rise and are transmitted after being modulated to a digital signal o1 of one system for transmission as a pulse having the pulse width decided as mentioned above corresponding to the combination of the binary levels of the respective signals d11 and d12. At the time of demodulation, a data clock o2 in the term T is demodulated from the rise term T of the digital signal o1 for transmission, and respective digital signals d21 and d22 having the combination of binary levels decided as mentioned above are demodulated from the pulse width of this digital signal o1 for transmission.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal transmission method for transmitting digital signals between various digital devices, and more particularly to a plurality of digital signals synchronized with a data clock and the data clock. The present invention relates to a digital signal transmission method for transmitting a signal.

[0002]

2. Description of the Related Art Conventionally, when transmitting a digital signal between digital devices, various transmission methods have been used. Widely used transmission methods include, for example, a parallel transmission method in which digital signals of each system are transmitted by different transmission systems, or a digital signal of a plurality of systems is transmitted by time-sharing one transmission system. A serial transmission method can be used.

The serial transmission method is a method in which one transmission system is time-divided and a digital signal of a corresponding system is transmitted for each divided time. In this method, the receiving unit needs to determine which system of the digital signal the digital signal transmitted through the transmission system corresponds to, which complicates the processing in the transmitting unit and the receiving unit. Further, when the information necessary for the determination is transmitted by the transmission system, it is necessary to distinguish the information from the digital signal, which further complicates the processing in the transmitter and the receiver.

[0004] Therefore, when it is desired to simplify the configuration of the transmission unit and the reception unit, a parallel transmission method in which a dedicated transmission system is assigned to each system of digital signals and the signals are transmitted as they are is often used. In addition, a digital signal transmission method in which digital signals of a plurality of systems are encoded into several bits and transmitted in parallel by a transmission system for the number of bits is also used.

[0005]

However, in the conventional digital signal transmission method based on the parallel transmission method, the number of transmission systems corresponding to the number of digital signal systems, or
A transmission system for the number of encoded bits is required. further,
When the digital signal of each system is synchronized with the data clock, the data clock needs to be transmitted by another transmission system.

Therefore, the above-mentioned conventional digital signal transmission method has a problem that it is difficult to reduce the number of transmission systems. Since each transmission system includes a transmission unit, a reception unit, a transmission line, and the like, an increase in the transmission system causes the overall configuration of the transmission means to become complicated and large.
In particular, in the case of performing optical transmission, the optical transmitter, the optical receiver, and the optical cable have a complicated structure and are difficult to miniaturize as compared with the respective portions in the case of transmitting using electricity, and therefore, there is a strong demand for solving the above problems. There is.

The present invention has been made in view of the above problems, and an object thereof is to transmit a data clock and a plurality of digital signals synchronized with the data clock as one digital signal. It is to realize a simple method.

[0008]

According to a first aspect of the present invention, there is provided a digital signal transmission method, wherein a plurality of systems of digital signals synchronized with a data clock are converted into a single system of transmission digital signals. A digital signal transmission method in which the digital signal for transmission has the same cycle as the data clock and is input in synchronization with each data clock. It is characterized by having a predetermined pulse width for a combination of binary levels of signals.

In the above structure, the cycle of the data clock can be restored by the cycle of the transmission digital signal, and a plurality of systems of predetermined binary level combinations depending on the pulse width of the transmission digital signal. The digital signal of can be restored.

Therefore, one transmission is possible without the need for a plurality of transmission systems for transmitting digital signals of a plurality of systems and a transmission system for transmitting a data clock, which were required in the case of parallel transmission as in the prior art. Depending on the system, a plurality of systems of digital signals synchronized with the data clock and the data clock can be transmitted.

Since the number of transmission systems can be drastically reduced as compared with the prior art, the number of transmission units, reception units, and transmission lines required for each transmission system can be reduced, and transmission means used for transmission of digital signals. The overall configuration can be greatly simplified.

A digital signal demodulating device according to a second aspect of the invention is a digital signal demodulating device for demodulating a transmission digital signal according to the first aspect, which is characterized by the following means.

That is, clock generation means for synchronizing with the transmission digital signal and generating a data clock having the same frequency as the transmission digital signal and a high-speed clock having a frequency higher than the transmission digital signal,
A pulse width measuring means for measuring the pulse width of the transmission digital signal, and a plurality of combinations having a predetermined binary level corresponding to the pulse width based on the pulse width measured by the pulse width measuring means. And a signal generating means for generating a digital signal of the system.

Further, the pulse width measuring means is provided with counting means for counting the period of the high speed clock generated by the clock generating means and measuring the pulse width.

The clock generation means is a PLL (Pha
se lock loop) circuit, etc., and oscillates a data clock having the same frequency as the transmission digital signal and synchronized with the transmission digital signal, and a high-speed clock having an integer multiple frequency of the transmission digital signal. It is a thing.

With the above structure, the digital signal demodulation device can demodulate the data clock from the cycle of the transmission digital signal and the digital signal of each system from the pulse width. As a result, it is not necessary to perform time division as in the digital signal demodulating device in the conventional serial transmission method, and thus it is possible to demodulate digital signals of a plurality of systems with a relatively simple configuration. Therefore, it is possible to easily realize a digital signal demodulator having a high operation speed and a short delay time. As a result, it is possible to easily demodulate the digital signal in the same cycle as the digital signal before modulation. In addition, the number of required digital signal demodulators can be significantly reduced as compared with the conventional parallel transmission method. In addition, since the pulse width is measured by the high speed clock used when demodulating the data clock, the pulse width can be measured without separately providing a clock for measuring the pulse width.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 2, a transmission device for transmitting a digital signal by the digital signal transmission method according to the present invention has a data clock φ1 and, for example, two systems of digital signals d11. d12
And a modulation unit 1 for modulating the transmission digital signal o1 and the modulated transmission digital signal o1 from the data clock φ2.
And a demodulation unit 2 for demodulating the two systems of digital signals d21 and d22, and a digital transmission line 3 such as an optical cable for connecting the two and transmitting the transmission digital signal o1.

In this embodiment, since two systems of digital signals d11 and d12 are transmitted, there are usually four combinations of binary levels to be transmitted, and each combination has a pulse width different from each other. Pulse p00, p
01, p10, and p11 are assigned. The pulse width of each pulse is the period T of the data clock φ1.
It is set to a shorter value.

In the present embodiment, for convenience of explanation, 2
The case where the digital signals d11 and d12 input to the system are converted into the digital signal o1 for transmission of one system has been described. However, by increasing the number of pulse widths corresponding to the combination of binary levels, two or more systems are provided. Can be transmitted as one system of transmission digital signal o1.

In the following, one of the binary levels is represented by 1 and the other is represented by 0, and the combination of the binary level a1 of the digital signal d11 and the binary level a2 of the digital signal d12 is expressed as follows.
It is written as (a1, a2). For example, the binary level of the digital signal d11 is 1 and the binary level of the digital signal d12 is 2.
When the value level is 0, the digital signals d11 and d12
The binary level combination of is represented by (1, 0).

Here, 2 of the digital signals d11 and d12
FIG. 3 shows an example of correspondence between combinations of value levels and pulses. That is, the combination (0, 0) of the binary levels of the digital signals d11 and d12 corresponds to the pulse p00 having the pulse width w00, and the combination (0, 1) corresponds to the pulse p01 having the pulse width w01. For the combination (1,0), the pulse p1 with the pulse width w10
0 is assigned, and for the combination (1,1),
A pulse p11 having a pulse width w11 is assigned.

As shown in FIG. 2, the modulator 1 is arranged so that the digital signals d11 and d12 synchronized with the data clock φ1 are generated.
Data recognition unit 11 for recognizing a combination of binary levels of
And a pulse generation unit 12 that rises at substantially the same time as the data clock φ1 and generates a transmission digital signal o1 that is a pulse having a pulse width based on the recognition of the data recognition unit 11.

The data recognizing section 11 receives the digital signals d11 and d1 each time the data clock φ1 rises.
A binary level combination of 2 is recognized, and a pulse width set value indicating a pulse width determined in advance for the combination is output.

The pulse generator 12 uses the data clock φ1.
The digital signal for transmission o1 which is an output is raised at substantially the same time as the rising of the digital signal, the number of rises of the master clock ck1 is counted, and the digital signal for transmission o1 is set to the Hi level while the pulse generator 12 counts the pulse width setting value. keep. When the pulse width setting value is exceeded, the pulse generator 1
2 lowers the transmission digital signal o1 to the Low level and waits for the next rising of the data clock φ1.

As a result, the pulse generator 12 rises at substantially the same time as the data clock φ1, and the digital signal d1
A pulse having a pulse width corresponding to a combination of binary levels of 1 · d12 is output to the digital transmission line 3 as a transmission digital signal o1.

The master clock ck1 is used to generate a data clock φ1 by frequency division, and is synchronized with the data clock φ1. The master clock ck1 is a clock having a frequency sufficiently higher than that of the data clock φ1, and the pulse widths corresponding to the above combinations can be distinguished by counting the number of rising times of the clock.

The transmission digital signal o1 modulated by the modulator 1 is transmitted to the demodulator 2 via one digital transmission line 3. The demodulator 2 includes a rising edge detector 21 for demodulating the data clock φ2 and a PLL (Phase Locator).
k Loop) circuit 22 (clock generating means), a counter 25 (pulse width measuring means and counting means) for demodulating the digital signals d21 and d22 of each system, and a data generating section 26 (signal generating means). .

The rising detector 21 is a flip-flop.
Each time a rising edge of the transmission digital signal o1 is detected, a binary level different from the current output is stored and the stored binary level is output. Therefore, the rise detection unit 21 determines that the transmission digital signal o1
The rising clock ck2 having a doubled cycle is output at almost the same time as the rising of the clock.

The PLL circuit 22 comprises a PLL oscillator 23 and a frequency divider 24. PLL oscillator 2
3 oscillates the high-speed clock ck3 having a frequency of approximately 2k times (k is a preset integer) of the rising clock ck2, and the rising clock ck2,
A comparison clock ck obtained by dividing the high-speed clock ck3 and having substantially the same frequency as the rising clock ck2.
4 and the period of the high-speed clock ck3 is adjusted so that the rising times of both are the same.

For example, when the comparison clock ck4 rises earlier than the rising clock ck2, the cycle of the high speed clock ck3 is changed slightly longer, and when it rises later, the cycle of the high speed clock ck3 is changed slightly shorter. The rising clock ck2 and the high speed clock ck3 are synchronized. The frequency of the high-speed clock ck3 is set to be slightly higher than the frequency that is 2k times higher than the rising clock ck2, and the comparison clock ck3
Whenever 4 rises faster than rising clock ck2, high-speed clock ck3 is thinned out, and rising clock c
The k2 and the high-speed clock ck3 may be synchronized.

The frequency divider 24 divides the high-speed clock ck3 oscillated by the PLL oscillator 23 by 2 k to generate the comparison clock ck4, and at the same time, the high-speed clock ck4.
3 is divided by k to generate a data clock φ2.

The integer k that determines the oscillation frequency of the PLL oscillator 23 and the frequency division ratio of the frequency divider 24 is a binary value that differs from each other by counting the number of rising times of the high-speed clock ck3 oscillated by the PLL oscillator 23. It is set to a number larger than the number of pulse widths so that each pulse width corresponding to a combination of levels can be distinguished. Generally, in a PLL circuit, k is set to a sufficiently large value in order to suppress frequency fluctuations and at the same time make the Hi level period and the Low level period substantially the same.

On the other hand, the counter 25 counts the number of times the high-speed clock ck3 rises and the time during which the transmission digital signal o1 is at the Hi level (that is, the pulse width).
To measure. In addition, the data generation unit 26 uses the counter 2
The pulse width of the transmission digital signal o1 is discriminated based on the count value of 5, and two systems of digital signals d21 and d22 having a combination of binary levels corresponding to the pulse width.
Generate

With the above configuration, the operation of each part of the transmission device when the data clock φ1 shown in FIG. 1 and the digital signals d11 and d12 synchronized with the data clock φ1 are input will be described based on FIGS. 1 and 2. The explanation is as follows.

For example, at time t1 shown in FIG. 1, which is one of the rising points of the data clock φ1, the combination of binary levels of the digital signals d11 and d12 is (0, 0).

Therefore, the data recognizing section 11 in the modulating section 1 combines the binary level of the digital signals d11 and d12 (0,
0) is recognized, and the pulse width setting value indicating the pulse width w00 corresponding to the combination (0, 0) is output.

The pulse generating section 12 at time t1
Output is Hi at approximately the same time as the rising edge of the data clock φ1
While rising to the level, the number of rising times of the master clock ck1 is counted and clocked. When the number of times counted by the pulse generation unit 12 exceeds the pulse width setting value indicating the pulse width w00, the pulse generation unit 12 lowers the output to the Low level and waits until the data clock φ1 rises next. As a result, from the time t1, the pulse P1 having the pulse width w00 rises at almost the same time as the data clock φ1.

Then, from the time t2 which is the next rising time of the data clock φ1, the time t1 is almost the same as the time t1.
Combination of binary levels of the digital signals d11 and d12 at the rising edge of the data clock φ1 (1,0)
A pulse P2 having a pulse width w10 corresponding to is generated.

Similarly, at the time of rising of each of the other data clocks φ1, the modulator 1 similarly operates the digital signal d11.
A pulse having a pulse width corresponding to the combination of the binary levels of d12 and rising at substantially the same time as the data clock φ1 is generated. As a result, the digital signals d11 and d1
2 and the data clock φ1 are the digital signal o1 for transmission.
Is modulated to.

The rising cycle of the transmission digital signal o1 is T, which is the same as the cycle of the data clock φ1,
The pulse width of each pulse is 2 of the digital signals d11 and d12.
Corresponds to a combination of value levels.

When the transmission digital signal o1 is transmitted to the demodulation unit 2 via the digital transmission line 3, the demodulation unit 2
Demodulates the data clock φ2 and the digital signals d21 and d22 from the transmitted digital signal o1 for transmission.

That is, in order to demodulate the data clock φ2, the rising edge detecting section 21 generates a rising edge clock ck2 having a different binary level for each rising edge of the transmission digital signal o1. Since the rising edges of the transmission digital signal o1 are at regular intervals of the cycle T, the rising clock ck2 has a cycle of 2T and has a cycle of H.
The clock has a duty ratio of about 50%, which is the ratio of the i-level time.

The PLL circuit 22 oscillates a high-speed clock ck3 having a frequency approximately 2k times higher than the rising clock ck2 by the PLL oscillating unit 23, and the clock ck3 and a comparison clock ck4 obtained by dividing the frequency by 2k by the frequency divider 24. The frequency of the high-speed clock ck3 is adjusted so that the two rise at approximately the same time. As a result, the rising clock ck2
, A high-speed clock ck3 having a frequency approximately 2k times that of the clock ck2 is obtained. Further, the frequency divider 24 divides the clock ck3 by k to generate the data clock φ2.

The data clock φ2 is synchronized with the rising clock ck2, and the rising clock ck2 is 2
It is a double frequency clock. Rising clock ck
Since the cycle of 2 is 2T, the cycle of the data clock φ2 is T. Further, since the data clock φ1, the transmission digital signal o1, and the rising clock ck2 rise at substantially the same time, the data clock φ2 rises slightly later than the data clock φ1. As a result, the data clock φ1 before modulation has the same cycle and the clock φ1
The data clock φ2 which rises at approximately the same time is demodulated.

On the other hand, digital signals d21 and d2 of each system
In order to reproduce 2, the counter 25 uses the high-speed clock ck3 during the time when the transmission digital signal o1 is at the Hi level.
It is measured by counting the number of rising edges.

The count value of the counter 25 indicates the pulse width of the transmission digital signal o1, and based on the count value, the data generator 26 obtains a combination of binary levels corresponding to the pulse width. Data generator 26
Restores the digital signals d21 and d22 according to the obtained combination of binary levels.

For example, the pulse width w00 of the pulse P1 shown in FIG. 1 corresponds to the combination of binary levels (0, 0). Therefore, the count value of the counter 25 indicates the pulse width w00. Based on the count value, the data generator 26 determines that the digital signal d21 whose binary levels are both 0.
And d22 are respectively demodulated.

Further, the pulse width w of the pulse P2 shown in FIG.
10 corresponds to a combination of binary levels (1, 0). Therefore, the data generation unit 26 determines that the binary level is 1.
And a digital signal d22 having a binary level of 0 are generated.

The counter 25 and the data generator 26
In, the pulse width of each pulse is discriminated and the digital signals d21 and d22 are generated. Therefore, the digital signals d21 and d22 are generated with a certain delay after the rising of the transmission digital signal o1.

In this embodiment, the data generator 26
Is the time when the pulse width measurement is definitely finished,
The digital signals d21 and d22 are generated when the longest pulse width w11 shown in FIG. 3 has elapsed. Counter 2
5 and the data generation unit 26 can be realized by a simple circuit such as a counter circuit and a comparison circuit, the delay time generated in the data generation unit 26 is small. Therefore, the digital signals d21 and d22 corresponding to the pulse P1 are
From time t3 delayed by about w11 from time t1, digital signals d21 and d22 corresponding to the pulse P2 are output from time t4 delayed by about w11 from time t2. Since the longest pulse width w11, which is the time required to determine the pulse width of each pulse, is shorter than the period T, the digital signals d21 and d22 are the digital signals d11 and d before modulation.
It is demodulated in the same cycle as 12. Also, the data clock φ
The delay time of the digital signals d21 and d22 with respect to 1 is
It can be suppressed within 1 clock.

Even if the maximum pulse width is not waited for, it is possible to determine whether or not the pulse is the longest pulse when the pulse width next to the longest pulse width is exceeded. By generating the digital signals d21 and d22 at this point,
The delay time can be further shortened.

As described above, in the transmission device using the digital signal transmission method according to the present embodiment, the combination of binary levels of digital signals of a plurality of systems is previously associated with the pulse width of the transmission digital signal. I will let you. Then, by modulating into a transmission digital signal o1 having a pulse width corresponding to a combination of binary levels of digital signals inputted at the same time and having the same cycle as the data clock φ1, a plurality of systems of digital signals and data clock φ are obtained.
1 and 1 can be transmitted by one system of digital transmission line 3.

Further, the demodulation section 2 uses the digital transmission line 3
The data clock φ2 is demodulated from the cycle of the transmission digital signal o1 transmitted by the above-mentioned method, and the digital signal having the combination of the binary level corresponding to the pulse width is demodulated from the pulse width of the transmission digital signal o1.

Therefore, the number of transmission systems can be significantly reduced as compared with the conventional parallel transmission method. As a result, the number of transmitters, receivers, and transmission lines required for each transmission system can be significantly reduced, and the configuration of the entire transmission device can be simplified.

Further, in the demodulation section 2 according to the present embodiment, the PLL circuit 22 demodulates the data clock φ2 and the high-speed clock generated by the PLL circuit 22 when measuring the pulse width of the transmission digital signal o1. ck3
By counting the pulse width to demodulate the digital signals d21 and d22.

Therefore, it is possible to demodulate digital signals of a plurality of systems with a demodulator having a simple structure as compared with the conventional serial transmission method. Therefore, it is possible to easily realize a demodulator having a high operation speed and a short delay time.

Further, the pulse width of the transmission digital signal o1 can be measured without separately providing a pulse width measuring clock. Furthermore, since the high-speed clock ck3 rises at almost the same time as the rise of the transmission digital signal o1,
There will be no measurement error due to the synchronization shift between the two. As a result, without complicating the configuration of the demodulation unit 2,
The pulse width can be measured with high accuracy.

In the present embodiment, pulses having different pulse widths are assigned to all combinations of binary levels that the digital signals d11 and d12 can take, but the digital signals d11 and d12 can take such combinations. Not 2
It is not necessary to assign pulses of different pulse widths to the combination of value levels. Thus, when there are binary level combinations that cannot be taken at the same time, the number of pulses to be allocated can be reduced, and the accuracy required when measuring the pulse width can be suppressed to a low level.

As a transmission path for transmitting the transmission digital signal o1, a wire such as an electric wire or an optical cable, or a wireless one such as infrared rays can be used. If the transmission path is capable of transmitting pulses, substantially the same effect as this embodiment can be obtained.

[0061]

As described above, the digital signal transmission method according to the first aspect of the present invention modulates a plurality of systems of digital signals synchronized with the data clock into one system of transmission digital signals and transmits the digital signals. A digital signal transmission method for demodulation, wherein the transmission digital signal is a plurality of systems of digital signals input in synchronization with the data clock.
It has a predetermined pulse width for a combination of value levels and has the same cycle as the cycle of the data clock.

Therefore, a plurality of transmission systems for transmitting digital signals of a plurality of systems and a transmission system for transmitting a data clock, which were required in the case of parallel transmission as in the conventional case, are not required, and one The transmission system can transmit a plurality of systems of digital signals synchronized with the data clock and the data clock. As a result, it is possible to significantly reduce the number of transmission systems and to simplify the configuration of the entire transmission means as compared with the related art.

As described above, the digital signal demodulating device according to the second aspect of the invention uses the data clock synchronized with the transmission digital signal and having the same frequency as the transmission digital signal and the transmission digital signal. A clock generating means for generating a high-speed clock having a high frequency, a pulse width measuring means for measuring the pulse width of a digital signal for transmission, and a pulse width corresponding to the pulse width measured by the pulse width measuring means. Signal generation means for generating a plurality of systems of digital signals having a combination of predetermined binary levels, and the pulse width measurement means includes a cycle of the high-speed clock generated by the clock generation means. In this configuration, counting means for counting and measuring the pulse width is provided.

With the above structure, the digital signal demodulating device can demodulate digital signals of a plurality of systems with a relatively simple structure. Further, the number of transmission systems required is smaller than that of the digital signal demodulation device of the parallel transmission method. As a result, it is possible to simplify the configuration of the digital signal demodulation device that demodulates digital signals of a plurality of systems. Therefore, the operation speed of the digital signal demodulator is improved,
It is easy to shorten the delay time. As a result, it is possible to easily realize a digital signal demodulating device that demodulates in the same cycle as the digital signal before modulation.

In addition, the pulse width is measured using the high speed clock used when demodulating the data clock. As a result, it is not necessary to separately provide a clock for measuring the pulse width, and it is possible to further simplify the configuration of the digital signal demodulating device.

[Brief description of drawings]

FIG. 1 is a waveform diagram showing waveforms of respective parts of a digital signal transmission device that transmits a digital signal using a digital signal transmission method according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a main part of the digital signal transmission device.

FIG. 3 is a waveform diagram showing an example of correspondence between a combination of binary levels of an input digital signal and a pulse of an output digital signal for transmission in the digital signal transmission method.

[Description of Codes] 1 Modulator 2 Demodulator (Demodulator) 3 Digital Transmission Line 22 PLL Circuit (Clock Generating Means) 25 Counter (Pulse Width Measuring Means and Counting Means) 26 Data Generating Unit (Signal Generating Means)

Claims (2)

[Claims] 1. A digital signal transmission method in which a plurality of systems of digital signals synchronized with a data clock are modulated into one system of transmission digital signals for transmission and then demodulated, wherein the transmission digital signals are: It is characterized in that it has a predetermined pulse width for a combination of binary levels of digital signals of a plurality of systems input in synchronization with the data clock, and has the same cycle as the cycle of the data clock. Digital signal transmission method. 2. A digital signal demodulating device for demodulating a digital signal for transmission according to claim 1, wherein the data clock synchronized with the digital signal for transmission has the same frequency as the digital signal for transmission and the transmission. A clock generating means for generating a high-speed clock having a frequency higher than that of the digital signal for use, a pulse width measuring means for measuring the pulse width of the digital signal for transmission, and a pulse width measured by the pulse width measuring means, Signal generation means for generating a plurality of systems of digital signals having a combination of the above-mentioned predetermined binary levels corresponding to the pulse width, and the pulse width measurement means has a high speed generated by the clock generation means. A digital signal demodulating device, characterized in that counting means for counting a clock period to measure a pulse width is provided.