JPH0936865A - Data transmission method and its device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transmit audio video data adopting the D2 system or the like in compliance with the AAL1 protocol of the ATM system. SOLUTION: Only data included in an ancillary data area and a video data area are extracted from sound and video data of the D2 system at a data rate of 143Mbps and the data quantity is reduced to be at a data rate 132Mdps or below in compliance with the AAL1 protocol for an ATM communication channel. The sound and video data of the D2 system whose quantity is reduced are multiplexed together with other prescribed data into a prescribed transport packet in the unit of lines and the pocket is sent to the ATM communication channel. A receiver side adds unrequired date to the received sound and video data to reproduce the video and sound data of the D2 system and the receiver side outputs them synchronously with a regenerated synchronizing signal SYNC.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is an AT for audio / video data etc. obtained from a D2 type VTR device in units of one line.
The present invention relates to a data transmission method and apparatus for transmitting data via an M communication line or the like.

[0002]

2. Description of the Related Art The MPEG2 system is widely used as a system for compressing and encoding audio / video data. On the other hand, recently, an asynchronous transmission mode (ATM) system has been put into practical use as a high-speed digital data transmission system.

In the ATM system, AAL (ATM Adop) is used as a protocol of the adaptation layer of ATM.
tation Layer) Type 1 to AAL Type 5 (hereinafter AA
L1 to AAL5) are known. Of these protocols, only AAL1 has a fixed data rate,
Currently, it is suitable for audio / video data transmission.

[0004]

[Problems to be Solved by the Invention] In AAL1,
53-byte transport packet (hereinafter, simply AT
Of the M cells), 47 bytes are used as a payload part of user data and can be used for transmission of audio / video data. Therefore, the data length of the transport packet of the MPEG2 system is exactly 4 ATM.
The size is 188 (= 47 × 4) bytes so that one cell can transmit one transport packet.

However, the data length of the transport packet of the MPEG2 system is not always exactly 188 bytes depending on the data format. Therefore, 18
If it is shorter than 8 bytes, the entire payload cannot be used effectively, and if it is longer than 188 bytes, one ATM transport packet cannot be completely transmitted by four ATM cells. .

The data length of the transport packet of the MPEG2 system is an integer multiple of the data length of the payload part of the ATM cell other than 188 bytes, for example, 47 bytes, 94.
Bytes, 235 bytes, etc. are also possible. However, even if the value is other than 188 bytes, the data length of the transport packet is just 47 bytes, 94 bytes,
If it does not become 235 bytes, the same trouble as in the case of 188 bytes occurs.

Further, when audio / video data having a low compression rate or uncompressed is transmitted by the ATM system, the data rate becomes high, and therefore it is necessary to prevent waste in the payload part of the ATM cell. . For example, in the ATM system, an interface defined as SDH has a basic data rate of 155.52 Mbp for digital multiple hierarchy.
It is unified in s. The data rate obtained by removing the address part (6 bytes for each ATM cell) from this basic data rate is 132.8 Mbps. Here, the data rate of the audio / video data of the D2 system is 143 Mbps.
Therefore, it is not compatible with the AAL1 protocol as it is.

The present invention has been made in view of the above-mentioned problems of the prior art, and it is used effectively without causing waste in the payload part of an ATM cell to transmit audio / video data of the MPEG2 system or the like. It is an object of the present invention to provide a data transmission method and an apparatus therefor capable of performing the data transmission. In addition, the present invention converts audio / video data such as the D2 system into AT
It is an object of the present invention to provide a data transmission method and apparatus capable of transmitting data in conformity with the M-system AAL1 protocol.

[0009]

In order to achieve the above object, a data transmission method according to the present invention provides a synchronous transmission mode (AT) of D2 audio / video data from a transmission side to a reception side.
M) A data transmission method of transmitting via a communication line, wherein the transmitting side multiplexes the audio / video data of the D2 system on a line-by-line basis at a predetermined position of a predetermined transport packet, The audio / video data multiplexed in the transport packet is transferred to the ATM.
It is transmitted to the receiving side via a communication line.

Preferably, on the transmitting side, only the audio data and the video data are separated from the audio / video data of the D2 system on a line-by-line basis, and only the separated audio data and the video data are separated by a predetermined transformer on a line-by-line basis. It is multiplexed at a predetermined position of the port packet.

Preferably, the AT is provided on the receiving side.
Receiving the transport packet from the M communication line,
The audio data and the video data are separated from the received transport packet, and the separated audio data and the video data are reassembled into the D2 format.

Further, in the data transmission device according to the present invention, the data transmission device on the transmission side is changed from the data transmission device on the reception side to the D transmission device.
A data transmission device for transmitting two types of audio / video data via an ATM communication line, wherein the data transmission device on the transmission side transmits only audio data and video data from D2 system audio / video data in line units. Audio / video data separation means for separating data, multiplexing means for multiplexing the separated audio data and video data at a predetermined position of a predetermined transport packet in line units, and the predetermined transport packet Transmission means for transmitting the multiplexed audio data and video data to the data transmission device on the receiving side via an ATM communication line.

Preferably, the data transmission device on the receiving side separates the audio data and the video data from the receiving means for receiving the transport packet from the ATM communication line and the received transport packet. It has audio / video data separating means, and audio / video data assembling means for assembling the separated audio data and video data into the data format of the D2 system.

[0014]

According to the data transmission method of the present invention, the D2 type audio / video data is transmitted from the transmitting side to the receiving side through the ATM communication line. On the transmitting side, only audio data and video data are separated from the D2 audio / video data on a line-by-line basis, and data that is not necessary for playback is deleted to reduce the amount of data. The data rate is AAL1 protocol. Make sure that the value is compatible (132.8 Mbps or less).

The separated audio data, video data and, if necessary, other data are multiplexed at a predetermined position of a predetermined transport packet. The audio data and the video data multiplexed in the transport packet are placed on the payload portion of the ATM cell to
Send to M communication line.

The receiving side sequentially receives ATM cells from the ATM communication line and separates the transport packet from the payload portion of the ATM cells. Further, audio data, video data and other data are separated from the transport packet. The separated audio data and video data are supplemented with unnecessary parts deleted on the transmitting side, and D2
Plays the audio and video data of the system.

[0017]

First Embodiment A first embodiment of the present invention will be described below.
FIG. 1 is a diagram showing a configuration of a data transmission system 1 according to the present invention. As shown in FIG. 1, the data transmission system 1
The data transmission devices 3a to 3f, to which the VTR devices 14a to 14f are respectively connected, are connected to each other via an ATM communication line 2 that provides a transmission line of the AAL1 protocol to them. Data transmission devices 3a-3
f mutually transmits predetermined transmission data, for example, audio / video data for a program or relay, via the ATM communication line 2.

It should be noted that 155.52 MHz supplied from the ATM communication line 2 to the data transmission devices 3a to 3f, respectively.
Line clock NC used when processing the ATM cell as 8-bit parallel data by dividing the clock of
The frequency of LK is 19.44 MHz (155.52 / 8)
It is. On the other hand, an internal clock 4f _sc used in the data transmission devices 3a to 3f when transmitting by the SDI system
Is about 14.3 MHz. If each is correct,
The frequency of these clocks is an integer ratio (NCLK: 4f _sc
= 1188: 875).

The VTRs 14a-14f use the internal clock 4
SD2 method which is an improved SDI method or SDDI method by recording / reproducing D2 standard digital audio / video data in synchronization with f _sc (hereinafter simply referred to as SDI method)
Data transmission device 3 in 143 Mbps serial format
Output to each of a to 3f.

FIG. 2 shows the data transmission device 3a shown in FIG.
3 f are transmission packets (SSCU-PDU packets, hereinafter referred to as “PDU”, which are mutually transmitted via the ATM communication line 2.
FIG. 3 is a diagram showing a configuration of “packet”). In addition,
The number attached to the left of the PDU packet indicates the byte length of each data, and the table attached to the right of the PDU packet indicates the content of each corresponding data.

In the PDU packet, the data TRS has FFh, 00h, and 00h as contents, and indicates the head position of the PDU packet. The data TRS, ancillary data (ANC; ANCillary) area and video data (VID)
It is prohibited that the data included in the PDU packet has a value of 00h or FFh, except for data inserted every 5 bytes in the (EO) area.

Each of the data RTS1 and RTS2 contains the synchronous data RTS having a 6-bit value obtained by subtracting 832 from the count value of the internal clock 4f _sc for the 1188 cycles of the external clock NCLK. However, since the transmission packet is transmitted at the time of 910 cycles of the internal clock 4f _sc , two count values may appear during the transmission of one transmission packet. Data RTS1, RTS2
The above two areas are secured to cope with such a case.

The data RTS1 and RTS2 are data transmission devices 3 on the receiving side (in the case where one of the data transmission devices 3a to 3f is not specified below, the data transmission devices 3
Etc.) is used to establish network synchronization. A valid bit V (Varid) is entered in the sixth bit of the data RTS1 and RTS2, and the content of the valid bit V is, for example, a logical value 1 when these data are valid and when they are not valid. Has a logical value of 0. Further, in order to prevent the data value from becoming 00h and FFh, the logically inverted value of the valid bit V is added as the seventh bit.

The data LNID (Line Number ID) is used to identify the audio / video data of the transmission data included in the ancillary data area and the video data area in the same PDU packet, and the 0th to 2nd bits. Indicates a field number (FN; Field Number) indicating a field including audio / video data, and third to seventh bits having a value of 0 to 31 indicate a line number (LN) indicating a line including audio / video data. ; Line Number).

The data LN1 takes a value in the range of 1 to 525, and is used together with the data LNID1 for identifying audio / video data within the range of 2 fields. The 1st byte and the 2nd byte of the data LN1 have the 0th to 4th bits and the 5th bit of the numerical value, respectively.
9th bit is entered, and the 5th bit of each contains the logically inverted value of the 4th bit for the same reason as the valid bit V of the data RTS1 and RTS2.

The data LNID2 and LN2 are, for example, when the time at which the data transmission device 3 on the receiving side processes the transmitted transmission data is determined, for example, the received transmission data is converted into a program being broadcast in real time. When used, the data transmission device 3 on the transmission side is used when compensating for a transmission delay time occurring in transmission data (transmission packet) in the ATM communication line 2 or the like. That is, the data LNID2, L
N2 is for the audio / video data included in the same PDU packet, the VTR device 14 advances the transmission data by several lines to compensate the transmission delay time in the television broadcasting station on the transmission side, Indicates whether the data transmission device 3 has transmitted this transmission data. The data LNID
The details of the contents of 2 and LN2 are the same as those of the above-mentioned data LNID1 and LN1.

By referring to the data LNID2 and LN2, the transmission device 3 on the receiving side can identify the shuffling method and the like from the audio / video data included in the ancillary data area and the video data area.
That is, of the audio / video data, a shuffling block (every 23 lines, etc.) of a video data portion is discriminated from the data LNID2 and LN2, and deshuffling is performed for each shuffling block.

The data Flag has packet table (PT) data indicating the data amount of the ancillary data portion and the video data portion in the 0th to 3rd bits. The fourth to seventh bits include bits sb0 to sb3. These bits sb0 to sb3 are used to convey the shuffling method on the encoder side.

Data RS422-ch1, RS422-
The ch2 is used, for example, for transmission of control data or the like using the RS422 between computers (not shown) respectively connected to the data transmission devices 3 on the transmission side and the reception side. Data RS422-ch1, RS422-ch
In the 0th to 3rd bits of 2, either the upper 4 bits or the lower 4 bits of the data to be transmitted are entered,
The fourth bit contains a bit UL (Upper / Lower) that becomes 1 when the data contained in the 0th to 3rd bits is the upper 4 bits and becomes 0 when the data is the lower 4 bits. For the same reason as the valid bit V of the data RTS1 and RTS2, the logical inversion value of the fourth bit is entered in the fifth bit. Further, in the 6th bit, the data RS422-ch
1, a valid bit V indicating whether or not RS422-ch2 is valid is added.

The data VOICE contains voice data used for communication and the like. For example, the audio data can be sampled at a sampling frequency substantially equal to the sampling frequency of a PCM encoding device used for general telephone communication, and the horizontal synchronization signal ( 15.75K
Hz) 8 bits are generated, one for every two cycles. Therefore, one audio data is 1 for each cycle of the horizontal sync signal.
It will be transmitted over two generated PDU packets. In the case shown in FIG. 2, the high-order 4 bits or low-order 4 bits of the audio data are put in the 0th to 3rd bits of the data VOICE.

Further, in the 4th bit, the data RS42
Similarly to 2-ch1 and RS422-ch2, the 0th to 3rd
A bit UL indicating whether the bit data is the upper 4 bits or the lower 4 bits is inserted, and the fifth bit is
For the same reason as the valid bit V of the data RTS1 and RTS2, the logical inversion value of the fourth bit is inserted, and further, the valid bit V indicating whether or not the audio data is valid is added.

Further, the sixth and seventh bits are bits 8F1 and 8F2 (8F is a bit used for measuring the delay time given to the PDU packet by the internal circuit of the data transmission device 3 and the ATM communication line 2). (Abbreviation of 8 Frame)
Goes in. The data put in the data LNID2 and LN2 is calculated based on the delay time measured using these bits 8F1 and 8F2.

The spare data is an area reserved as a spare in case another use occurs.
Similarly to 1 and RTS2, the logic inversion value of the 6th bit is put in the 7th bit so that the value is neither 00h nor FFh. Data CRCC1, CRCC2, C
The error correction code of the preceding data area is put in each RCC3. Similar to the data RTS1 and RTS2, the logic inversion value of the sixth bit is put in the seventh bit so that the value is neither 00h nor FFh.

The word length of the ancillary data area is, for example, 69 words, and the word width is converted by the word width conversion unit 410 of the word width conversion circuit 44 described above.
S / EBU data is entered. For example, the word width conversion circuit 44 converts 55 words of AES / EBU data into 8
When converted to bits, the 8-bit parallel data obtained as a result of the conversion is 68 words and 6 bits.

In such a case, in order to prevent the prohibition code (00h, FFh) from being generated, the 2-bit value 01 or 10 is put in the remaining 2 bits. The entered 01 or 10 is discarded when the PDU packet is reproduced in the data transmission device 3 on the receiving side. In this area, the AES / EBU data is in the order of the lower word in front of the PDU packet and the upper word in back.

In the video data area, from the word width of 1 word 10 bits conforming to the SDI system to the image data of 8 bits 1 word conforming to the ATM communication line 2, the data mainly relating to the video is of the D2 system. It is put in line units of video data. The video data is in the order of the lower byte in front of the PDU packet and the upper byte in the rear.

The ancillary data area and the video data area of the PDU packet have variable lengths, and these areas may not include valid data. In addition, the data RS422-ch1, VOICE, etc., are valid bits V
Therefore, for example, when only the valid data V of the data VIOCE is 1 and the valid data V of the other data is 0, only the data VOICE is valid and all the other data are invalid. means.

The relationship between the transmission data multiplexed in the ancillary data area and the video data area of the PDU packet and the D2 audio / video data input to or output from the VTR device 14 will be described below. FIG. 3 is a diagram for explaining the structure of D2 audio / video data. 52
The data amount of the header data of the D2 system corresponding to a system of 5 lines and 29.97 frames / sec is 16 words x 8 bits for each horizontal synchronization period (1 line), so the data rate is as shown in the following formula. It becomes 2 Mbps.

[0039]

## EQU1 ## 16 × 8 bits × 525 lines × 29.97 frames = 2 Mbps (1)

In a system of 525 lines and 29.97 frames / sec, since the number of pixels included in one line is 910 and the data per pixel is 10 bits, the data rate is as shown in the following equation. To 143 Mbp
s.

[0041]

## EQU00002 ## 910 pixels.times.10 bits.times.525 lines.times.29.97 frames = 143 Mbps (2)

However, as shown in FIG. 3, there is an unnecessary portion in the audio / video data of the D2 system, and the ancillary data (audio data), the video data (video data) and the header data shown by the diagonal lines in FIG. Only is needed for audio and video playback on the receiving side. FIG.
The data rates of the ancillary data, the video data, and the header data shown in (1) are as follows.

[0043]

## EQU00003 ## Data amount per second of ancillary data part a 21.times.10 bits.times.12 lines.times.29.97 frames.times.2 = 0.15 Mbps (3)

[0044]

## EQU00004 ## Data amount per second of ancillary data part b 376 × 10 bits × 6 lines × 29.97 frames × 2 = 1.3 Mbps (4)

[0045]

## EQU00005 ## Data amount per second of ancillary data part c 55.times.10 bits.times.254 lines.times.29.97 frames.times.2 = 8.4 Mbps (5)

[0046]

## EQU00006 ## Data amount per second of video data part d 768 × 8 bits × (254 + 253) lines × 29.97 frames = 93.3 Mbps (6)

[0047]

[Equation 7] 1 of video data section and ancillary data section
Total data amount per second e a + b + c + d = 0.15 + 1.3 + 8.4 + 93.3 = 103.2 Mbps (7)

Further, when header data is added, the data rate of the ancillary data, video data and header data becomes 105.2 Mbps as shown in the following equation.

[0049]

2 + 103.2 = 105.2 Mbps (8)

As described above, in the ancillary area of the PDU packet and the video data, an unnecessary portion is removed from the D2 audio / video data (total 143 Mbps).
Since data of 55.2 Mbps is multiplexed and an unnecessary portion is removed, there is a margin in transmission data, and it is possible to transmit voice / video data of the D2 system via an ATM communication line.

Since the audio / video data has a periodicity as shown in FIG. 3, it can be multiplexed in a PDU packet in a fixed processing method line by line on both the transmitting side and the receiving side. . Therefore, the hardware configuration is simple. By multiplexing the transmission data with other data such as RTS data in the PDU packet described above and transmitting the data, not only the transmission data is transmitted, but also useful for processing the transmission data on the receiving side. Data can also be transmitted.

In addition to the first embodiment, in the data transmission system 1 according to the present invention, the number of data transmission devices 3 may be increased or decreased, or the types of data to be multiplexed in PDU packets may be further increased. Various configurations such as the above configuration can be adopted.

[0053]

[Second Embodiment] A second embodiment will be described below. In the second embodiment, the data transmission method according to the present invention shown in the first embodiment is simplified. For example, from the D2 audio / video data shown in FIG. 3, 10.2 Mbps (= 14).
This is a method of deleting data for 3 to 132.8 Mbps) or more by a predetermined method and transmitting as it is using the transport packet shown in FIG.

As described above, the AAL of the ATM communication line 2
The effective transmission data rate by one protocol is 13
It is 2.8 Mbps. Therefore, D2 of 143 Mbps
The audio / video data (transmission data) of the D2 system is transmitted by the ATM communication line 2 by compressing the video / audio data of the system at a very low compression rate by the difference between these values, or by omitting a part of the data. Can be transmitted via. Note that in SMPTE-259M, some predetermined words are inserted in the D2 format, and these words do not necessarily have to be transmitted. Therefore, deleting such a word is considered as a method of partially missing the data.

The transport packet shown in FIG.
Data TRS, RTS, Flag, FN, LN and D
The two types of audio / video data are multiplexed line by line. The data TRS, RTS, Fla shown in FIG.
g, FN and LN are the same as the corresponding data of the PDU packet shown in FIG.

Since the data amount of the data TRS, RTS, Flag, FN, LN can be ignored compared to the data amount of the audio / video data, even if these data are multiplexed, the transmission throughput will not be affected. Absent. By using the transport packet shown in FIG. 4, the processing related to the transmission becomes simpler than that shown in the first embodiment, and the hardware configuration can be simplified.

[0057]

Third Embodiment As the third embodiment of the present invention, the configuration of the data transmission devices 3a to 3f will be described below. FIG.
It is a figure which shows the structure of the data transmission apparatuses 3a-3f shown in FIG. As shown in FIG. 5, each of the data transmission devices 3a to 3f is composed of a transmission unit 5 and a reception unit 6. From the reception unit 6 to the VTR devices 14a to 14f, the reception unit 6 receives the PDU packet. The separated transmission data (reception data) RVD of the D2 system is input to the VTR device 14
a to 14f are reproduced according to the control of the transmission unit 5 via the control signal VC, and are output to the transmission unit 5 as transmission data (transmission data) PVD of the D2 method. In addition, the receiving unit 6
From the transmitter 8 to the bit 8F1, which is received by the receiver 6.
8F2 is supplied.

FIG. 6 is a diagram showing the structure of the transmitting unit 5 shown in FIG. As shown in FIG. 6, the transmitter 5 includes a clock generator 12, a digital video tape recorder (VT).
R) 14, RTS generation device 16, transmission device (TX) 18
And a delay processing circuit 22.

The clock generator 12 is a 14.3 MH used in the transmitter 5 by using, for example, a crystal oscillator.
An internal clock 4f _{sc of} z and a sync signal SYNC corresponding to a horizontal sync signal and a vertical sync signal of the video signal are generated and supplied to the VTR 14, the RTS generator 16 and the transmitter 18. The VTR 14 records / reproduces digital audio / video data of D2 standard in synchronization with the internal clock 4f _sc , and sends it to the transmitter 18 in a 143 Mbps serial format by the SDI system or the SDDI system (hereinafter simply referred to as SDI system). Output.

The RTS generator 16 uses the ATM communication line 2
It shows the actual integer ratio of the frequency of the internal clock 4f _{sc to} the frequency of the line clock NCLK supplied from the device, and generates synchronization data RTS (Residual Time Stamp) used for establishing synchronization with the transmission units 5 and 30. The delay processing circuit 22 includes the bits 8F1, 8 input from the receiving unit 6.
The delay time measurement process shown in FIG. 5 is performed based on F2.

FIG. 7 is a diagram showing the configuration of the transmission device 18 shown in FIG. As shown in FIG. 7, the transmission device 18 is
It is composed of a first block 180 which operates in synchronization with the internal clock 4f _sc and a second block 210 which operates in synchronization with the line clock NCLK.

The first block 180 includes a serial / parallel conversion circuit (S / P circuit) 182, a first switch circuit (SW1) 184, and a second switch circuit (SW2) 1.
86, rounding circuit 188, shuffling circuit 1
90, a first FIFO circuit 192, a word width conversion circuit (10 → 8) 194, a second FIFO circuit 196, a timing generation circuit a200, a timing generation circuit b20.
2, control circuit 204 and reference signal generation circuit 2
It is composed of 06. The second block 210 includes a multiplexing circuit (MUX) 212, a third FIFO circuit 214, a control circuit 216, and a timing generation circuit c21.
8.

In the first block 180, the timing generation circuit a200 determines that the other data transmission devices 3a to 3f.
When the data is not transmitted from (default), the video data (black burst data) corresponding to the black burst is generated at the operation timing based on the data RTS having the value. The reference signal generation circuit 206 is a circuit outside the first block 180, generates black burst data similarly to the timing generation circuit a200, and outputs it to the terminal a of the switch circuit 184.

The S / P circuit 182 converts the 1-bit serial format SDI transmission data input from the VTR device 14 into a 10-bit parallel format and outputs it to the terminal b of the switch circuit 184. Switch circuit 18
Reference numeral 4 denotes a reference signal generation circuit 206 which selects the terminal b side to output the output data of the S / P circuit 182 when the transmitting unit 5 transmits data, and selects the terminal a side otherwise. Switch circuit 1 to output black burst data
Output to 86.

The switch circuit 186 is the switch circuit 18
4 selects the video data portion of the output data (transmission data) of the S / P circuit 182 selected from the S / P circuit 182 of the audio / video data of the D2 system shown in FIG.
It outputs to 88, selects an ancillary data part, and outputs to the word width conversion circuit 194. The rounding circuit 188 converts the data (video data) corresponding to the video data portion shown in FIG. 3 into 8-bit parallel format data (rounds) and sends the data to the shuffling circuit 190. Output. The control circuit 204 handles the header data shown in FIG.

The shuffling circuit 190 receives the 8-bit parallel signal input from the rounding circuit 188,
When a data error occurs in the ATM communication line 2, the data is rearranged in an order that facilitates interpolation and is output to the FIFO circuit 192. The word width conversion circuit 194 converts the data (voice data) corresponding to the ancillary data portion input from the switch circuit 186 shown in FIG. 3 into an 8-bit parallel format, and outputs it to the FIFO circuit 196.

The FIFO circuits 192 and 194 respectively read the data in synchronization with the internal clock 4f _sc and sequentially output the data in synchronization with the line clock 4f _sc .
The data is transferred from the block 180 to the second block 210. The control circuits 204 and 216 monitor the addresses to which data is written and the addresses from which data is read in the FIFO circuits 192 and 194, respectively, and control these addresses. Furthermore, the first block 1
80 is data L based on bits 8F1, 8F2, etc.
N1, LNID1, LN2, LNID2 and data F
lag (FIG. 2) is generated and output to the second block 210.

In the second block 210, the timing generation circuit c218 controls the operation timing of the block 210 based on the line clock NCLK. Data R from the inspection signal applying circuit 16 is sent to the multiplexing circuit 212.
TS is input, and data data LN1, LNID1, LN2, LNID2, Flag are input from the first block 180.
Is entered. The multiplexing circuit 212 multiplexes these data with the audio data and the video data input from the FIFO circuits 192 and 194, and the FIFO circuit 21.
4 is output.

The CRCC addition circuit 213 is for each data CR
The CC is calculated, added, and output to the FIFO circuit 214. The FIFO circuit 214 buffers the output data of the multiplexing circuit 212 and outputs it as transmission data TXD to the ATM communication line 2. As shown in the figure, bits 8F1 and 8F2 from the delay processing circuit 22 are further added to the output data of the FIFO circuit 214 to form the transmission data TXD.

FIG. 8 shows a structure of delay processing circuit 22 shown in FIG. As shown in FIG. 8, the delay processing circuit 22 includes a measurement bit generation circuit 220 and a time difference detection circuit. The measurement bit generation circuit 220
The bit 8F2 shown in FIG. 2 is generated, and the bit 8F2 received by the receiving unit 6 is returned to the bit 8F1. As shown in FIG. 6, the time difference detection circuit 222 detects the time difference between the bit 8F1 received by the reception unit 6 and the bit 8F2 generated by the measurement bit generation circuit 220, and the transmission delay time T
d is calculated, the VTR device 14 is controlled via the control signal VC, and advance control is performed.

FIG. 9 shows the configuration of the receiving unit 6 shown in FIG.
FIG. As shown in FIG. 9, the receiving unit 6 is a receiving device.
(RX) 32, VTR 34, clock controller 36 and
And clock generator 38, and data on the transmission side
Receives PDU packets transmitted from transmission device 3
Based on the synchronous data RTS and the line clock NCLK.
Then, the internal clock 4f of the data transmission device 3 on the transmission side
_scInternal clock 4f synchronized with_scPlay the PDU package
Separated from audio / video data (transmission data)
To record.

FIG. 10 is a diagram showing the configuration of the receiving device 32 shown in FIG. As shown in FIG.
Is composed of a first block 320 that operates in synchronization with the line clock NCLK and a second block 350 that operates in synchronization with the internal clock 4f _{sc. From} a PDU packet received as reception data RXD from the ATM communication line 2. , Separate each data and transmission data, and VT the transmission data among the separated data as the reception data RVD.
It outputs to the R device 14, and outputs bits 8F1 and 8F2 to the delay processing circuit 22.

The first block 320 includes an input data control circuit 322, a first register circuit 324, a CRCC calculation circuit 326, adder circuits 328a and 328b, a first memory circuit 330, a second memory circuit 332 and a second block. Register circuit 334, third register circuit 336, control circuit 338, and timing generating circuit d340.

The second block 350 includes an output data control circuit 352, a fourth register 354, a first reference signal generation circuit 356, a deshuffling circuit 358, a concealment circuit 360, a first error correction circuit 362 and a FIFO circuit 364. , A second error correction circuit 366, a switch circuit 368, a timing generation circuit e370, a second reference signal generation circuit 372, a switch circuit 374, a parallel / serial conversion circuit (P / S circuit) 376, and a control circuit 378. It

The PDU packet received by the receiving device 32 from the ATM communication line 2 includes the input data control circuit 322, the first register circuit 324 and the CRCC calculation circuit 326.
Is input to The first register circuit 324 converts the received 8-bit parallel format PDU packet into a 64-bit parallel format. The CRCC calculation circuit 326 is
The calculation processing relating to each data CRCC (FIG. 2) included in the PDU packet is performed, and the calculation result is output to the addition circuit 328a. The CRCC calculation circuit 326 converts the transmission data ^Xn + ^Xn-1 + ^Xn-2 + ... + X + 1 into G (X).
= X ¹⁴ + X ² + X + 1, an error is detected when the remainder is other than 0, and the calculation result is set to the logical value 1 and output.

The input data control circuit 322 determines, based on each data included in the input PDU packet, write flag data (a; 8-bit parallel data with all bits having a logical value of 0, each bit being a PDU packet). (Corresponding to 1 byte of) is generated and output to the addition circuit 328b. The adder circuit 328b is the first register circuit 3
Write flag data is added to the output data of 24
Output in bit width.

The input data control circuit 322 also generates read flag data (b) of 9 bits × 8 words. After reading the read flag data, the input data control circuit 322 sets only the parity bit to the logical value 1 and all the other bits to the logical value 0, and sets the number of lines (525) ×
The PDU packet is written into the memory circuit 332 having an address space of packet length × 9 bits. The reason why the input data control circuit 322 performs the bit operation of the read flag data in this way is to judge that the necessary data has not arrived when the read flag data of the read data has the logical value 1. Note that the read flag data has a logical value of 0 if it has been written before reading.

The register circuit 334 collects 8 pieces of 9-bit data including 8 bits of received data and 1 bit of flag data corresponding to the received data as 72-bit data from the memory circuit 332 in synchronization with the line clock NCLK. The data is read and output to the register 354 in synchronization with the internal clock 4f _sc .

The input data control circuit 322 also outputs write flag data to the adder circuit 328a (c).
The adder circuit 328 a adds write flag data to the calculation result of the CRCC calculation circuit 326 and returns it to the input data control circuit 322. The input data control circuit 322 outputs the calculation result with the write flag data added to the memory circuit 330.
(D).

The register circuit 336 is the memory circuit 332.
The addition result of the addition circuit 328a stored in the internal clock 4 is read in synchronization with the line clock NCLK.
Output in synchronization with f _sc . Control circuit 338, 3
78 is a control circuit 204, 21 of the transmitter 18.
6 manages the write addresses and read addresses of the register circuits 334 and 336 in the same manner as 6 (FIG. 7).

In the second block 350, the timing generation circuit e370 controls the operation timing of each part of the second block 350 based on the internal clock 4f _sc . The reference signal generation circuit 372 generates and outputs a reference signal. The reference signal generation circuit 356 generates a reference signal and outputs it to the terminal a of the switch circuit 374. The reference signal generated by the reference signal generation circuits 372 and 356 is a signal that does not contain video data and ancillary data and that makes the screen black after reproduction.

The data output from the register circuit 334 is input to the register 354. On the other hand, the data output from the register circuit 336 is the output data control circuit 35.
2 is input. The register circuit 354 transfers each word of the data corresponding to the ancillary data section shown in FIG. 3 (voice data multiplexed in the ancillary area shown in FIG. 2) to the lower 2 bits and its parity bit (a), It is decomposed into the upper 8 bits (b) and its parity bit and output to the input data control circuit 322.

The output data control circuit 352 sends to the deshuffling circuit 358 data corresponding to the video data section shown in FIG. 3 (video data multiplexed in the video data area shown in FIG. 2) and its parity. The error correction circuit 36 outputs (c) the data corresponding to the ancillary data section shown in FIG. 3 (voice data multiplexed in the ancillary data area shown in FIG. 2) and its parity.
2 is output (d) to the data RS42 shown in FIG.
2-ch1, RS422-ch2, VOICE, RTS
Error correction circuit 36
It outputs to 6 (e). That is, the output data control circuit 352 also serves as a separation circuit that separates the audio data and the video data from the PDU packet and the data RS422-ch1 and the like.

By this processing, the output data control circuit 352 a: 8-bit data (1) + flag data (2), b; 2 bits (3) + flag data (4), output of register 2 = CRCC 1 bit Of each data of the + flag data (6), (2), (4), (5),
When any one of (6) has a logical value of 1, a logical value of 1 is newly output as flag data. That is, the output data control circuit 352 performs conversion with a flag of 2 words width of a; (reception data 8 bits + flag data 1 bit) into (ancillary data 10 bits + flag data 1 bit).

The deshuffling circuit 358 performs a process corresponding to the shuffling circuit 190 shown in FIG. 7 based on the data LNID2 and LN2 included in the input data, restores the original order, and sends it to the concealment circuit 360. Output. The concealment circuit 360 interpolates the data of the pixel in which the data error has occurred, for example, by the interpolation of the surrounding pixels, and the switch circuit 374.
It is output to the terminal b.

The error correction circuit 362 receives the input error correction circuit 362, performs error correction on the input audio data, and outputs the error data to the FIFO circuit 364. The FIFO circuit 364 outputs the video data output from the concealment circuit 360 and the error correction circuit 362 output from the error correction circuit 362 to the terminal c of the switch circuit 374 at the same timing.

The switch circuits 374 are connected to terminals a ...
The reference signal from the reference signal generation circuit 356, the output data of the concealment circuit 360, and the FIFO
One of the output signals of the circuit 364 is selected in an order suitable for the audio / video data of the D2 system in the SDI system, and is output to the P / S circuit 376. P / S circuit 3
Reference numeral 76 converts the data input from the switch circuit 374 into serial format data, and outputs the data to the VTR device 14 in synchronization with the internal clock 4f _sc .

The error correction circuit 366 performs error correction on the inputted data such as RS422-ch1 and outputs it to the switch circuit 368. The switch circuit 368 separates the error-corrected data and outputs the data RS422-ch1, RS422-ch2, respectively.
Output as VOICE, RTS and preliminary data.

VTR device 14 (FIG. 9) Internal clock 4f
_The audio / video data RVD input from the P / S conversion circuit 330 is recorded in synchronization with _sc . Clock generator 3
Reference numeral 8 denotes, for example, a voltage controlled oscillator circuit having a crystal oscillator circuit, which generates an internal clock 4f _sc having a frequency according to the control of the clock control device 36 via the clock control signal CC, and each component of the transmission device 30. Supply to. The clock control device 36 generates a clock control signal CC based on the synchronous data RTS input from the reception device 32, and the clock generation device 38 is generated via this clock control signal CC.
Control the frequency of the internal clock 4f _sc generated by the transmission device 30, synchronize the internal clock 4f _sc of the transmission device 30 with the internal clock 4f _sc of the transmission device 10, and further synchronize with the synchronization signal SYNC corresponding to the horizontal synchronization signal and the vertical synchronization signal. Is generated and supplied to the VTR device 14 and the like.

With reference to FIG. 1 again, the data transmission is performed between the data transmission devices 3a and 3b using the transmission unit 5 and the reception unit 6 shown in the third embodiment as an example. The operation of the transmission system 1 will be described. In the data transmission device 3a, the VTR device 14a of the transmission unit 5 is
Plays D2 audio and video data, 143Mbps
Transmitter 18 as serial audio / video data PVD
Output to

On the other hand, the RTS generator 16 has the internal clock 4f _sc generated by the clock generator 12 and A
Based on the line clock NCLK supplied by the TM communication line 2, synchronization data RT indicating how many cycles the internal clock 4f _sc enters during the 1188 periods of the line clock NCLK.
S is generated and sequentially output to the transmission device 18.

The transmission device 18 multiplexes the transmission data PVD and the synchronization data RTS into the PDU packet shown in FIG. 2, and the data transmission device 3b via the ATM communication line 2.
Send to Further, the transmission device 18 performs the advance control shown in FIG. 7 on the VTR device 14a as necessary. The ATM communication line 2 is a data transmission device 3
The ATM cell transmitted from a is transmitted to the data transmission device 3b, and the line clock NCLK is supplied to the data transmission device 3b.

In the data transmission device 3b, the PDU packet transmitted from the data transmission device 3a is received by the reception device 32 of the reception unit 6. The receiving device 32 is
The reception data RVD corresponding to the transmission data PVD of the reception unit 6 of the data transmission device 3a is output to the VTR 14b, and the VTR 14b records this.

The clock controller 36 uses the synchronous data RT
S, the frequency of the internal clock 4f _sc generated by the clock generator 38 based on the internal clock 4f _sc supplied from the clock generator 38 and the line clock NCLK supplied from the ATM communication line 2 The clock control signal CC that is synchronized with the internal clock 4f _sc in the receiving unit 6 of 3b is generated and output to the clock generator 38. The clock generator 38 uses the internal clock signal 4 at a frequency according to the clock control signal CC.
f _sc is generated and supplied to each part of the reception unit 6 of the data transmission device 3b.

As described above, according to the data transmission system 1 of the present invention, the SDI system which is widely used as the infrastructure in the television broadcasting station and the like can be used as the interface of the VTR 14, so that the existing system can be used. The equipment can be easily connected to the ATM communication line.

The circuit configurations and the like of the transmitting unit 5 and the receiving unit 6 shown in the above embodiments are examples, and can be replaced with circuits or the like capable of realizing equivalent functions. Further, although the VTR device has been illustrated as the device connected to the transmission part 5 and the reception part 6, the invention is not limited to this, and for example, an editing device for inputting / outputting data by the SDI system, a relay device or a transmission facility is connected You may.

Further, the PDU packet shown in FIG. 2 is an example, and the present invention can be applied to a transmission method using a transmission packet of another format. Further, the data transmission system 1, the transmitter 5 and the receiver 6 according to the present invention are
In addition to video data, it can be applied to any of these data, or data for information processing.

[0098]

As described above, according to the data transmission method and the apparatus therefor of the present invention, MP can be effectively used without waste in the payload part of the ATM cell.
It is possible to transmit audio / video data such as the EG2 system. Further, according to the data transmission method and the apparatus thereof according to the present invention, audio / video data of the D2 system or the like is transmitted to the AT.
It can be transmitted in conformity with the M system AAL1 protocol.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a data transmission system according to the present invention in a first embodiment.

FIG. 2 is a diagram showing a configuration of a transmission packet (PDU packet) mutually transmitted by the data transmission device shown in FIG. 1 through an ATM communication line.

FIG. 3 is a diagram illustrating a configuration of audio / video data of D2 system.

FIG. 4 is a diagram showing a structure of a transport packet in the second embodiment.

FIG. 5 is a diagram showing the configuration of the data transmission device shown in FIG. 1 in a third embodiment.

6 is a diagram showing a configuration of a transmission unit shown in FIG.

FIG. 7 is a diagram showing a configuration of a transmission device shown in FIG.

8 is a diagram showing a configuration of a delay processing circuit shown in FIG.

9 is a diagram showing a configuration of a receiving unit shown in FIG.

FIG. 10 is a diagram showing a configuration of a receiving device shown in FIG.

[Explanation of symbols]

1 ... Data transmission system, 2 ... ATM communication line, 3, 3
a to 3f ... Data transmission devices 3, 14, 14a to 14f ...
VTR device, 5 ... Transmitter, 12 ... Clock generator, 1
6 ... RTS generation device, 18 ... Transmission device, 180 ... First block, 182 ... S / P circuit, 184 ... Switch circuit, 186 ... Switch circuit, 188 ... Rounding circuit, 190 ... Shuffling circuit, 192 ... FIFO Circuit, 194 ... Word width conversion circuit, 196 ... FIFO circuit, 200 ... Timing generation circuit a, 202 ... Timing generation circuit b, 204 ... Control circuit, 206 ... Reference signal generation circuit, 210 ... Second block, 212 ... Multiplexing Circuit, 214 ... FIFO circuit, 216 ... Control circuit, 218 ... Timing generating circuit c, 22 ... Delay processing circuit, 220 ... Measurement bit generating circuit, 222 ... Delay processing circuit, 6 ... Receiving section, 32 ... Receiving device, 320 ... first
Block 322 ... Input data control circuit, 324 ... Register circuit, 326 ... CRCC calculation circuit, 328 ... Addition circuit, 330 ... Memory circuit, 332 ... Memory circuit, 33
4 ... Register circuit, 336 ... Register circuit, 338 ... Control circuit, 340 ... Timing generating circuit d, 35
0 ... Second block, 352 ... Output data control circuit, 3
54 ... Register circuit, 356 ... Reference signal generating circuit, 35
8 ... Deshuffling circuit, 360 ... Conseal circuit, 3
62 ... Error correction circuit, 364 ... FIFO circuit, 366
... error correction circuit, 368 ... switch circuit, 370 ... timing generation circuit e, 372 ... reference signal generation circuit, 37
4 ... Switch circuit, 376 ... P / S circuit, 378 ... Control circuit, 36 ... Clock control device, 38 ... Clock generation device

Front page continued (72) Inventor Takayuki Takeda 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (5)

[Claims] 1. A data transmission method for transmitting D2 audio / video data from a transmitting side to a receiving side via a synchronous transmission mode (ATM) communication line, wherein the transmitting side uses D2 audio / video. Data for multiplexing data at a predetermined position of a predetermined transport packet line by line, and transmitting the audio / video data multiplexed in the predetermined transport packet to the receiving side via the ATM communication line. Transmission method. 2. The transmitting side separates only audio data and video data from D2 audio / video data in line units, and separates only the audio data and video data into predetermined transport packets in line units. 2. The data transmission method according to claim 1, wherein the data is multiplexed at a predetermined position of. 3. The receiving side receives the transport packet from the ATM communication line, separates the audio data and the video data from the received transport packet, and separates the audio data and the video data. The data transmission method according to claim 2, wherein the data is reassembled into the D2 format. 4. A data transmission device for transmitting D2 audio / video data from a transmission side data transmission device to a reception side data transmission device through an ATM communication line, wherein the transmission side data transmission device is , Audio / video data separating means for separating only audio data and video data from audio / video data of the D2 system in line units, and the separated audio data and video data in a predetermined transport packet for each line unit. Multiplexing means for multiplexing at a predetermined position and transmitting means for transmitting the audio data and the video data multiplexed in the predetermined transport packet to the data transmission device on the receiving side through an ATM communication line. Data transmission device having. 5. The data transmission device on the receiving side comprises a receiving means for receiving the transport packet from the ATM communication line, and an audio / voice separating device for separating the audio data and the video data from the received transport packet. The data transmission apparatus according to claim 4, further comprising: video data separating means; and audio / video data assembling means for assembling the separated audio data and video data into the D2 format data format.