JPH0936787A - Interference compensation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the convergence to a synchronization state by providing an output of a signal or a prescribed value obtained by holding a correlation signal outputted from N-sets of taps, respective, based on an asynchronizing signal outputted from a demodulator. SOLUTION: A multiplier 21 multiplies an input base band signal with an error signal E from a subtractor 16 in each of taps 31-3n to obtain an instantaneous correlation value. The obtained instantaneous correlation value is fed to an integration device 22, where the signal is averaged in terms of time and correlation signals C1 -CN. are generated. The signals C1 -CN are fed to a limit value control circuit 17 and also to a corresponding limit device 25. After the correlation is limited below a limit value by limit signals L1 -LN received by the circuit 17, the result is fed to the multiplier 23 as a tap coefficient, in which an input base band signal is multiplied as a tap signal. The tap signal is added by an adder 14 and the result, is fed to a discrimination device 15 and a subtractor 16, from which an error signal E is outputted.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an interference compensator,
In particular, the present invention relates to an interference compensator used in a demodulator for digital radio communication of single frequency relay.

[0002]

2. Description of the Related Art A single frequency relay system is being put to practical use in order to improve frequency utilization efficiency in a digital wireless communication system. Since this single frequency relay system uses the same transmission frequency and reception frequency, the frequency utilization efficiency can be doubled as compared with the conventional dual frequency relay system, but it also has the drawback of increasing the amount of interference due to antenna coupling. .

Therefore, in this single frequency relay, an interference compensator for reducing the amount of interference due to antenna coupling has been conventionally used. Waveform equalization by a transversal filter is considered for this conventional interference compensator (for example, John G. Proakis, "Digital Communications", McGRA
Published by WHILL, p.357-381).

FIG. 7 is a block diagram showing an example of a conventional interference compensator using a transversal filter having an N tap structure (N is a natural number). In the figure, the number of taps N is determined by the nature of the interference wave that can occur, but in single frequency relay,
Since long-term differential interference having a wide time difference (μs order) such as overreach interference, intra-station interference, and delayed interference described in FIG. 8 poses a problem, a value of several tens to several hundreds of taps is usually selected.

Here, the overreach interference is a forward echo interference which is received by the own station 123 by skipping the station 122 one hop before the station 121 two hops before, as shown in FIG. Further, the intra-station interference is delayed echo interference generated by the transmission and reception coupling of the antenna of the self station 123, and
Reflective interference is delayed echo interference caused by reflection on a reflector 125 (a wall surface of a distant building, etc.).

In FIG. 7, a transversal filter includes a first tap 11, a second tap 12 to an Nth tap 1n for performing interference compensation on a baseband signal input from a demodulator to a terminal 1, and each tap 11 of these. An adder 14 that adds the output signals of 1n to output an equalized signal, a determiner 15 that estimates a transmission signal that may have been sent from the output equalized signal of the adder 14 and outputs a determination signal, and The subtracter 16 outputs an error signal E which is an equalization residual from the difference between the equalization signal and the determination signal. The judgment signal is output to the terminal 2.

The first tap 11 is a first multiplier 21 for obtaining an instantaneous correlation value by the product of the input data signal from the terminal 1 and the error signal E, and the correlation value signal is obtained by averaging the instantaneous correlation values over time. It is composed of an integrator 22 for outputting and a second multiplier 23 for outputting a first tap signal by a product of an input data signal and a correlation value signal (tap coefficient). This correlation value signal is called the tap coefficient of the first tap.

Each of the second tap 12 to the Nth tap 1n has a delay element 24 for adjusting the time of tap input, and otherwise performs the same operation with the same configuration as the first tap 11. . A method of obtaining such a correlation signal is called an MSE algorithm. According to the MSE algorithm, each tap of the transversal filter operates so as to minimize the root mean square value of the error signal.

As described above, the input data signal containing various interferences is subjected to interference compensation by the transversal filter. The tap coefficient for interference compensation is automatically determined by the MSE algorithm of the circuit shown in FIG.

[0010]

When the interference compensator is composed of a normal transversal filter, the following two problems occur. The first problem is poor convergence.
In a normal transversal filter, a fixed limit value (weighting) is given to each tap in order to improve convergence. As the limit value, for example, there is a method of using the absolute value of the delay time difference from the center tap of the transversal filter and setting the limit value to 1 / A when the time difference is A clock.

However, in this method, when the transversal filter is used as an interference compensator only for the purpose of improving the frequency characteristic, a large tap coefficient may occur regardless of the time difference from the center tap. It is not possible to set a limit value unnecessarily. As a result, convergence becomes very difficult when all tap coefficients move at full scale.

The second problem is that the quantization noise increases as the number of taps increases. When the quantization noise power generated at each tap is P (NO), the quantization noise P (N) generated in the entire transversal filter has the following value.

P (N) = N × P (NO) That is, the quantization noise increases in proportion to the number of taps. As a result, conventionally, the noise resistance of the signal deteriorates.

The present invention has been made in view of the above points,
An object of the present invention is to provide an interference compensator capable of preventing deterioration of convergence and increase of quantization noise due to a large number of taps.

[0015]

According to the present invention, in order to achieve the above object, a baseband digital signal extracted from a demodulator of a demodulator in a digital wireless communication system and an error signal indicating an equalization error are commonly used. The corresponding limit value signals are input separately, and the tap signal generated based on the correlation value signal whose value is limited according to the input limit value signal and the correlation value signal whose value is not limited are input. The N taps that are output respectively, the adder that adds and synthesizes the tap signals output from the N taps, respectively, and outputs an equalized signal, and the output equalized signal of the adder is output, and a determination signal is output. A decision device, a subtractor that receives the decision signal output from the decision device and the equalized signal, and outputs an error signal that is the difference between the two signals, and a correlation value signal that is output from each of the N taps. A limit value control circuit for individually outputting a signal or a predetermined value obtained based on the asynchronous signal output from the demodulator to N tap values as N limit value signals Is.

Further, the limit value control circuit of the present invention includes N absolute value detection circuits for separately detecting the absolute values of the correlation value signals respectively output from the N taps, and the asynchronous signal from when the asynchronous signal is activated. It is characterized by comprising N holding circuits that hold the output absolute value of the absolute value detection circuit immediately before the asynchronous state until the cancellation, and output a predetermined value as a limit value signal when the asynchronous signal is canceled.

Alternatively, the limit value control circuit of the present invention is N
N absolute value detection circuits that separately detect the absolute values of the correlation value signals output from the respective taps, the output absolute value signals of the N absolute value detection circuits, and a predetermined threshold value are separately provided. And N comparators that output the comparison result of whether or not the absolute value signal is greater than or equal to the threshold value, and N absolute value detection circuits immediately before the asynchronous state from when the asynchronous signal is activated to when the asynchronous signal is released. Hold the output value of and output as the limit value signal,
Indicates that the absolute value signal does not exceed the threshold value at the time of synchronization.When the comparison result is output from the comparator, zero is output as the limit value signal, and at the time of synchronization, the absolute value signal indicates the threshold value or more. When the comparison result is output from the comparator, N holding circuits that output a predetermined value that is not limited as a limit value signal are provided.

Generally, the waveform distortion due to fading is
Equalization is possible with a few taps around the center tap. However,
In that case, the tap coefficient and the tap position of the compensator have a feature that they change from moment to moment depending on the propagation conditions. Further, when compensating for the long-term difference interference, although the tap coefficient of the interference compensator temporally changes depending on the propagation condition, the tap position is determined by geographical conditions such as a reflection source, so that there is almost no temporal fluctuation. . That is, the taps other than the periphery of the center tap and the periphery of the tap where there is a long-term difference interference are hardly operating.

Therefore, according to the present invention, when the demodulator is in an asynchronous state, the tap coefficient limit value is increased only around the operating center tap and the tap where there is long-term difference interference, and the other taps are strict. Give a limit value.
That is, in the present invention, a signal obtained by holding the correlation value signals respectively output from the N taps on the basis of the asynchronous signal output from the demodulator or a predetermined value is used as the N limit value signals. The N taps are individually output, the N taps limit the value of the correlation value signal according to the input limit value signal, and the tap signal is generated based on the correlation value signal obtained by this In this state, the tap coefficient (correlation value signal) of N taps is limited. The position of the long-term difference interference can be determined by observing the correlation value signal in the limit value control circuit in the synchronous state and holding the detected position in the asynchronous state.

Further, each tap of the transversal filter performs interference compensation when operating with a certain degree of correlation, but when there is very little correlation,
On the contrary, it may become a noise source. Therefore, in the present invention,
A comparator compares the absolute value signal of the correlation value signal with a predetermined threshold value, considers the tap whose absolute value signal does not exceed the threshold value as a noise source, and sets the limit value signal to that tap to zero. And

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of an interference compensator according to the present invention. In the figure, the same components as those in FIG. 7 are designated by the same reference numerals.

This embodiment is an interference compensator used in a demodulator of a digital radio communication system and having a function of removing interference contained in a baseband digital signal from the demodulator of the demodulator, which is shown in FIG. As shown in
The tap 31, the N tap from the second tap 32 to the Nth tap 3n, the adder 14 that adds the output signals of the taps 31 to 3n and outputs an equalized signal, and the adder 14 sent from the equalized signal. Judgment device 1 for estimating a wax signal and outputting a judgment signal
5, a transversal filter including a subtractor 16 that outputs an error signal that is an equalization residual based on the difference between the equalization signal and the determination signal, and a limit value control circuit 17.

The limit value control circuit 17 includes the taps 31 to 31.
Each tap 3 receives the correlation value signals C _{1 to} C _{N from n} and an asynchronous signal from a demodulator (not shown) input to the terminal 3.
Limit value signals L _{1 to} L _N are output for each of _{1 to} 3n. Further, the taps 31 to 3n are respectively the conventional taps 11 to 1n.
The first tap 31 has a different configuration from the first multiplier 2
1 and the integrator 22, each of which has a limiter 25 that limits the correlation value signal C ₁ input by the limit value signal L ₁ input from the outside. The output of the limiter 25 is used as a tap coefficient. It is configured so that it is supplied to the second multiplier 23 and multiplied with the input signal.

The output correlation value signal C ₁ of the integrator 22 is "-
It is normalized so that it has a real value from 1 ”to“ 1 ”.
The limit value signal L ₁ takes a real value from “0” to “1”, and limits the absolute value of the magnitude of the correlation value signal C ₁ input from the integrator 22 to the limit value.

An example of the input / output characteristics of the limiter 25 is shown in FIG.
Shown in That is, as shown in FIG. 2, the limiter 25 sets the limit value to B (0 ≦ B ≦ 1), outputs the input value as it is when the input value is within the range of B to −B, and the input value is the above-mentioned value. When exceeding the range (when the absolute value of the input value is larger than B), the output value is limited to the upper limit value B or the lower limit value −B. The upper limit value B and the lower limit value −B are variably controlled by a limit value signal L ₁ from the outside.

The second tap 32 to the Nth tap 3n are each provided with a delay element 24 for adjusting the tap input time, and the corresponding limit value signal L ₂ to L ₂ from the limit value control circuit 17. The first tap 31 except that L _N is input to the internal limiter 25 independently of other taps
Is the same as

The limit value signals L _{1 to} L _N are sent to the limit value control circuit 17
Is generated by. The limit value control circuit 17 receives an asynchronous signal (CAR) from a demodulator (not shown) input to the terminal 3.
ASYNC) is used to switch between holding or canceling the absolute value of the correlation value signal. Asynchronous signal generating means itself is known from JP-A-48-17661.

A block diagram of an example of the configuration of the limit value control circuit 17 is shown in FIG. As shown in the figure, the limit value control circuit 17 includes N absolute value detection circuits 41 to 4 in total.
n, and N holding circuits 51 to 5n in total, i
The holding circuit 5i holds the output signal of the absolute value detection circuit 4i of the first (1 ≦ i ≦ N = n).

The absolute value detection circuits 41 to 4n are respectively the first tap 31 to the Nth tap 3 of the transversal filter.
It receives the correlation value signals C _{1 to} C _N from _n as input and outputs the absolute value thereof. The holding circuits 51 to 5n receive the output absolute value signal of the corresponding absolute value detection circuit among the absolute value detection circuits 41 to 4n and the asynchronous signal from the demodulator as inputs, and hold the input absolute value signal when the asynchronous signal is activated, The hold value is output as the limit value signals L _{1 to} L _N until the asynchronous signal is released. Further, when the asynchronous signal is released, the holding circuits 51 to 5n
Outputs a "1" as the limit value signal L ₁ ~L _N.

Next, the operation of the embodiment of the present invention will be described. In FIG. 1, the baseband signal (data signal) input to the terminal 1 from the demodulator (not shown) is supplied to the multipliers 21 and 23 in the first tap 11, while the second tap 12 to the N−th Up to 1 tap, it is branched into 3 via the delay element 24 in each tap, is supplied to the multipliers 21 and 23 in that tap, respectively, is output to the tap in the next stage, and is input in the Nth tap in the final stage. The generated baseband signal is transmitted through the delay element 24 to the multiplier 2
1 and 23.

In each of the taps 31 to 3n, the multiplier 21 multiplies the input baseband signal and the error signal E from the subtractor 16 to obtain an instantaneous correlation value, and the instantaneous correlation value thus obtained is obtained. The correlation value signals C _{1 to} C _N are generated by supplying them to the integrator 22 and averaging them over time. The correlation value signals C _{1 to} C _N are commonly supplied to the limit value control circuit 17, respectively, and are also supplied to the corresponding limiter 25, and the limit value signals L ₁ individually input from the limit value control circuit 17 are supplied thereto. ~
After the magnitude of the correlation value is limited to the limit value or less by L _N , it is supplied to the multiplier 23 as a tap coefficient and is multiplied by the input baseband signal to be a tap signal.

The first tap signal to the Nth tap signal output from each multiplier 23 from the first tap 31 to the Nth tap 3n are added and combined by the adder 14 to be equalized signals, It is supplied to the determiner 15 and the subtractor 16. The determiner 15 estimates the transmission signal and outputs the determination signal to the output terminal 2. The subtracter 16 outputs an error signal E which is an equalization residual from the difference between the equalization signal and the determination signal.

Here, the limit value signals L _{1 to} L _N input to the limiter 25 are the limit value control circuit 17 having the configuration shown in FIG.
Is generated by. That is, the limit value control circuit 17
The absolute value detection circuit 4i detects the absolute value of the correlation value signal C _i shown in FIG. 4A input to the i-th (i is an arbitrary tap number in N taps) absolute value detection circuit 4i. hand,
From this, an absolute value signal as shown in FIG. 4 (B) is output.

In this state, when the "H" level asynchronous signal shown in FIG. 4C is input to the holding circuit 5i, the holding circuit 5i outputs the absolute value signal at that time as shown in FIG. 4D. The value a is held and output to the tap 3i as the limit value signal L _i . As a result, the tap coefficient output from the limiter 25 of the tap 3i to the second multiplier 23 is as shown in FIG.
As shown in FIG. Also, the asynchronous signal is
When the L "level is reached, that is, when the synchronization state is reached, FIG.
As shown in (D), "1" is output from the holding circuit 5i. Similar operations are performed for other taps.

As described above, in this embodiment, since the absolute values of the correlation value signals C _{1 to} C _N when the asynchronous signal is activated are input in the asynchronous state, in the asynchronous state, the correlation immediately before becoming asynchronous. The tap coefficient output to the multiplier 23 is limited by the absolute value of the value signal. On the other hand, in the synchronous state, the limit value signals L _{1 to} L _N input to the limiter 25 are “1”, and therefore each tap is tapped. The limiter 25 of 4 does not limit the tap coefficient.

As described above, when the tap coefficient of several tens of taps moves randomly in the asynchronous state, the output equalized signal of the adder 14, which is the sum of the tap signals, contains a large noise component. As a result, in the conventional interference compensator, the convergence operation performed using the error signal extracted by the subtractor 16 from the equalized signal becomes very difficult.

On the other hand, in the present system, unnecessary taps that are not operating as an interference compensator because they are in an asynchronous state are output to the multiplier 23 by the absolute value of the correlation value signal immediately before becoming asynchronous. Since the tap coefficients to be used are limited, only the necessary taps can be operated. As a result, the noise component due to an erroneous tap coefficient included in the equalized signal has a small value, and the convergence from the asynchronous state to the synchronous state can be improved.

Next, another embodiment of the limit value control circuit 17 will be described. FIG. 5 is a circuit system diagram of another embodiment of the limit value control circuit 17, and FIG. 6 is a signal waveform diagram for explaining the operation of FIG. 5, those parts that are the same as those corresponding parts in FIG. 3 are designated by the same reference numerals. In FIG. 5, the limit value control circuit 17
Are absolute value detection circuits 41 to 4n, comparators 61 to 6n, latch circuits 71 to 7n, OR gates 81 to 8n, 101 to.
10n and inverters 91 to 9n.
Latch circuits 71 to 7n, OR gates 81 to 8n, 101
-10n and the inverters 91-9n comprise the holding circuit.

The comparators 61 to 6n compare the input absolute value signal with a predetermined threshold value. This threshold value is set in order to select a tap that does not contribute to the operation of the transversal filter, and is set to a value of about 0.01 to 0.1, for example. The threshold value preset in the comparators 61 to 6n is determined in consideration of the number of taps and the like. When there are many taps,
Since the quantization noise increases accordingly, the threshold value is reduced to prevent the quantization noise from increasing.

The output signals of the absolute value detecting circuits 41 to 4n are input to the data input terminals of the latch circuits 71 to 7n,
The output signal of the comparator 61~6n to the clock terminal is input, OR gate 81~8n signal ORing the output signal of the comparator 61~6n asynchronous signal by its C _D
A signal which is input to the terminal, and which is obtained by performing a logical sum operation of the signal in which the output signals of the comparators 61 to 6n are phase-inverted by the inverters 71 to 7n and the asynchronous signal is input to the S _D terminal.

When the clock terminals of the latch circuits 71 to 7n change from "L" to "H", the value of the data input terminal D at that time is output from the Q output terminal. In addition, the latch circuits 71 to 7n both have terminals S _D and C _D
When input to H ", the immediately preceding logic value is output from the Q output terminal, and one of the terminals S _D and C _D is" H "and the other is" H ".
When L "outputs a logical value of the terminal C _D from the Q output terminal.

Next, the limit value control circuit 1 having the configuration shown in FIG.
The operation of No. 7 will be described with reference to FIG. The correlation value signal C output from the integrator 22 as shown in FIG.
i (where i is a natural number of 1 to n)
Is supplied to the absolute value detection circuit 4i to be an absolute value signal as shown in FIG. 6B, and then supplied to the comparator 6i to be compared with a predetermined threshold value, and the absolute value signal is thresholded. "L" when it is less than the value, "H" when it exceeds the threshold value
Is output as a signal. FIG. 6C shows this comparator 6i.
The output signal of is shown. In FIG. 6, the threshold value is set to about 0.5 for convenience of illustration.

The output signal of the comparator 6i is the OR gate 8
1 is logically ORed with the asynchronous signal and C of the latch circuit 7i
_While being input to the _D terminal, the phase is inverted by the inverter 9i, the logical sum is calculated with the asynchronous signal by the OR gate 10i, and the result is input to the S _D terminal of the latch circuit 7i. On the other hand, the absolute value detection circuit 4i is connected to the data input terminal of the latch circuit 7i.
Output absolute value signal is input, and an asynchronous signal is input to the clock terminal of the latch circuit 7i. FIG. 6 (D)
Indicates the waveform of this asynchronous signal, and when it is "H", it indicates that it is in an asynchronous state.

As a result, when the latch circuit 7i changes from the synchronous state to the asynchronous state, that is, the asynchronous signal is "
When L "changes to" H ", the value of the absolute value signal immediately before being input to the data input terminal is held until the asynchronous signal is released, and the held value is used as the limit value signal Q.
Output from the output terminal.

On the other hand, when the absolute value signal exceeds the threshold value of the comparator 6i at the time of synchronization, the tap is considered to be in the operating state, and the output signal of the comparator 6i becomes "H". The _CD terminal becomes "H" and the _SD terminal becomes "L", so that the latch circuit 7i outputs "H", that is, "1" from the Q output terminal.

When the absolute value signal does not exceed the threshold value of the comparator 6i at the time of synchronization, the output signal of the comparator 6i becomes "L" assuming that the tap is in the non-operating state, so that C _D The terminal becomes "L" and the _SD terminal becomes "H", so that the latch circuit 7i outputs "L", that is, "0" from the Q output terminal. Thus, from the Q output terminal of the latch circuit 7i is such signal shown in FIG. 6 (E) is taken out, is input as the limit value signal L _i to limiter 25 taps 3i in FIG. Therefore, the tap coefficient supplied by the limiter 25 to the second multiplier 23 of the tap 3i is shown in FIG.
Limited as shown in.

As described above, according to the embodiment of the present invention, the tap is considered to be in the non-operating state in the synchronous state, and when the absolute value of the correlation value signal does not exceed the threshold value, the tap is always operated. By outputting "0" as the limit value signal, the quantization noise generated from the tap output can be eliminated. Also, in the synchronous state and when the absolute value of the correlation value signal is equal to or greater than the threshold value, the tap is considered to be in the operating state, and "1" is always output to determine the magnitude of the tap with respect to the tap coefficient. No restrictions are imposed.

As described in the section of the problem to be solved by the invention, the quantization noise power included in the equalized signal is proportional to the number of taps. In a transversal filter type equalizer for the purpose of compensating for intersymbol interference, since the number of taps is about 10, quantization noise hardly poses a problem.

However, when an interference compensator is intended, the number of taps is from several tens to one as compared with that of a transversal filter type equalizer intended to compensate for intersymbol interference.
00, which is quite large, and fine quantization is required to reduce the quantization noise. for that purpose,
The hardware configuration of the device becomes complicated, and it is not realistic in terms of power consumption, operating speed, and the like. On the other hand, in the interference compensator having the limit value control circuit 17 configured as shown in FIG. 5, the output of the tap that is not in operation becomes zero, so that the unnecessary tap can be prevented from becoming a noise source.

[0050]

As described above, according to the present invention,
When the demodulator is in the asynchronous state, the tap coefficient (correlation value signal) of N taps is limited. Therefore, the noise component due to the erroneous tap coefficient included in the equalized signal is set to a small value, so that the asynchronous state is synchronized. It is possible to improve the convergence to the state.

Further, according to the present invention, for taps whose tap coefficient does not exceed the threshold value, the tap output becomes zero, so that the quantization noise power included in the equalized signal can be reduced, Therefore, it is particularly suitable for application to an interference compensator having a large number of taps.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of input / output characteristics of a limiter in FIG.

FIG. 3 is a block diagram of an example of a limit value control circuit of FIG.

FIG. 4 is a signal waveform diagram for explaining the operation of FIG. 3;

5 is a circuit system diagram of another example of the limit value control circuit of FIG.

6 is a signal waveform diagram for explaining the operation of FIG.

FIG. 7 is a configuration diagram of a conventional example.

FIG. 8 is an explanatory diagram of each interference wave.

[Explanation of symbols]

1 Baseband Digital Signal Input Terminal 2 Judgment Signal Output Terminal 3 Asynchronous Signal Input Terminal 15 Judger 16 Subtractor 17 Limit Value Control Circuit 21 First Multiplier 22 Integrator 23 Second Multiplier 25 Limiter 31-3n Tap 41~4n absolute value detecting circuit 51~5n holding circuit 61~6n comparator 71~7n latch circuit C ₁ -C _N correlation signal L ₁ ~L _N limit value signal

Claims (4)

[Claims] 1. A baseband digital signal extracted from a demodulator of a demodulator in a digital radio communication system and an error signal indicating an equalization error are commonly input, and corresponding limit value signals are individually input. N taps that respectively output a tap signal generated based on a correlation value signal whose value is limited according to an input limit value signal, and a correlation value signal whose value is not limited, and from the N taps An adder that outputs the equalized signal by adding and synthesizing the tap signals that are respectively output, a determiner that receives the output equalized signal of the adder and outputs a determination signal, and an output determination signal of the determination device A subtractor that receives the equalized signal and outputs the error signal that is the difference between the two signals, and a correlation value signal that is output from each of the N taps A limit value control circuit that individually outputs a signal obtained by holding based on the output asynchronous signal or a predetermined value to the N taps as the N limit value signals. Interference compensator. 2. Each of the N taps calculates an instantaneous correlation value by multiplying the error signal by a baseband digital signal extracted from the demodulator.
And an integrator for integrating the first multiplier to output a correlation value signal whose value is not limited, and an output correlation value signal of the integrator having a value according to the limit value signal. A limiter for limiting and outputting; and a second multiplier for multiplying the output signal of the limiter and the baseband digital signal to output the tap signal, further comprising: 2. The second to N-th taps with respect to the input terminal of the baseband digital signal each have a delay element for time adjustment on the input side of the first multiplier. Interference compensator. 3. The limit value control circuit includes N absolute value detection circuits that separately detect the absolute values of the correlation value signals output from the N taps respectively, and the absolute value detection circuits from the time the asynchronous signal is activated to the absolute value detection circuit. The present invention further comprises: N holding circuits that hold the output absolute value of the absolute value detection circuit immediately before the asynchronous state until the asynchronous signal is released, and output a predetermined value as the limit value signal when the asynchronous signal is released. The interference compensator according to claim 1 or 2. 4. The limit value control circuit includes N absolute value detection circuits for separately detecting absolute values of the correlation value signals output from the N taps, and the N absolute value detection circuits. N comparators that separately compare the output absolute value signal of the circuit and a predetermined threshold value and output a comparison result as to whether the absolute value signal is greater than or equal to the threshold value; From the time until the asynchronous signal is released, the output values of the N absolute value detection circuits immediately before the asynchronous state are held and output as the limit value signal, and the absolute value signal exceeds the threshold value at the time of synchronization. When the comparison result indicating that there is no output is output from the comparator, zero is output as the limit value signal, and the comparison result in which the absolute value signal indicates the threshold value or more at the time of synchronization is output from the comparator. The above restrictions are applied when output 3. The interference compensator according to claim 1, further comprising N holding circuits that output a non-predetermined value as the limit value signal.