JPH0936238A - Method and device for reutilizing lsi layout pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately and quickly prepare a new layout by utilizing an already existing layout pattern. SOLUTION: The addition, correction, deletion, etc., of functional cells and wiring to an original LSI circuit are decided (S2) and functional cells to be added and corrected are arranged by securing spaces by deleting patterns which have become unnecessary (S4). A wiring channel graph is prepared (S6) and areas are roughly assigned to wiring routes and through holes on the wiring channel graph (S8). Then partial route correction is performed (S10) and a detailed layout pattern is prepared (S12).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI layout pattern reusing apparatus.

[0002]

2. Description of the Related Art With the increasing variety and functionality of electronic equipment, various demands have been made from LSI users for the specifications of LSI. In order to meet such needs, the LSIs are being made more diversified and have more functions.
To meet more detailed requirements, LSI redesign is required. For example, while the main functional circuit portion of the LSI is left as it is, the design of the memory capacity and some auxiliary circuits such as the interface portion is partially changed according to the user's specifications. There is an increasing need to efficiently design LSIs by responding to such specifications required by users in detail.

Therefore, conventionally, the detailed layout data of the LSI pattern previously designed is used to manually add / delete functional cells and wirings in the lower hierarchy.
Change the design. Here, the functional cell of the lower layer is, for example, an adder (a functional cell of a lower layer) included in an operation block (a functional cell of a higher layer) or a transistor (a lower layer of a functional cell) included in an adder (a functional cell of an upper layer). Function cell of the hierarchy). At the time of this design change, L
It is necessary to modify (change) the layout considering the design rules for SI manufacturing. In addition, since the layout of one part needs to be corrected, the other part needs to be corrected, so that a human error occurs or a considerable work time is required.

As one of the means for coping with this,
A method for reusing an already designed circuit and layout pattern has been proposed. For example, Okada, Onodera, Tamaru, "Shape Optimization Compaction" (The Institute of Electronics, Information and Communication Engineers, IEEJ, CAS-11, VLD93-11, DSP93-21
(1993-05), pp.73-80), a method is proposed in which local shape changes are repeatedly taken into consideration while taking into account wiring to layout elements whose shapes change, and overall compression and shape optimization are performed simultaneously. ing. According to this method, it is possible to automate the selection of the element shape and reuse the layout.

[0005]

However, the above-mentioned method reuses the detailed layout pattern of the designed LSI as it is, and a certain functional unit in the LSI such as an arithmetic unit, an adder, and a transistor is used. Since the replacement of the functional cells to be realized is not considered, it cannot be fully utilized for redesign. The device supporting the redesign is provided with a function for making a new design change such as addition / correction / deletion of a functional cell or wiring in a lower hierarchy in the existing layout pattern of the LSI so as to meet the user's specifications.
It is essential to efficiently complete the layout pattern.

Therefore, according to the present invention, a reuse method of an LSI layout pattern capable of accurately and promptly creating a high-density and high-quality layout corresponding to a change in a partial circuit by utilizing a layout pattern previously designed ( Device).

[0007]

In order to achieve the above object, a method of reusing an LSI layout pattern according to the present invention is such that a layout pattern of an original LSI circuit that has already been created is partially modified to create a new LSI. In the method of reusing the LSI layout pattern for completing the circuit layout pattern, the circuit data of the original LSI circuit and the new LSI circuit are compared to determine whether to add / correct / delete functional cells / wiring to the original LSI circuit. Based on the change part determination step to be performed and the above determination, the unnecessary pattern such as the functional cell, wiring, and through hole to be deleted is deleted from the layout pattern of the original LSI circuit to secure a space, and the addition / correction is performed. Partial modification by arranging functional cells and partially modifying the layout pattern of the original LSI circuit to obtain a cell layout modification pattern Step, a wiring channel graph creating step for creating a wiring channel graph based on the layout position of the functional cells on the cell layout changing pattern, and wiring and through holes of the original LSI circuit reused in the cell layout changing pattern Is assigned to the schematic wiring paths and through holes shown on the wiring channel graph, and the relative placement determining step of determining the relative placement relationship between the wiring patterns and the relative placement relationship between the wiring patterns are determined. In addition to the above-mentioned cell arrangement change pattern, a route correction step for determining a route of an unconnected wiring or a partial route correction of the wiring, which may be caused by addition / correction / deletion of a functional cell, and reuse in the changed area Connected wiring, the wiring channel graph, the schematic wiring route, etc. , Details layout pattern generating step of generating a detailed layout pattern embodied functional cells and wiring arrangement change pattern, characterized in that it comprises a.

The LSI layout pattern reusing apparatus according to the second aspect of the invention uses the new LSI by partially modifying the layout pattern of the original LSI circuit that has already been created.
In an LSI layout pattern reuse device that completes a circuit layout pattern, an original LSI circuit and a new L
From the layout pattern of the original LSI circuit, based on the above-mentioned determination, the changed portion determining means for comparing the circuit data with the SI circuit to determine addition / correction / deletion of functional cells / wiring to the original LSI circuit, A space is secured by scraping away unnecessary patterns such as function cells, wiring and through holes that should be deleted, and add / modify special function cells are arranged.
Partial changing means for partially changing the layout pattern of the SI circuit to obtain a cell layout changing pattern, and wiring channel graph creating means for creating a wiring channel graph based on the layout position of the functional cells on the cell layout changing pattern And the wirings and through holes of the original LSI circuit that are reused in the cell layout change pattern are assigned to the schematic wiring paths and through holes shown on the wiring channel graph, and the relative layout relationship between the wiring patterns is determined. Relative placement determining means, for the cell placement change pattern, the relative placement relationship between the wiring patterns is determined,
Route correction means for determining the route of unconnected wiring and partial route correction of wiring that may occur with addition / correction / deletion of functional cells, wiring reused in the changed area, and graph of the wiring channel A detailed layout pattern creating means for creating a detailed layout pattern of functional cells and wirings embodied in the cell placement change pattern processed by the path correcting means, with reference to the above-mentioned schematic wiring path and the like. Characterize.

[0009]

In the above structure, the circuit designer first compares the previously designed circuit diagram of the usable layout pattern with the new circuit diagram, and adds / corrects / deletes the used layout pattern. The functional cell of the lower hierarchy to be used is determined. Addition / change of connection information of the net with it
Also decide to delete. Further, if necessary, the designer can specify a portion on the circuit diagram in which the relative positional relationship of the wiring and the relative positional relationship of the through hole are desired to be stored. The partial change step (or means) automatically removes a wasteful space in the layout and secures a necessary space, so that the layout can be easily corrected without making a mistake. The wiring channel graph creating step (or means) creates a wiring channel graph necessary for searching a rough wiring route for the corrected layout. In the relative placement determining step (or means), the relative positions of the through-holes and the rough wiring route on the channel graph are determined with reference to the detailed layout patterns regarding the created wirings and through-holes. Route correction step (or means)
Determines the route of unconnected nets and the route correction of a part of nets due to the layout modification. The detailed layout pattern creating means refers to the already created detailed layout pattern and creates a final detailed layout pattern from the relative positions of the rough wiring paths and the through holes.

As a result, in particular, it is possible to globally optimize the determination of the shortest wiring route without detours and the minimum number of crossings between wirings and the number of through holes, resulting in a high-density and high-quality layout. It is possible to efficiently create a design.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows the overall configuration of an LSI layout pattern reusing apparatus (computer system) according to the present invention. A layout pattern reuse device includes a keyboard 1, a pointing device 2 for inputting coordinates such as a mouse and a tablet, a database 3 for storing information required for reuse and creation of layout patterns,
Follow the instructions entered from the keyboard 1 and mouse 2,
A data processing device 4 that performs various processes related to the reuse and creation of layout patterns using the data of the database 3, and a graphic display 5 that displays a layout pattern created by a circuit diagram or data processing device.
Consists of After all the processing is completed, the created layout pattern is the new LSI manufacturing mask pattern data 6
Is output to a database or recording medium (not shown).

Next, the processing in the data processing device will be described with reference to the flow chart. The flowchart shown in FIG. 1 shows the overall configuration of the present invention, and the flowcharts of FIGS. 3 to 8 and the explanatory diagrams of FIGS. 9 to 11 to be described later are more specific of each step shown in FIG. 1 described below. The specific content.

First, the overall operation will be described with reference to FIG. As shown in FIG. 1, the circuit data of the original LSI circuit, which is the target of the design change, is compared with the data of the new circuit to be created from the database 3 to add / correct / delete the functional cells in the lower hierarchy. decide. In addition, the addition / deletion / correction of wiring is determined accordingly (step S2, FIG.
(A)).

In order to secure a space for arranging a function cell of a lower hierarchy to be added / corrected, a waste space of a function cell, wiring, and a through hole to be deleted from the layout pattern of the original LSI circuit is reduced, and a space of a newly arranged cell is reduced. Secure. The added / modified new function cell is arranged (step S4, FIG. 9B and FIG. 10C).
(A)).

A wiring channel graph, which is necessary when searching a rough wiring route, is created (step S6, FIG. 10).
(B)). A channel is a region where one or more wirings can be formed, and is used for determining a wiring route by a two-step method of rough wiring and detailed wiring. The rough wiring is wiring information in which a route is globally determined on a channel graph, and the detailed wiring is wiring information in which a wiring layer and a detailed route (position) are determined so as to satisfy a design rule (design rule). .

With respect to the detailed layout pattern of the wiring and through holes of the original LSI circuit which has already been created,
Relative arrangement positions of the rough wiring route and the through hole on the channel graph are determined (step S8, FIG. 10C).

The route of the unconnected net is determined and the route of a part of the net is corrected in accordance with the layout correction (step S10, FIG. 11A).

With reference to the detailed layout pattern of the original LSI circuit that has already been created, the final detailed layout pattern is created from the relative positions of the rough wiring paths and through holes (step S12, FIG. 11B).

Next, the above steps will be described. FIG. 3 is a flowchart showing a more specific procedure of step S2. That is, from the database 3 that stocks the designed layout patterns,
The data of the circuit diagram (old circuit diagram) of the LSI to be reused as shown in (a) is read. The designer modifies the circuit to meet the required specifications and designs a new circuit diagram. Alternatively, a new circuit diagram modified by a device (not shown) is stored in the database 3 in advance. The data of the old circuit diagram and the data of the new circuit diagram to be designed are read (step S202). The quoted functional cell lists before and after the modification are compared (step S204). The functional cell of the lower hierarchy that needs to be added, modified or deleted is determined (step S206).

Further, from the read data of the old circuit diagram and the data of the new circuit diagram (step S212), a list of a set of connection terminals is created for each new / old circuit diagram on a net basis (step S214). The lists of terminal sets of the new and old circuit diagrams are compared (step S216), and the net to be deleted, the net to be added, and the net to be corrected are determined (step S218). For example, in the circuit diagram shown in FIG. 9A, as a result of comparison of data between the old and new circuit diagrams, the functional cell B,
It is decided that C and F should be removed and functional cells G and H should be added.

Based on these pieces of information, a space is secured in the already created layout pattern, and the layout location of the functional cell added / modified by the designer is designated (step S4). That is, the data processing system takes in the data of the already designed pattern, the reuse pattern area, the data of the deletion / addition / correction function cell, the data of the deletion / addition / correction net, the design rule and the like (step S402). And
The layout pattern related to the deleted cell and the deleted net is deleted (step S404). Further, a part of the wiring pattern of the correction net is deleted, and the result of FIG.
As shown in (b), the functional cell and the existing wiring are deleted (step S406). Addition, correction cell placement, and direction determination are performed (step S408). A process of creating a space in the X direction is performed (step S410). Further, a process for creating a space in the Y direction is performed to make space for an additional cell as shown in FIG. 9C (step S41).
2). As shown in FIG. 10 (a), an addition / correction cell placement process is performed (step S414). By these processes, the layout pattern of the functional cells and the wiring pattern to be reused are obtained (step S416).

Next, a wiring channel graph is created (step S6). That is, by taking in the layout pattern of the functional cells, searching for the wirable area in the X direction,
Determine the free space in the X direction. For example, in FIG.
As shown in (a), outside the layout area above and below,
Assuming that a virtually large functional cell exists, areas x1 to x8 sandwiched between vertically adjacent functional cells are discriminated as wirable areas (step S604). A straight line is created at the center of the wirable areas x1 to x8 sandwiched between the functional cells (step S606).

Similarly, from the arrangement pattern of the functional cells, Y
A wirable area in the direction is searched to determine an empty space. For example, as shown in FIG. 12B, it is assumed that virtually large cells exist outside the left and right of the layout area, and areas y1 to y sandwiched between the left and right functional cells are arranged.
y8 is determined as the wirable area (step S60).
8). Wirable areas y1 to y sandwiched by functional cells on the left and right
A straight line is created at the center of 8 (step S610). As a result, a graph represented by a straight line (dotted line) extending in the X and Y directions is created (step S612). As shown in FIG. 10B, a channel is drawn from the terminal of the functional cell to the edge of the graph to create a drawn channel (step S614). As a result, wiring channel graph data is obtained (step S616).

Next, the relative positions of the rough wiring route and the through hole on the channel graph are determined (step S8).
That is, the wiring channel data and the wiring pattern to be reused are fetched (step S802), and the wiring pattern is decomposed into wiring segments in the X and Y directions (step S802). Information about the relative order of wiring patterns, wiring layers, and wiring intersections is stored (step S8).
06). As shown in FIG. 10C, the wiring pattern is mapped to the closest channel in the same direction (step S808). As a result, the wiring route on the channel graph of the wiring pattern to be reused, the relative order of the wiring patterns, the wiring layer, and the intersection information are obtained (step S81).
0).

Next, the route of the unconnected net is determined and the route of the net is corrected in accordance with the layout correction (step S1).
0). That is, the wiring channel graph, the net information to be added / modified, and the data of the wiring route on the channel graph of the wiring pattern to be reused are fetched (step S100).
2) Referring to the wiring route on the channel graph, the already-wired portion is recognized (step S1004). A route candidate set of wiring patterns on the channel graph is generated for each net (step S1006). As shown in FIG. 11A, the optimum wiring route is determined from the combinations of route candidates (step S1008). As a result, the wiring route on the wiring channel graph is obtained (step S1010).

Next, a final detailed layout pattern is created (step S12). That is, the wiring channel graph, the wiring route on the wiring channel, the relative order of the wiring patterns to be reused, the wiring layer, the intersection information, and the like are fetched (step S1202), and the relative order of the wirings is determined for each channel. At this time, the number of intersections between the wirings is minimized (step S1204). X direction, Y
Directional compaction is performed to secure a wiring space (step S1206). The wiring layer is determined and through holes are generated if necessary (step S1208).

As a result, for example, as shown in FIG. 11 (b), most of the functional cells that are reused as they are, the newly added functional cells G and H, and the through-holes indicated by points X are used. And detailed data of the wiring pattern constituted by the multi-layer wiring by the cross wiring shown by the dotted line and the arrangement data of each functional cell are obtained (step S121).
0).

As shown by 131 in FIG. 13, a channel 131 passing through the functional cell can be provided in an LSI circuit having multilayer wiring. For example, this can be added in step S8 to create a higher density layout pattern. In the figure, 132 is a functional cell arrangement position, 133 is a channel graph, 134 is a lower level functional cell, and 135 is a wiring terminal.

Further, as shown in FIGS. 14A and 14B, of the created channels, both sides of the channel are not actual functional cells of the lower hierarchy, and the wiring capacity of the channel is defined in advance by the designer. When the value is equal to or less than the above value, it is possible to combine a plurality of channels in the same direction into one.

As described above, according to the present invention, since the existing layout pattern is reused, the LSI design period can be shortened. Use existing circuits that do not have any problems and add functional cells and wiring according to a certain algorithm.
Since correction / deletion is performed, it is possible to eliminate mistakes related to design rule violation. Since a useless area generated on the corrected layout can be deleted, a high-density layout can be created. In addition, when newly modifying / generating wiring, it is possible to consider the wiring route of the designed part and the crossing situation of the wiring, and to eliminate the detour of the wiring and the generation of unnecessary wiring crossing and through holes. It is possible to create a high quality layout pattern.

[0031]

As described above, according to the present invention,
Since the existing layout pattern is reused, the LSI design period can be shortened.

[Brief description of drawings]

FIG. 1 is a flowchart schematically illustrating reuse of a layout pattern according to the present invention.

FIG. 2 is a block diagram schematically showing an overall configuration of a CAD device that executes the present invention.

FIG. 3 is a flowchart explaining step S2 of the flowchart shown in FIG. 1 more specifically.

FIG. 4 is a flowchart for more specifically explaining step S4 of the flowchart shown in FIG.

5 is a flowchart for explaining step S6 of the flowchart shown in FIG. 1 more specifically. FIG.

FIG. 6 is a flowchart for more specifically explaining step S8 of the flowchart shown in FIG.

FIG. 7 is a flowchart for explaining step S10 of the flowchart shown in FIG. 1 more specifically.

FIG. 8 is a flowchart for more specifically explaining step S12 of the flowchart shown in FIG.

FIG. 9A to FIG. 9C are explanatory diagrams for explaining a circuit layout step by step.

FIG. 10A to FIG. 10C are explanatory diagrams for explaining a circuit layout step by step.

FIG. 11A and FIG. 11B are explanatory diagrams for explaining a circuit layout step by step.

FIG. 12A and FIG. 12B are explanatory diagrams for explaining the empty area search at the stage of creating a channel graph.

FIG. 13 is an explanatory diagram illustrating generation of a channel graph.

FIG. 14 is an explanatory diagram illustrating merge processing of a plurality of channels in the same direction.

[Explanation of symbols]

 1 keyboard 2 mouse (pointing device) 3 database server 4 data processor 5 graphic display

Claims (4)

[Claims] 1. A method of reusing an LSI layout pattern, wherein a layout pattern of an original LSI circuit that has already been created is partially modified to complete a layout pattern of a new LSI circuit. A changed portion determination step of comparing circuit data with the LSI circuit to determine addition / correction / deletion of functional cells / wiring to the original LSI circuit; and based on the determination, from a layout pattern of the original LSI circuit, A cell is created by removing unnecessary patterns such as function cells, wiring and through holes to be deleted to secure space, arranging add / modify function cells, and partially changing the layout pattern of the original LSI circuit. A partial changing step for obtaining a placement change pattern, and a wiring channel graph based on the placement position of the functional cells on the cell placement change pattern. A wiring channel graph generating step of generating the original LS is reused in the cell arrangement change pattern
Relative layout determining step of allocating wirings and through holes of the I circuit to the schematic wiring paths and through holes shown on the wiring channel graph to determine a relative layout relationship between the wiring patterns, and a relative layout determining step between the wiring patterns. A route correction step for determining a route of an unconnected wiring or a partial route correction of a wiring, which may occur with the addition / correction / deletion of a functional cell with respect to the cell layout change pattern for which a specific layout relationship is determined. , A detailed layout pattern of functional cells and wiring embodied in the cell layout change pattern that has undergone the route correction step, with reference to the wirings reused in the changed region, the wiring channel graph, the general wiring route, etc. And a detailed layout pattern creating step for creating an LSI layout pattern. . 2. The method of reusing an LSI layout pattern according to claim 1, wherein the relative placement determining step has a function of creating a channel passing on the functional cell. 3. The wiring channel graph creating step comprises:
The function cell does not exist on both sides of the channel, and when the wiring capacitance of the channel is equal to or less than a specified value, adjacent channels are expressed as one channel. Reusing method of LSI layout pattern. 4. An LSI layout pattern reuse apparatus for partially modifying a layout pattern of an original LSI circuit that has already been created to complete a layout pattern of a new LSI circuit. A changed portion determining unit that compares circuit data with the LSI circuit to determine addition / correction / deletion of a functional cell / wiring to the original LSI circuit; and a layout pattern of the original LSI circuit based on the determination, A cell is created by removing unnecessary patterns such as function cells, wiring and through holes to be deleted to secure space, arranging add / modify function cells, and partially changing the layout pattern of the original LSI circuit. Partial changing means for obtaining a layout change pattern, and creating a wiring channel graph based on the layout position of the functional cells on the cell layout change pattern A wiring channel graph generator that, original LS is reused in the cell arrangement change pattern
Relative arrangement determining means for allocating the wirings and through holes of the I circuit to the schematic wiring paths and through holes shown on the wiring channel graph to determine the relative arrangement relationship between the wiring patterns, and the relative arrangement between the wiring patterns. With respect to the cell layout change pattern for which the physical layout relationship is determined, route correction means for determining the route of unconnected wiring and partial route correction of wiring, which may occur with the addition / correction / deletion of functional cells. , Details of functional cells and wiring embodied in the cell layout change pattern processed by the route correction means, with reference to the wirings reused in the changed area, the graph of the wiring channel, the general wiring route, etc. An LSI layout pattern reusing apparatus, comprising: a detailed layout pattern creating means for creating a layout pattern.