JPH09320289A - Semiconductor nonvolatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of defect of multibits by providing a reference level generating means and a discriminating means, discriminating the state of data before the threshold exceeds the discriminating limit and rewriting the data, if necessary. SOLUTION: The respective outputs of level comparators 21-23 are supplied to a discriminating part 24. The discriminating part 24 judges the data preserved in a memory cell i.e., the propriety of a threshold and the shift of the threshold from the result of comparison by means of an algorithm. When it is judged that the threshold has shifted, data held in the memory cell are read out by a data rewrite control part 25 and data held in a latch circuit B or an I/O buffer 11 are again rewritten in the memory cell. Thus, the threshold of a cell transistor is set again. In rewriting, when the data are corrected to '1', erasure is performed, and when they are corrected to '0', writing after the erasure is performed. Erasing/writing of data are performed by using an EEPROM, and processing such as this is performed with a page unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a semiconductor non-volatile memory, and more particularly to improving reliability of data held in a memory cell of an EEPROM.

[0002]

2. Description of the Related Art Examples of conventional EEPROMs are shown in FIGS.
This will be described with reference to FIG. FIG. 6 is a block diagram showing an outline of EEPROPM. Word line control circuits are arranged in the row direction and bit line control circuits are arranged in the column direction of a cell array in which memory cells are arranged in a matrix. The cell array is composed of a plurality of blocks, and each block is composed of a plurality of pages. In a flash memory using a NAND structure, erasing is performed for all bits or blocks, and writing and reading are performed collectively for each page. For example, one block is 4 Kbytes and one page is 5
It consists of 12 bytes.

FIG. 7 shows a block configuration example of a NAND flash memory. In the figure, SG1,
2 is a block selection line for selecting a block, CG1 to CG
8 is a word line for controlling the gate of the memory, BL0 to BL
4095 is a bit line, and Vs is a source potential.

FIG. 8 shows a part of the bit line control circuit for one word line, where A is a sense amplifier circuit and B is a sense amplifier circuit.
Indicates a data latch circuit, and C indicates a bit line potential control circuit. AB form part 10 of the bit line control circuit for one bit line. Reference numeral 11 is an I / O buffer that temporarily holds input / output data.

In such a configuration, when erasing block data, BL0 to BL4095 are floated, SG
1, SG2 is 20 volts, CG1 to CG8 is 0 volts,
This is done by setting Vs to 20 volts and P-well to 20 volts.

When writing page data to the memory, for example, when writing data to the page of CG4, BL1 to BL1
0 volt (data “0”) or 8 volt (data “1”) corresponding to one page of data for each BL4095
Set. SG1 and SG2 are 10 volts, CG1 to C
G3 is 10V, CG4 is 18V, CG5-CG
Set 8 to 10 volts, Vs to 0 volts and P-well to 0 volts. At the time of writing, the data latch circuit B and the bit line potential control circuit C are used. The data from the I / O buffer is input to and held in the latch circuit B. The hold output is input to the bit line potential control circuit C. OSC to the circuit is the output of the ring oscillator, and when the data is "0", "0 volt" is applied, and when the data is "1", the pumping operation is performed and "8 volt" is applied to the bit line. .

When reading page data from the memory, for example, when reading a page of CG4, the bit line BL1
~ BL4095 is precharged, and then the bit line is brought into a floating state. SG1 and SG2 are Vcc volt, CG1 to CG3 are Vcc volt, selected CG4
Is set to 0 volt, CG5 to CG8 are set to Vcc volt, Vs is set to 0 volt, and P well is set to 0 volt. Selected N
The non-selected memory cell in the AND cell becomes conductive, and the potential of the bit line is determined depending on whether the threshold value of the selected memory cell is positive or negative. If the data of the selected memory cell is "0", the cell current does not flow and the potential of the selected bit is held as the precharge voltage. If the data is "1", the cell current causes the potential of the selected bit to drop below the reference value VR. Bit line B
The potential VBL of L is set to the reference value V by the current mirror circuit A.
Compared to R. If the bit line potential is below that,
It is determined as "1" data, and if it is more than that, it is determined as "0" data.

[0008]

As shown in FIG. 9, when the threshold value of the memory cell transistor is set to data "0", the data read by the above-mentioned precharge method is performed by the potential of the precharged bit line. V with little decrease
The characteristic of BL0 is the characteristic of VBL1 in which the potential drop of the precharged bit line is large when the data is set to "1".

By the way, in a non-volatile memory, data may be lost during use due to "read disturb" in which the threshold value increases due to the voltage of the control gate CG at the time of reading or "data loss" in which charges slowly escape through the oxide film. Can change from one to the other. This means that the above-mentioned VBL characteristic changes during use, and erroneous data is output.

Bit property (1
If the cell threshold rises and the data changes in one cell), ECC (Er
rorCorrection Code) is conventionally used. But E
CC has the following drawbacks.

(A) It is necessary to perform a calculation process to detect an ECC error. If you try to do this in the chip, EC
It becomes necessary to incorporate additional bits for C, arithmetic processing circuits, etc.,
The chip area becomes quite large.

(B) Conventionally, an extra cell for ECC capable of correcting 1 bit per row is provided, but the threshold value is gradually increased due to read disturb, and a plurality of defective cells are generated per row. Sometimes I can't help.

(C) Since the cell data itself is not modified, it must be modified when the data is read after the change.
The read response performance is reduced accordingly.

Therefore, according to the present invention, it is possible to prevent the problem that the held data is inverted due to the shift of the threshold value of the cell transistor, and to eliminate the need for an external or complicated in-chip peripheral circuit necessary for ECC correction. Intended to provide memory.

[0015]

In order to achieve the above object, a semiconductor non-volatile memory of the present invention has a structure in which non-volatile memory cells in which data can be electrically written and erased are arranged in rows and columns. In a semiconductor nonvolatile memory having a cell array in which a memory cell corresponding to a specified address can be selected by a line group and a word line group, the semiconductor nonvolatile memory corresponds to first and second values (“1” and “0”) of data, respectively. First and second reference levels ("VL", "VH")
And a reference level generating means for generating an intermediate level ("VM") of an intermediate value of the first and second reference levels,
The potential (VBL) of the precharged bit line for reading data from the addressed memory cell is the mutual difference between the first reference level ("VL") and the intermediate level ("VM"). Between the second reference level (“VH”) and the intermediate level (“VM”) and the bit line potential (VBL). , The first reference level (“VL
”) And the intermediate level (“ VM ”), the first value (“ 1 ”) is written to the memory cell from which the data has been read, and the second reference level (“ VH ”) and Data rewriting means (25) for writing a second value ("0") to the memory cell from which the data has been read when it is between the intermediate level ("VM") and the intermediate level ("VM"). And

The semiconductor nonvolatile memory of the present invention is
Semiconductor non-volatile having a cell array in which non-volatile memory cells in which writing and erasing of data are electrically enabled are arranged in a matrix, and memory cells corresponding to a specified address can be selected by a bit line group and a word line group. In the memory, first and second reference levels (“VL” corresponding to first and second values (“1”, “0”) of data, respectively)
, "VH") and the bit line (BL) precharged for reading data from the addressed memory cell, the bit at the first time (t1) The line potential (VBL) is compared with the first reference level ("VL") and the second time (t2
), The bit line potential (VBL) is compared with the second reference level ("VH") to determine whether the data needs to be corrected, and the second time (t2).
), When the bit line potential (VBL) is lower than the first reference level ("VL"), the first value ("1") is written to the memory cell from which the data has been read, and the bit line potential (VB
L) is the first and second reference level (“VL”, “VH”)
A data rewriting means (25) for writing a second value (“0”) into the memory cell from which the data has been read when the data is in between.
It is characterized by having.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an EEPROM to which the present invention is applied.
It is a block diagram which shows the principal part of FIG. In the figure, parts corresponding to those in FIG. 8 are denoted by the same reference numerals, and description of such parts is omitted.

In this embodiment, level comparators 21 to 23 are connected to each bit line BLi through a transistor Ts which conducts in the test mode. A reference voltage VL is applied to the level comparator 21, a reference voltage VM is applied to the level comparator 21, and a comparison reference voltage VH is applied to the level comparator 23.

As shown in FIG. 4, each reference voltage is set so that reference voltage VL <reference voltage VM <comparison reference voltage VH.
The charges precharged on the bit line BL have characteristics of VBL0 and VBL1 when the data held in the memory cell is normal. When the threshold shifts, the detection voltage is within the range of VL <VH at time t after precharge. Therefore, when the detected voltage is VL <VM, the data is corrected to "1". If the detected voltage is VM <VH, the data is corrected to "0". Each reference voltage is, for example, reference voltage VL = 1 volt, VM = 2 volt, VH = 3 volt,
Set to.

The outputs of the level comparators 21 to 23 are supplied to the discriminator 24. The determination unit 24 determines the data held in the memory cell, that is, the suitability of the set threshold value and the shift of the threshold value, from each comparison result using an algorithm described later. When it is determined that the threshold value has shifted, the data rewrite control unit 25 reads the data held in the memory cell and reads it into the latch circuit B or the I / O buffer 11. Then, the latch circuit B or I / O
The data held in the buffer 11 is rewritten in the memory cell again. As a result, the threshold value of the cell transistor is set again. In the rewriting (correction), when it is corrected to "1", it is erased. To correct to "0", erase → write. A known technique in EEPROM can be used for erasing and writing of data. Such processing can be performed in page units.

The operation of the above configuration will be further described with reference to the flowchart of FIG.

In FIG. 2, first, a test mode is executed when power is supplied to a computer system (not shown), when the system is terminated, or when the CPU does not access the EEPROM. In this mode, for example, addressing is performed in page units that are data reading units. Addressing can be incorporated by the program of the CPU or as a function of the peripheral circuit of the EEPROM. When the address is input, it is decoded and the data held in the memory cell of the corresponding page can be read (S12). next,
Data is read in the same manner as described in the conventional example. That is,
The bit lines for one page are precharged, and for example, C
To read the data corresponding to the G4 page, CG4
0 volt is applied to CG1, CG1 to CG3 are Vcc, CG5
~ CG8 is set to Vcc, SG1 and SG2 are set to Vcc, and C
The data of each memory cell of one page to which the gate voltage of G4 is applied is read and held in the I / O buffer (S
14).

At this time, as shown in FIG. 4, the potential due to the discharge (reduction) of the charges charged in the bit line becomes time t.
Detected in. In FIG. 4, a curve VBL0 represents a defined area of data "0", a curve VBLS represents a limit of discrimination between data "0" and "1", and a curve VBL1 represents a defined area of data "1". When the charge voltage VBL of the bit line is in the region between the curve VBL0 and the curve VBL1, the threshold value of the read cell is shifted and it is determined that the correction is required.

The above-mentioned discriminating section 24 includes the level comparator 21.
23 to 23, the state of the memory cell of the read data is determined. At time t, the bit line voltage V
When BL is lower than the reference value VL, the held data is "1", it is determined that there is no shift in the threshold value of the cell transistor, and the test for that bit ends (S1).
6). When the bit line voltage VBL is higher than the reference value VH,
Since the held data is "0", it is determined that the threshold value of the cell transistor is not shifted, and the test for the relevant bit ends (S18). Bit line voltage VBL is reference value VL
If it is higher than the reference value VH and lower than the reference value VH, it is determined that the threshold value of the cell transistor is shifted (S18).
Therefore, when the bit line voltage VBL is higher than the discrimination reference value VM, the held data is corrected to "0" (S24).
If the bit line voltage VBL is lower than the discrimination reference value VM, the held data is corrected to "1" (S22). The stored data can be modified by comparing the reference values VR and VM of the sense amplifier A.
If and are set to be the same, the read data held in the I / O buffer is written again as it is. However, the corresponding data can be written again by the CPU. This correction process can be performed in page units.
The data correction step corresponds to the operation of the data rewriting control unit 25. The test on the bit (or page) at the specified address ends. Further, if the test of another page is designated, steps S12 to S24 are repeated.

When the defect is repaired by such a sequence, the data in the process of gradually changing from one side to the other side due to read disturb or data loss is rewritten to the data based on the threshold value of the cell transistor. By returning it, it becomes possible to prevent the occurrence of a data error.

FIG. 3 shows another embodiment of the present invention. In this example, as shown in FIG. 5, times t1 and t
The bit line voltage detection of 2 is performed twice to make a determination. This has the advantage that the number of level comparators used can be reduced to two. For this reason, the level comparator 22 shown in FIG. 1 is not provided in this embodiment.

First, as in the previous embodiment, when the computer system is powered on, when the system is shut down, or when the CPU does not access the EEPROM,
The test mode is executed. In this mode,
For example, addressing is performed on a page-by-page basis, which is a data reading unit. CP for addressing for testing
It can be incorporated by the program of U or as a function of the peripheral circuit of the EEPROM. When the address is input, it is decoded and the data held in the memory cell of the corresponding page can be read (S4).
2).

Next, the data is read. That is,
The bit lines BL0 to BL4095 for one page are precharged. For example, in order to read the data corresponding to the page of CG4 corresponding to the designated address, 0 volt is applied to CG4, and CG1 to CG3 are Vcc and CG5 to CG5. CG8
Is set to Vcc, SG1 and SG2 are set to Vcc, and the data of each memory cell for one page to which the gate voltage of CG4 is applied is read and held in the I / O buffer (S4
4).

At this time, as shown in FIG. 5, at times t1 and t2, the potential lowered by the discharge (reduction) of the charges precharged on the bit line BL is detected. In the figure, a curve VBL0 represents a fixed area of data "0", and a curve VBL1 represents a fixed area of data "1". For example, the comparison reference value VL is the value of the curve VBL1 at the time t1, the reference value VH is the value of the curve VBL0 at the time t2,
Each is set.

The discriminator 24 includes level comparators 21 and 23.
The threshold value state of the read memory cell is discriminated by each output of. When the voltage VBL of the bit line is lower than the reference value VL in the first detection at time t1, the held data is determined to be "1". In this case, VBL is the curve VBL
Due to the descent characteristic of, the data is still within the discrimination range of the data “1”. The test for the bit ends (S
46). At this time, if the voltage VBL is higher than the reference value VL, it means that the held data is "0" or the threshold value is shifted.

At time t2, the second detection of the bit line potential VBL lowered by the discharge (reduction) of the charges precharged on the bit line BL is performed (S48).

The discriminator 24 includes level comparators 21 and 23.
The potential VBL of the bit line is discriminated by the respective outputs of. When the bit line potential VBL is higher than the reference value VH, the held data is determined to be "0". Since it does not fall below the curve VBL0, it is determined that there is no threshold shift, and the test for that bit ends (S50).

When the bit line voltage VBL is lower than the reference value VH (S50) and lower than the reference value VL (S52), it is determined that the threshold value of the cell transistor is shifted from "1" (S52). The data rewrite control unit 25 corrects the held data to "1" (S54), and ends.

When the bit line voltage VBL is lower than the reference value VH (S50) and higher than the reference value VL (S52), it is determined that the threshold value is shifted from the data "0". Therefore, the data rewrite control unit 25 corrects the held data to "0" (S54), and ends the processing. The held data is modified, for example, by rewriting the read data held in the I / O buffer as it is. However, the corresponding data can be written again by the CPU. This correction process can be performed in page units. The test on the bit (or page) at the specified address ends. Further, if the test of another page is designated, steps S42 to S56 are repeated.

In the above example, the memory for writing and reading in page units was described, but the present invention can be similarly applied to the memory for writing and reading in bit units and block units. It is possible to rewrite data in block units.

Further, as the test mode, it is possible to judge the shift of the threshold value of the cell transistor in parallel with the data reading, instead of separately from the normal data reading.

[0038]

As described above, according to the semiconductor nonvolatile memory of the present invention, the data state is discriminated before the threshold value exceeds the discrimination limit, and the data is rewritten if necessary. It is possible to prevent the occurrence of defects. Further, unlike the ECC check, it is not necessary to perform the error check process every time the data is read, so the response performance does not deteriorate. Since an additional bit for ECC check and an ECC check mechanism are unnecessary, the influence on the increase of the memory chip area can be relatively small.

[Brief description of drawings]

FIG. 1 is a block circuit diagram illustrating an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation mode according to the first embodiment.

FIG. 3 is a flowchart illustrating an operation mode according to the second embodiment.

FIG. 4 is an explanatory diagram illustrating determination of a threshold value according to the first embodiment.

FIG. 5 is an explanatory diagram illustrating determination of a threshold value according to the second embodiment.

FIG. 6 is an explanatory diagram illustrating a schematic configuration of a semiconductor nonvolatile memory.

FIG. 7 is an explanatory diagram showing a configuration example of a memory cell of a NAND flash memory.

FIG. 8 is a block diagram illustrating a part of a bit line control circuit for one bit line.

FIG. 9 is an explanatory diagram illustrating a change in bit line potential after precharging in a conventional device.

[Explanation of symbols]

 10 bit line control circuit 11 I / O buffers 21-23 level comparator 24 discriminator 25 data rewrite controller

Claims (3)

[Claims] 1. A cell array in which non-volatile memory cells in which data can be written and erased electrically are arranged in a matrix, and a memory cell corresponding to a designated address can be selected by a bit line group and a word line group. A semiconductor non-volatile memory having: a first non-volatile memory corresponding to the first and second values of the data, respectively.
And a second reference level and an intermediate level intermediate the first and second reference levels, and precharge for reading data from the addressed memory cell. The potential of the selected bit line is between the first reference level and the intermediate level, or the second level.
Discriminating means for discriminating between the reference level and the intermediate level, and data when the potential of the bit line is between the first reference level and the intermediate level. A data rewriting means for writing a first value into the read memory cell and writing a second value into the memory cell from which the data has been read when the first value is between the second reference level and the intermediate level. A semiconductor non-volatile memory comprising: 2. The discriminating means comprises a first level comparator for comparing the bit line potential and the first reference level, and a second level comparator for comparing the bit line potential and the intermediate level. 2. The semiconductor nonvolatile memory according to claim 1, further comprising: a third level comparator that compares the bit line potential with the second reference level. 3. A cell array in which non-volatile memory cells electrically capable of writing and erasing data are arranged in a matrix, and a memory cell corresponding to a designated address can be selected by a bit line group and a word line group. A semiconductor non-volatile memory having: a first non-volatile memory corresponding to the first and second values of the data, respectively.
And a reference level generating means for generating a second reference level and a bit line precharged for reading data from an addressed memory cell, at a first time, the potential of the bit line and the The first reference level is compared, and at a second time, the bit line potential and the second
Discriminating means for discriminating whether or not data correction is necessary by comparing the bit line potential with the first level at the second time.
When the bit line potential is between the first and second reference levels, the second value is written to the storage cell from which the data has been read. A semiconductor non-volatile memory, comprising: a data rewriting means for writing the value of.