JPH09319733A - Fft arithmetic method and circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To properly reduce the redundant parts and the scale of an arithmetic circuit without deteriorating the arithmetic accuracy by preparing a butterfly arithmetic process, a data storage process, an overflow detection process and a bit shift process respectively. SOLUTION: The overflow detection parts 231 to 2311 monitor the overflows of butterfly arithmetic results, and the overflow detection information are outputted to the bit shift parts 241 to 2411. The data written in the data memory parts 221 to 2211 are outputted to the parts 241 to 2411 after the butterfly arithmetic results of all input data are stored. The parts 241 to 2411 select three operations based on the overflow detection information. That is, lower 10 bits of input 12-bit data are directly outputted to the next stage, 10 bits of the input 12-bit data excluding the lowest bit are outputted to the next stage, and higher 10 bits of the input 12-bit data are directly outputted to the next stage. No overflow occurs at all in these output data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
(Orthogonal Frequency Division Multiplex) FFT that can be used for digital transmission
The present invention relates to a (Fast Fourier Transform) calculation method and an FFT calculation circuit, and particularly to a technique for reducing the circuit scale.

[0002]

2. Description of the Related Art In recent years, OF has been used in digital audio broadcasting for mobiles and terrestrial digital television broadcasting.
The DM method is drawing attention. In such OFDM digital transmission, FFT calculation is indispensable for signal conversion between the frequency domain and the time domain.

In performing this FFT operation with conventional hardware, it was necessary to have a long operation word length inside the dedicated LSI. FIG. 3 shows an operation process that requires a long operation word length.

In FIG. 3, one vertical column on the left side is the input data to the FFT, and one vertical column on the far right side is the final calculation result. The operation consists of M (M = 3 in the figure) stages, and is performed by flowing data from left to right.

In each stage, butterfly calculation (shown by cross points in the figure) is performed on the input data. By this butterfly operation, two output data are obtained from two input data. That is, the butterfly calculation is performed N / 2 (= 4) times in one stage for N pieces (N = 8 in the figure) of input data for which the FFT calculation is performed. Then, N (= 8) pieces of output data become the input data in the next stage.

As described above, in the FFT operation, the processing "each input data is butterfly-operated only once for each stage, and its output data is again butterfly-operated once as the input data of the next stage" is processed. Repeated. In FIG. 2, [2 to the third power] point ([2 to M)
[Multiplying] point), and the butterfly calculation is performed three times (M times) in the stage direction.

In the butterfly operation, first, one of the two input data is subjected to complex multiplication, and the operation result and the other data are subjected to complex addition and subtraction.
It is only a journey. However, this method is a case where a method called a time thinning method is used.

The dynamic range of the complex operation output is as follows when considered in the polar coordinate system. The value of the radius does not change in the first complex multiplication, but the radius is doubled at the maximum in the next complex addition and subtraction. Therefore, the output dynamic range needs to be twice the input range.

Let us consider this with respect to the FFT operation of [2 M power] points. In this case, the butterfly calculation is performed M times in the data flow direction. That is, the range needs to be doubled for one butterfly operation, and this is repeated M times. Therefore, the dynamic range of the output unit needs to be [2 to the Mth power] times the dynamic range of the input unit. For example, in an FFT operation of 2048 points ([2 to the 11th power] points), the same number of points as 2048 points
A double dynamic range will be provided for calculation.

When this is expressed in hardware, it is necessary to increase the operation word length by 1 bit for each butterfly operation. Therefore, in the final stage of the FFT operation of [2 M power] points, it is necessary to expand M bits.

[0011]

However, the extension bit is not surely used in one FFT operation, and is prepared as a bit that may be used. That is, an unused area may occur in one FFT calculation. As a result, this can be regarded as redundant, and becomes a cause of unnecessarily increasing the circuit scale.

In particular, in the above-mentioned OFDM digital transmission, there is a strong demand for reduction of the circuit scale toward the integration of the OFDM demodulation circuit. Therefore, reduction of the redundant part of the FFT operation circuit is very significant.

The present invention has been made in view of the above circumstances, and an FFT operation method and an FF which can reduce the circuit scale by appropriately reducing the redundant portion without impairing the operation accuracy.
An object is to provide a T arithmetic circuit.

[0014]

In order to solve the above-mentioned problems, an FFT operation method of the present invention is a butterfly operation process for performing butterfly operation on a plurality of input data, and all output data within a stage of this butterfly operation process. A data storage step of accumulating and outputting to the next stage, and an overflow detection step of detecting the presence or absence of overflow for all output data in the stage of the butterfly operation step,
When an overflow is detected in the overflow detection process, a bit shift process of performing bit shift of the output data in the data storage process is provided.

Further, the FFT operation circuit of the present invention includes a butterfly operation section for performing butterfly operation on a plurality of input data, a data storage section for accumulating all output data in the stage of the butterfly operation section and outputting it to the next stage. An overflow detection unit that detects the presence or absence of overflow for all output data in the stage of the butterfly operation unit; and a bit shift unit that performs a bit shift of the output data of the data storage unit when the overflow detection unit detects an overflow. I was prepared.

In particular, an FF used in an OFDM demodulator for converting time domain input data into frequency domain data.
The T operation method is provided with an operation result output step of outputting an operation result by limiting the operation word length of an arbitrary stage based on the accuracy of the input data and the area distribution.

An FF used in an OFDM demodulator for converting input data in the time domain into data in the frequency domain.
The T operation circuit is provided with operation result output means for outputting the operation result by limiting the operation word length of any stage based on the accuracy of the input data and the area distribution.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Prior to describing the embodiments of the present invention, the operation principle will be described in order to facilitate understanding. First, when applied to the OFDM demodulator, the OFDM
Due to the condition of demodulation, the following can be said regarding input / output data around the FFT operation circuit. (1) Input data is an OFDM transmission signal subjected to IFFT. (2) Output data are QPSK symbol points and QAM symbol points. From the above, the data value in the calculation process from the input data to the output data can be grasped by the simulation study.

Therefore, the amplitude distribution in this operation process is studied in advance, and the redundant operation word length is omitted by utilizing the special property obtained from the amplitude distribution, thereby eliminating the waste of the circuit. The calculation process used here is a butterfly calculation of each stage, and the amplitude distribution of each stage is treated.

It is known that the amplitude distribution of the OFDM signal input to the FFT calculation circuit is Gaussian distribution. However, when the amplitude distribution of each stage is examined by simulation, the dynamic range of 2 times, 4 times, ... Is not required.

For example, when a simulation is actually performed for QPSK modulation, the result is 1.5 times,
2.2 times, 3.2 times, 4.5 times, and so on. Even in the stage requiring 16 times, the amplitude distribution was obtained only in the range of 4.5 times.

Further, at the QPSK symbol point of the final output, the range originally required to be 2048 times required only 13.7 times at most. In other words, the operation word length needs to be extended by 11 bits, but the operation can be performed by extending only 4 bits.

Further development of this result can realize the following circuit configuration. First, the extension of the operation word length is set to 2 bits. Then, in the actual calculation process, when the butterfly calculation value overflows beyond the dynamic range of the extended 2 bits, bit shift is performed to reduce the calculation value of the entire stage to 1/2. After that, when the calculated value overflows again, the calculated value is bit-shifted in stages. With this configuration, it is possible to realize a circuit in which the operation word length expansion which copes with the data overflow is only 2 bits.

The present invention eliminates the redundancy of the operation word length by using this technique of bit shift operation.
As a result, the FFT operation circuit can be downsized. In the present invention, in order to maintain the calculation accuracy, it is necessary to consider the occurrence of a truncation error due to the bit shift. However, with respect to this as well, it is possible to conduct a simulation study in advance. As a result of the examination, it was confirmed that the operation accuracy as the FFT operator can be secured by expanding the operation word length of 2 to 4 bits with respect to the number of input data bits in the first stage. For example, by applying the present invention to what has conventionally required 11-bit extension, the circuit can be configured by only 2-bit extension. This leads to the fact that the circuit scale can be reduced to about 1/3, and the circuit scale can be greatly reduced and downsized.

Next, the function of each operation will be described using numerical examples. The operation word length is 10 bits. The dynamic range in this case is -512 to +511. The input to the butterfly calculator is this range and its output range is 2
Doubled. That is, the data is distributed in the range of -1024 to +1023. In the bit shift operation, the data is halved to −512 to +511.

At this time, rounding, rounding up, or rounding down to the number after the decimal point of 0.5 is arbitrary in the circuit configuration.
However, due to the complex operation, if there is data that exceeds the dynamic range even if it is bit-shifted, another bit is shifted.

FIG. 1 shows a schematic configuration of an FFT operation circuit which is an embodiment of the present invention. Here, 2048
It is assumed that the FFT operation at points ([2 to the 11th power] point) is performed, the bit width of the input data is 8 bits, the bit width of the data memory unit is 12 bits, and the bit width of the internal operation is 10 bits. Also, the variance of the input data is set to 1/4 of the dynamic range. At this time, internal calculation is -5
A value of 12 to +511 can be handled.

This FFT operation circuit is composed of 11 stages, and is provided with a buffer memory 11 for holding input data in the input section. Each of the stages S1 to S11 includes a butterfly computation unit 211 to 2111, a data memory unit 221-2221, and an overflow detection unit 231 to respectively.
2311 and bit shift units 241 to 2411.

Each of the butterfly operation units 211 to 2111 selectively inputs two output data of the preceding stage, repeats the butterfly operation, and sequentially outputs two data. The internal memories 221 to 2211 accumulate all calculation results of the butterfly calculation units 211 to 2111.

Overflow detectors 231 to 2311
Detects whether or not there is an overflow in all the calculation results of the butterfly calculation units 211 to 2111. The bit shift units 241 to 2411 include the overflow detection unit 23.
When overflow is detected in 1 to 2311, the output data of the data memory units 221 to 2211 are bit-shifted.

The processing of each unit is properly timing-controlled by a control unit (not shown). In the above configuration, the processing procedure will be described below with reference to the flowchart shown in FIG.

First, in each of the stages S1 to S11, two pieces of data from the preceding stage are selected to select the butterfly operation unit 21.
1 to 2111. Butterfly computing units 211-2
In 111, since the input bit width is 10 bits, the output bit width is 12 bits (11 bits if doubled, but because complex operation is taken into consideration). This data is not changed and remains as 12 bits in the data memory unit 22.
Nos. 1 to 2211 are written to the overflow detection units 231 to 2311 at the same time.

The overflow detection units 231 to 2311 monitor the overflow of the butterfly operation result, and the overflow detection information is used as the overflow detection information.
It is output to 1 to 2411. Data memory units 221-2
The data written in 211 is stored in the butterfly operation of all input data, and then the bit shift units 241 to 241.
It is output to 1.

The bit shift units 241 to 2411 select the following three operations using the overflow detection information. The first operation outputs the lower 10 bits of the input 12-bit data as it is to the next stage. The second operation is the remaining 1 after removing the least significant bit of the input 12-bit data.
Output 0 bit to the next stage. The third operation outputs the upper 10 bits of the input 12-bit data as it is to the next stage.

No overflow has occurred in these output data. Also, these operations can be switched in units of stages. As a result of performing a simulation using the FFT arithmetic circuit having the above-mentioned configuration, the finally obtained arithmetic precision can ensure the performance which does not practically affect the arithmetic precision using the computer.

Therefore, according to the FFT operation circuit of the present embodiment, it is possible to realize the FFT operation which secures the required operation accuracy with the bit width of the input data being 8 bits and the bit width of the internal operation being 10 bits. Although this may change the calculation accuracy to some extent depending on the input conditions and other requirements,
It can also be grasped by performing a simulation in advance.

The present invention is not limited to the configuration of the above embodiment. For example, the butterfly operation may use a necessary number of arithmetic units in parallel instead of repeatedly using one arithmetic unit. Further, overflow detection and bit shift operation may be performed only in some stages.

The present invention can be implemented by software instead of the hardware configuration. The embodiment is shown in FIG. FIG. 2 is a flowchart showing a one-stage processing process of FFT calculation.

First, the preceding stage or two pieces of data from the preceding stage are selectively input (step A1) and a butterfly operation is performed (step A2). The overflow is detected for the calculation result (step A3), the result is accumulated in the data memory unit (step A4), and the above process is repeated until all the data are selected (step A5).

After the above processing is completed, the stored data is sequentially read from the data memory unit two by two (step A6). At this time, it is judged whether or not the overflow is detected in step A3 (step A7), and the overflow is detected. If not, output without bit shifting (step A
8) If at least one overflow is detected,
All data are bit-shifted and output (step A9),
The processing of one stage is completed.

With the above processing procedure, the present invention can be realized by software. However, it goes without saying that the order of processing can be variously changed. Further, although the case where the radix is 2 has been described in the first and second embodiments, the radix may be 4, 8, ..., And the present invention can be implemented regardless of the radix.

[0042]

As described above, according to the present invention, it is possible to provide the FFT operation method and the FFT operation circuit which can appropriately reduce the redundant portion without impairing the operation accuracy and reduce the circuit scale. .

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing a schematic configuration of an FFT operation circuit according to the present invention.

FIG. 2 is a flowchart showing a one-stage arithmetic processing process of the FFT arithmetic circuit according to the present invention.

FIG. 3 is a conceptual diagram showing a conventional FFT calculation algorithm.

[Explanation of symbols]

 11 ... Buffer memory S1 to S11 ... Stage 21 ... Butterfly operation unit 22 ... Data memory unit 23 ... Overflow detection unit 24 ... Bit shift unit

Claims (4)

[Claims] 1. A butterfly operation process for performing butterfly operation on a plurality of input data, a data storage process for accumulating all output data in a stage of this butterfly operation process and outputting it to the next stage, and an in-stage operation of the butterfly operation process. An FFT, comprising: an overflow detection process for detecting the presence or absence of overflow in the output data; and a bit shift process for performing a bit shift of the output data in the data storage process when an overflow is detected in the overflow detection process. Calculation method. 2. A butterfly operation unit for performing butterfly operation on a plurality of input data, a data storage unit for accumulating all output data in the stage of the butterfly operation unit and outputting it to the next stage, and an entire stage in the butterfly operation unit. An FF comprising: an overflow detection unit that detects the presence or absence of overflow in the output data; and a bit shift unit that performs a bit shift of the output data of the data storage unit when the overflow detection unit detects an overflow.
T arithmetic circuit. 3. An FFT calculation method used in an OFDM demodulator for converting input data in the time domain into data in the frequency domain, wherein an operation word of an arbitrary stage is calculated based on the accuracy of the input data and the simulation result of the area distribution. An FFT operation method comprising: an operation result output process of outputting an operation result with a limited length. 4. An FFT arithmetic circuit used in an OFDM demodulator for converting input data in a time domain into data in a frequency domain, wherein an arithmetic word of an arbitrary stage is calculated based on a simulation result of accuracy and amplitude distribution of the input data. An FFT arithmetic circuit comprising an arithmetic result output means for limiting the length and outputting an arithmetic result.