JPH09312592A - Spread spectrum receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To keep a high communication quality without increasing a circuit scale. SOLUTION: A self-running clock the frequency of which is comparatively low, one to four times with respect to the chip frequency of a received signal and the phase of which is asynchronous with respect to the chip phase of the received signal is used as a system clock. At this time, through a sampling timing by AD converters 106 and 107 are deviated from an ideal point at this time, the sample of the received signal of a deviated timing is interpolated by using a tap coefficient variable waveform forming a filter circuit 108 to approximate a value sampled with ideal timing. At the time of RAKE composing, a signal obtained by sampling the signals of all the paths with an optimum sampling timing is obtained without using an old main path tracking system or an independent tracking system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum receiver used for digital mobile radio communication.

[0002]

2. Description of the Related Art FIG. 18 shows the configuration of a conventional spread spectrum receiver. In FIG. 18, 1000 is a receiving antenna and 1001 is a quasi-coherent detection circuit. 1002,
1003 is a mixer, 1004 is a π / 2 phase shifter, 1005
Is a local oscillator for quasi-synchronous detection. Mixers 1002, 1
The output of 003 is the I component and the Q component of the baseband signal, respectively, and is passed to the respective analog waveform shaping filters 1006 and 1007 and AD converters (analog / digital converters) 1008 and 1009. The circuits after the AD converters 1008, 1009 are all realized by digital circuits. A correlator 1010 calculates correlation values XI and XQ between the received signals RI and RQ and the spread code. The outputs XI and XQ of the correlator 1010 are phase-compensated by the phase compensating circuit 1011 to become YI and YQ, and the sign determiner 1012 determines whether they are positive or negative to obtain the sign determination outputs SI and SQ. Reference numeral 1013 is a timing error detection circuit, which gives a time difference Err between the reception signals RI and RQ and the spread code. The output Err of the timing error detection circuit 1013 is converted into an analog signal by the DA converter (digital / analog converter) 1014, and the output frequency of the voltage controlled clock oscillator 1015 is controlled. The output of the voltage clock oscillator 1015 is the system clock φ.
Controls the operation of all digital circuits after the AD converters 1008, 1009.

In a mobile radio communication environment, a delayed wave is generated due to reflection by a building or the like, and a received signal is the sum of a plurality of signals (paths) having different timings. FIG.
The spread spectrum receiver shown in 8 is for demodulating by selecting only one of these paths having the largest amplitude (main path: main wave). However, if a plurality of correlators are provided here, it is possible to individually demodulate a plurality of paths, and if these demodulated signals are added before the code determination, it is possible to obtain a higher reliability than using only the main path. High code determination can be performed. The method of adding a plurality of path signals as described above is called RAKE combining.

FIG. 19 shows the configuration of a conventional spread spectrum receiver with a RAKE function. In FIG. 19, 1
Reference numeral 100 is a receiving antenna, and 1101 is a quasi-synchronous detection circuit. Reference numerals 1102 and 1103 denote mixers, 1104 denotes a π / 2 phase shifter, and 1105 denotes a quasi-coherent detection local oscillator. The oscillation frequency of the quasi-synchronous detection local oscillator 1105 is substantially equal to the carrier frequency of the received signal. Mixers 1102, 110
The outputs of 3 are the I component and the Q component of the baseband signal, respectively.
106, 1107 and AD converters (analog / digital converters) 1108, 1109. AD converter 1
The circuits after 108, 1109 are all realized by digital circuits. In FIG. 19, the three paths are RA
The example in the case of KE composition is shown, and AD converter 110 is shown.
Circuits from 8 and 1109 onward are provided in three systems. AD
The output digital signals of the converters 1108 and 1109 are buses having a width of several bits, and the shift registers 1110 and 11
11, 1112, 1113, 1114, 1115. The number of stages of these shift registers can be freely changed (there may be 0 stage), and the outputs of these shift registers are adjusted so that the timings of all the pass signals substantially match. 1116, 1117,
A correlator 1118 calculates correlation values XI and XQ between the received signals RI and RQ and the spread code. Correlator 1116,
The outputs XI and XQ of 1117 and 1118 are phase-compensated by phase compensation circuits 1119, 1120 and 1121.
The signals resulting from the phase compensation are added by the adders 1122 and 112.
3 is added, and the sign judgment unit 1124 judges whether the sign is positive or negative, and the sign judgment outputs SI and SQ are obtained. 11
Reference numeral 25 is a timing error detection circuit, which receives the signal RI,
The time difference Err between the RQ and the spread code is given. The output Err of the timing error detection circuit 1125 is converted into an analog signal by the DA converter (digital / analog converter) 1126, and the output frequency of the voltage control clock oscillator 1127 is controlled. The output of the voltage control clock oscillator 1127 is used as the system clock φ, and the AD converter 110
It controls the operation of all digital circuits from 8 and 1109.

FIG. 20 shows another structure of a conventional spread spectrum receiver with a RAKE function. In FIG. 20, reference numeral 1200 is a receiving antenna, and 1201 is a quasi-coherent detection circuit. 1202, 1203 are mixers, 1204 are π
A 1/2 phase shifter 1205 is a local oscillator for quasi-coherent detection. The oscillation frequency of the local oscillator for quasi-synchronous detection 1205 is
It is almost equal to the carrier frequency of the received signal. Mixer 120
The outputs of 2, 1203 are I of the baseband signal, respectively.
The component and the Q component are passed through separate analog waveform shaping filters 1206 and 1207, respectively. FIG. 20 shows an example in which three paths are RAKE-combined, and the subsequent circuits are provided in three systems. Therefore, A
The D converters (analog / digital converters) are provided for three paths (six in total). AD converters 1208 and 120
The output digital signals of 9, 1210, 1211, 1212, 1213 are buses having a width of several bits, and shift registers 1214, 1215, 1216, 1217, 121 are provided.
8 1219. The number of stages of these shift registers can be freely changed (there may be 0 stage), and the outputs of these shift registers are adjusted so that the timings of all the pass signals substantially match. Reference numerals 1220, 1221 and 1222 denote correlators, which calculate correlation values XI and XQ between the received signals RI and RQ and the spread code. Output X of the correlators 1220, 1221, 1222
I and XQ are phase compensation circuits 1223, 1224, 122.
5, the phase is compensated. The signals resulting from the phase compensation are added by adders 1226 and 1227, and the sign determiner 1228 determines whether the signals are positive or negative, and the code determination outputs SI and SQ are obtained. 1229, 1230, 1231
Is a timing error detection circuit for receiving signals RI, RQ
And the spread code time difference Err. Output Err of Timing Error Detection Circuit 1229, 1230, 1231
Is a DA converter (digital / analog converter) 123
2, 1233, 1234 are converted into analog signals and the voltage controlled clock oscillators 1235, 1236, 12
The output frequency of 37 is controlled. 20 differs from the example of FIG. 19 in that the system clock of the demodulation system is independent for each path. That is, the output of the voltage control clock oscillator 1235 controls the operation of the demodulation system (AD converters 1208 and 1209, shift registers 1214 and 1215, correlator 1220) of path 1 as the system clock φ1, and the output of the voltage control clock oscillator 1236. Is
As the system clock φ2, a demodulation system of path 2 (AD converters 1210 and 1211, shift registers 1216 and 12)
17, the operation of the correlator 1221), and the output of the voltage controlled clock oscillator 1237 is the demodulation system of the path 3 as the system clock φ3 (AD converters 1212 and 1213, shift registers 1218 and 1219, correlator 12221).
Is to control the operation of.

[0006]

However, in the above-described conventional spread spectrum receiver, when the spread spectrum signal is received, it is necessary to optimally control the sampling timing of the received signal by the AD converter. If the sampling timing is not optimal, the received signal power cannot be used efficiently and there is a problem that the communication quality deteriorates.

In the case of the spread spectrum receiver shown in FIG. 18, the system clock of the demodulation digital circuit is
An analog voltage control clock oscillator 1015 generates the control voltage to the DA converter 101.
However, when such an analog element is used, there is a problem that the operation becomes unstable, it becomes difficult to downsize the entire apparatus, and the number of adjustment points increases.

Further, in the case of the spread spectrum receiver with the RAKE function shown in FIG. 19, synchronous tracking of the spread code is performed only on the main path signal, which is called main path tracking. As a result, the AD converter 11
The sampling timings of 08 and 1109 are controlled so as to match the optimum sampling timing of the main path signal, and the main path signal can be captured at the optimum sampling timing. However, since the sampling timing for signals of paths other than the main path is controlled by the number of stages of the shift registers 1110 to 1115, the difference from the optimum sampling timing of the main path signal is an integral multiple of the sampling cycle of the AD converters 1108 and 1109. Can only be set to. Here, the delay time of the main path of each path rarely becomes an integral multiple of the sampling period of the AD converters 1108 and 1109, and in many cases, signals of paths other than the main path are captured at the optimum sampling timing. It is not possible. In order to capture at a timing closer to the optimum sampling timing, the AD converters 1108, 110
It is necessary to increase the sampling frequency of 9 and not only the current consumption of the AD converter increases but also the cost of hardware increases.

Further, in the case of the spread spectrum receiver with the RAKE function shown in FIG. 20, synchronization tracking is performed independently for all path signals, and the AD converters 120 of each of them are used.
The sampling timings of 8 to 1213 are controlled so as to coincide with the optimum sampling timing of each path signal, which is called independent tracking. Thereby, the signals of all the paths can be sampled at the optimum timing. However, the system clock oscillators (voltage controlled clock oscillators 1235 to 123) are all independent for each RAKE combining path.
7) and the DA converters 1232 to 1234 must be provided, which causes a problem that the scale of hardware increases.

The present invention solves such a conventional problem, and an object of the present invention is to provide a spread spectrum receiver capable of maintaining high communication quality without increasing the scale of hardware. .

[0011]

In order to achieve the above object, the present invention has a relatively low frequency of about 1 to 4 times the chip frequency of a received signal and a chip phase of the received signal. A free-running clock whose phase is asynchronous is used as the system clock. At this time, the sampling timing by the AD converter deviates from the ideal point, but the tap coefficient variable type waveform shaping filter is used to interpolate the received signal sample with the deviation of the sampling timing, and approximate the sampled value at the ideal sampling timing. . The tap coefficient of the variable tap coefficient waveform shaping filter is calculated from the timing error detected by the timing error detection circuit of the received signal. As a result, the system clock for operating all the digital circuits including the AD converter may be a free-running clock that is asynchronous with the received signal.
Therefore, the voltage-controlled clock oscillator and the DA converter that generates the control voltage for the voltage-controlled clock oscillator are unnecessary, and the number of analog elements in the device can be reduced.

Further, according to the above configuration, when performing RAKE combining, there is no need to increase the sampling frequency of the AD converter in the main path tracking method or to provide an independent system clock for each path in the independent tracking method. In addition, it is possible to obtain the value obtained by sampling the signals of all paths at the optimum sampling timing,
High communication quality can be maintained without increasing current consumption or hardware scale.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is based on two systems of I and Q by multiplying a received spread spectrum signal by a local oscillation signal of a frequency substantially equal to its carrier frequency. A quasi-synchronous detection circuit for converting into a band signal, an analog-digital converter for sampling the output signal of the quasi-synchronous detection circuit with a fixed sampling clock having a frequency substantially equal to several times the chip frequency of the received spread spectrum signal, A waveform shaping filter circuit driven by a fixed sampling clock and using a variable tap coefficient digital FIR filter for shaping the output of the analog-digital converter;
An output of the waveform shaping filter circuit is an input, a demodulation correlator including a demodulation spread code generator for demodulating a received spread spectrum signal, a digital multiplier and an adder, and an output of the demodulation correlator. In order to determine whether the signal is positive or negative, the phase error generated at the time of quasi-coherent detection is estimated by observing the output signal of the demodulation correlator, and the error is relative to the output signal of the demodulation correlator. A phase compensating circuit for compensating for the minute component, a sign judging device for individually judging whether the output of the phase compensating circuit is positive or negative by the I component and the Q component,
A timing error detection circuit that measures the timing error between the received spread spectrum signal and the demodulated spread code, and the most efficient way to obtain the energy of the received spread spectrum signal based on the timing error signal received from the timing error detection circuit. A spread spectrum receiver including a waveform shaping filter tap coefficient calculator for calculating a tap coefficient and updating the tap coefficient of the tap coefficient variable type waveform shaping filter circuit, and all digital circuits including an AD converter. Since a free-running clock that is asynchronous with the received signal is sufficient as the system clock for operating the, the voltage-controlled clock oscillator and the DA converter that generates the control voltage for it are unnecessary, and the number of analog elements in the device can be reduced. You can

According to the second aspect of the present invention, the phase compensation circuit in the latter stage of the demodulation correlator is eliminated, and instead of the waveform shaping filter tap coefficient calculator and the variable tap shaping waveform shaping filter circuit, Complex waveform shaping filter that estimates the phase error of the demodulation correlator output that occurs during quasi-coherent detection and multiplies the signal for compensating for the phase error by the tap coefficient specified for the variable tap coefficient waveform shaping filter circuit. The spread spectrum receiver according to claim 1, further comprising a tap coefficient calculator and a complex tap coefficient variable waveform shaping filter circuit whose characteristics are determined by the complex tap coefficient given from the complex waveform shaping filter tap coefficient calculator. In addition to the effect of the invention described in claim 1, since the phase compensation is performed before the correlator, a squarer is used in the timing error detection circuit. That it is unnecessary, the characteristics of the timing error detection is improved. Moreover, since the phase compensating circuit before the code determiner is unnecessary, the hardware scale can be reduced.

According to a third aspect of the present invention, the spread spectrum signal received is converted into a two-system baseband signal of I and Q by multiplying a local oscillation signal having a frequency substantially equal to its carrier frequency. A quasi-synchronous detection circuit, an analog digital converter for sampling the output signal of the quasi-synchronous detection circuit with a fixed sampling clock having a frequency substantially equal to several times the chip frequency of the received spread spectrum signal, and the fixed sampling clock. Driven by the output of the analog-to-digital converter, and a set of variable number of shift registers for preliminarily removing the timing difference of the path to be demodulated; Variable tap coefficient digital FIR for waveform shaping of register output A waveform shaping filter circuit using a filter, a demodulation correlator for demodulating a received spread spectrum signal with the output of the waveform shaping filter circuit as an input, and a positive / negative sign determination of the output signal of the demodulation correlator. Therefore, the phase error generated at the time of quasi-coherent detection is estimated by observing the output signal of the demodulation correlator,
A phase compensation circuit for compensating for the error component of the output signal of the demodulation correlator, and an addition for individually adding the phase-compensated demodulation correlator outputs of all the paths to be RAKE-combined for the I component and the Q component. , A code determiner for individually determining whether the addition result is positive or negative by an I component and a Q component, a timing error detection circuit for measuring a timing error of a received spread spectrum signal and a demodulated spread code, and the timing error detection circuit. A waveform shaping filter for calculating the tap coefficient that most efficiently acquires the energy of the received spread spectrum signal based on the timing error signal received from the above, and updating the tap coefficient of the tap coefficient variable type waveform shaping filter circuit. A tap coefficient calculator, a set of the shift register, a waveform shaping filter circuit, a demodulation correlator, a phase compensation circuit, and a timing A difference detecting circuit and the waveform shaping filter tap coefficient calculator, a spread spectrum receiver with a RAKE function with the number of paths to be RAKE combining,
Since the system clock for operating all the digital circuits including the AD converter is a free-running clock that is asynchronous with the received signal, the voltage-controlled clock oscillator and the DA converter for generating the control voltage are unnecessary. The number of analog elements in the device can be reduced. In addition, when performing RAKE combining, A in the main path tracking method is used.
Without increasing the sampling frequency of the D converter or providing an independent system clock for each path in the independent tracking method, it is possible to obtain a value obtained by sampling the signals of all paths at the optimum sampling timing, High communication quality can be maintained without increasing current consumption or hardware scale.

According to a fourth aspect of the present invention, the phase compensation circuit in the subsequent stage of the demodulation correlator is eliminated, and instead of the waveform shaping filter tap coefficient calculator and the variable tap coefficient waveform shaping filter circuit, Complex waveform shaping filter that estimates the phase error of the demodulation correlator output that occurs during quasi-coherent detection and multiplies the signal for compensating for the phase error by the tap coefficient specified for the variable tap coefficient waveform shaping filter circuit. 4. The spread spectrum receiver according to claim 3, comprising a tap coefficient calculator and a complex tap coefficient variable waveform shaping filter circuit whose characteristics are determined by the complex tap coefficient given from the complex waveform shaping filter tap coefficient calculator. In addition to the effect of the invention described in claim 3, since the phase compensation is performed before the correlator, a squarer is used in the timing error detection circuit. It is not necessary to have the characteristics of the timing error detection is improved. Moreover, since the phase compensating circuit before the code determiner is unnecessary, the hardware scale can be reduced.

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows claim 1 of the present invention.
2 shows a configuration of a spread spectrum receiver in the first exemplary embodiment corresponding to FIG. In FIG. 1, 100 is a receiving antenna and 101 is a quasi-coherent detection circuit. 10
Reference numerals 2 and 103 are mixers, 104 is a π / 2 phase shifter, and 105 is a local oscillator for quasi-coherent detection. Mixers 102, 103
Of the baseband signal are I and Q components, respectively, and are connected to individual AD converters (analog / digital converters) 106 and 107, respectively. The circuits after the AD converters 106 and 107 are all realized by digital circuits. The output digital signals of the AD converters 106 and 107 are buses of several bits and are input to the waveform shaping filter circuit 108. Waveform shaping filter circuit 1
The outputs DI and DQ of 08 are input to the correlator 109, the outputs XI and XQ of the correlator 109 are input to the phase compensation circuit 110, and the outputs YI and YQ of the phase compensation circuit 110 are input to the code determination unit 111. To be done. The outputs EI, LI, EQ, and LQ of the waveform shaping filter circuit 108 are input to the timing error detection circuit 112, and the output Err of the timing error detection circuit 112 is input to the waveform shaping filter tap coefficient calculator 113. The shaping filter tap coefficient calculator 113 provides the tap shaping coefficient setting information to the waveform shaping filter circuit 108.

Here, the waveform shaping filter circuit 108 is
Any of the configurations shown in FIGS. 2, 3, and 4 may be used. Further, the waveform shaping filter circuit 108 may be an FIR type digital filter as shown in FIG. In FIG. 5, 2
Reference numeral 15 is a register, and a plurality of registers are combined to form a shift register having the same number of stages as the number of taps. A digital multiplier 216 exists in the same number as the number of taps, and outputs the multiplication result of the tap coefficient given from the outside and the value of each register 215. An adder 217 adds the outputs of all the digital multipliers 216 to obtain the output value of the filter. 6 shows the configuration of the timing error detection circuit 112, and FIG. 7 shows the configuration of the correlator 109.

Next, the operation of the first embodiment will be described. First, the signals received from the receiving antenna 100 are the mixers 102 and 103, the π / 2 phase shifter 104,
The quasi-coherent detection circuit 101 composed of the local oscillator 105 for quasi-coherent detection performs quasi-coherent detection to obtain I and Q components of the baseband signal, and the individual AD converters 1
Sampled by 06 and 107 and converted into digital data RI and RQ. Here, the circuits after the AD converters 106 and 107 are all free-running clocks whose frequency is about 1 to 4 times the chip frequency of the received signal and whose phase is asynchronous with respect to the chip phase of the received signal. Work according to. Therefore, the AD converters 106 and 107
The input data of R is sampled with deviation from the ideal timing chart 9 (d) as shown in FIG.
I and RQ. The tap coefficient of the tap coefficient variable waveform shaping filter for demodulation in the waveform shaping filter circuit 108 is
As shown in FIG. 9 (g), it is set so as to obtain the maximum output when the signals RI and RQ whose sampling timings are shifted are input. This timing error is
It is calculated by the timing error detection circuit 112 described later.

The output of the waveform shaping filter circuit 108 is multiplied by the spread code in the correlator 109 and integrated for one symbol period to become correlator outputs XI and XQ. The phase compensation circuit 110 detects a phase error due to the quasi-coherent detection of the correlator outputs XI and XQ, performs a phase compensation calculation for canceling the detected phase error on XI and XQ, and outputs Y.
Give I and YQ. The code determiner 111 receives inputs YI, Y
The sign of each Q is determined and the sign determination outputs SI and SQ are given. Where XI, XQ, YI, YQ, SI, SQ
Is a signal of 1 sample per 1 symbol.

Next, the operation of the timing error detection circuit 112 will be described with reference to FIGS. 6 and 7. The early spreading code generator 302 and the late spreading code generator 307 in the timing error detection circuit 112 generate the same spreading code as that generated by the spreading code generator 401 in the demodulation correlator 109. Waveform shaping filter circuit 10
When the configuration of FIG. 2 is used for No. 8, the timing of the spreading code generated by the early spreading code generator 302 is higher than the timing of the spreading code generated by the spreading code generator 401 in the correlator 109 for demodulation. Advance by a certain time δ,
The timing of the spreading code generated by the Late spreading code generator 307 is the spreading code generator 40 in the correlator 109 for demodulation.
1 is delayed by a certain time δ from the timing of the spread code generated. The waveform shaping filter circuit 108 is shown in FIG.
Alternatively, when the configuration of FIG. 4 is used, the timing of the spreading code generated by the Early spreading code generator 302 and the Late spreading code generator 307 is the spreading code generated by the spreading code generator 401 in the demodulating correlator 109. It is the same as the code timing.

With the above setting, when the sampling timing of the AD converters 106 and 107 is later than the ideal sampling timing, the amplitude of the output of the Early branch correlator 300 becomes large, and the AD converters 106 and 107 are
When the sampling timing of 107 is earlier than the ideal sampling timing, the amplitude of the output of the Late branch correlator 301 becomes large. Next, the Early branch correlator 300 and
The output power of the Late branch correlator 301 is calculated by the Early branch power measuring device 312 and the Late branch power measuring device 313,
The subtracter 321 takes the difference to obtain the output Err of the timing error detection circuit 112. With the above configuration, Err takes a negative value when the sampling timing of the AD converters 106 and 107 is later than the ideal sampling, and Err takes a negative value when the sampling timing of the AD converters 106 and 107 is earlier than the ideal sampling. Takes a positive value.

Next, a method of setting the tap coefficient of the waveform shaping filter in the waveform shaping filter circuit 108 will be described. The received signal that has been quasi-coherently detected and converted into a baseband signal is generated by arranging and adding the root Nyquist single pulses shown in FIG. 8A at chip cycle Tc intervals as shown in FIG. 8B. It becomes something like 8 (c).
This received signal is converted by the AD converters 106 and 107 in FIG.
When the received signal is sampled at the timing as shown in FIG. 9D (this sampling timing is ideal), the tap coefficient sequence as shown in FIG. It is necessary to pass the waveform shaping filter that it has. In addition, the received signal is shown in FIG.
When sampling is performed at a timing deviated from the ideal timing by d as in (f), in order to most efficiently capture this received signal in the digital circuit,
It is necessary to pass a waveform shaping filter having a tap coefficient sequence as shown in (g). The timing error d is calculated by the above timing error detection circuit 112, and in the form of the error signal Err, the waveform shaping filter tap coefficient calculator 11
Given to 3. Waveform shaping filter tap coefficient calculator 1
Reference numeral 13 supplies the tap coefficient calculated based on the error signal Err to the waveform shaping filter circuit 108.

Here, when the configuration of FIG. 2 or FIG. 3 is applied to the waveform shaping filter circuit 108, the same tap coefficient is given to all the tap coefficient variable waveform shaping filters in the waveform shaping filter circuit 108. When the waveform shaping filter circuit 108 has the configuration of FIG. 4, among all the tap coefficient variable waveform shaping filters in the waveform shaping filter circuit 108, the EI and EQ filters 209 and 212 have D
A tap coefficient in a form that is earlier by δ than the tap coefficient given to the I and DQ filters 211 and 214 is given, and the DI and DQ filter 2 is given to the LI and LQ filters 210 and 213.
A tap coefficient that is slower than the tap coefficient given to 11, 214 by δ is given.

As described above, according to the first embodiment,
Since the system clock for operating all digital circuits including the AD converter is a free-running clock that is asynchronous with the received signal, the voltage-controlled clock oscillator and the DA converter that generates the control voltage for the system are unnecessary. The number of analog elements in the device can be reduced.

(Second Embodiment) FIG. 10 shows the configuration of a spread spectrum receiver in a second embodiment corresponding to claim 2 of the present invention. In FIG. 10, 50
Reference numeral 0 is a receiving antenna, and 501 is a quasi-coherent detection circuit. 5
02 and 503 are mixers, 504 is a π / 2 phase shifter, and 505
Is a local oscillator for quasi-synchronous detection. Mixer 502, 50
The outputs of 3 are the I component and the Q component of the baseband signal, respectively, and are connected to the individual AD converters (analog / digital converters) 506 and 507, respectively. AD
The circuits after the converters 506 and 507 are all realized by digital circuits. The output digital signals of the AD converters 506 and 507 are buses of several bits and are input to the complex waveform shaping filter circuit 508. The outputs DI and DQ of the complex waveform shaping filter circuit 508 are input to the correlator 509, and the outputs XI and XQ of the correlator 509 are the code determiner 511 and the complex waveform shaping filter tap coefficient calculator 5.
12 is input. Also, the output S of the sign determiner 511
I and SQ are the coherent timing error detection circuit 5
10 is input. The outputs EI and EQ of the complex waveform shaping filter circuit 508 are input to the coherent timing error detection circuit 510, and the output Err of the coherent timing error detection circuit 510 is input to the complex waveform shaping filter tap coefficient calculator 512. From the waveform shaping filter tap coefficient calculator 512, tap coefficient setting information is given to the complex waveform shaping filter circuit 508.

Here, the complex waveform shaping filter circuit 508
May have any of the configurations shown in FIGS. 11, 12, and 13.
Further, the complex waveform shaping filter circuit 508 may be an FIR type digital filter as shown in FIG.
In FIG. 14, reference numeral 610 is a two-column register, which is combined to form a two-parallel shift register having the same number of stages as the number of taps. Reference numeral 611 denotes a complex digital multiplier, which has the same number as the number of taps and outputs the multiplication result of the complex tap coefficient given from the outside and the value of each two-column register 610. An adder 612 adds the outputs of all the complex digital multipliers 611 to obtain the output value of the filter. In addition, the coherent timing error detection circuit 51
The configuration of 0 is shown in FIG. The configuration of correlator 509 is the same as that shown in FIG.

Next, the operation of the second embodiment will be described. First, the signals received from the receiving antenna 500 are the mixers 502 and 503, the π / 2 phase shifter 504,
The quasi-synchronous detection circuit 501 including the local oscillator for quasi-synchronous detection quasi-coherently detects the I-component and the Q-component of the baseband signal.
It is sampled by 06 and 507 and converted into digital data RI and RQ. Here, the circuits after the AD converters 506 and 507 are all free-running clocks whose frequency is about 1 to 4 times the chip frequency of the received signal and whose phase is asynchronous with respect to the chip phase of the received signal. Work according to. Therefore, the AD converters 506 and 507
As shown in FIG. 9F, the input data of is sampled with deviation from the ideal timing, and becomes RI and RQ. The tap coefficient of the variable tap coefficient for demodulation in the complex complex waveform shaping filter circuit 508 is
As shown in FIG. 9 (g), it is set so as to obtain the largest output when the signals RI and RQ with the dumping timings shifted are input. This timing error is
Coherent timing error detection circuit 510 described later
Is calculated by

The output of the complex waveform shaping filter circuit 108 is multiplied by the spread code inside the correlator 509 and integrated for one symbol period to become correlator outputs XI and XQ. The sign determiner 511 determines whether the inputs XI and XQ are positive or negative, and provides the sign determination outputs SI and SQ. Here, XI, XQ, SI, and SQ are signals of 1 sample per 1 symbol.

Next, the operation of the coherent timing error detection circuit 510 will be described. FIG. 15 shows the configuration of the coherent timing error detection circuit 510. In the coherent timing error detection circuit 510,
The early spreading code generator 702 and the late spreading code generator 707 are the spreading code generator 4 in the correlator 509 for demodulation.
Generates the same spreading code that 01 occurs. When the configuration of FIG. 11 is used for the complex waveform shaping filter circuit 508, the timing of the spreading code generated by the Early spreading code generator 702 is the spreading code generated by the spreading code generator 401 in the demodulation correlator 509. By a certain time δ earlier than the timing of, and the Late spread code generator 707
The timing of the spreading code generated by the
The timing of the spreading code generated by the spreading code generator 401 in 09 is delayed by a certain time δ. When the configuration of FIG. 12 or FIG. 13 is used for the complex waveform shaping filter circuit 508, the Early spreading code generator 702 and
The timing of the spreading code generated by the Late spreading code generator 707 is determined by the spreading code generator 40 in the correlator 509 for demodulation.
The timing is the same as the timing of the spread code generated by 1.

With the above settings, when the sampling timing of the AD converters 506 and 507 is later than the ideal sampling timing, the amplitude of the output of the Early branch correlator 700 becomes large, and the AD converter 506,
When the sampling timing of 507 is earlier than the ideal sampling timing, the amplitude of the output of the Late branch correlator 701 becomes large. Next, the Early Branch Correlator 700 and
The output power of the Late branch correlator 701 is calculated by the Early branch power measuring device 712 and the Late branch power measuring device 713,
The subtracter 721 takes the difference to obtain the output Err of the coherent timing error detection circuit 510.

The early-branch power measuring device 312 and the late-branch power measuring device 313 in the timing error detection circuit 112 shown in the first embodiment are a squarer as means for collecting the phases of input signals in a certain direction for power measurement. However, since the square operation deteriorates the signal-to-noise ratio, the performance of the timing error detection circuit 112 is relatively poor.
On the other hand, the coherent timing error detection circuit 5
The Early branch power measuring device 712 and the Late branch power measuring device 713 in 10 include multipliers 714, 715, 718, and 719 for performing multiplication with the code determination output instead of the squarer. Output E of complex waveform shaping filter circuit 508
I, LI, EQ, and LQ have already been phase-compensated, and by multiplying the output of the code determining unit 511, the phases of the output signals of the Early branch power measuring unit 712 and the Late branch power measuring unit 713 are calculated. Can be aligned in a certain direction. Moreover, since the square operation is not used, the signal-to-noise ratio is not deteriorated and has good characteristics. With the above configuration, Err takes a negative value when the sampling timing of the AD converters 506 and 507 is later than the ideal sampling, and Err takes a negative value when the sampling timing of the AD converters 506 and 507 is earlier than the ideal sampling. Takes a positive value.

Next, a method of setting the tap coefficient of the complex waveform shaping filter in the complex waveform shaping filter circuit 508 will be described. The received signal that has been quasi-coherently detected and converted into a baseband signal is generated by arranging and adding the root Nyquist single pulses shown in FIG. 8A at chip cycle Tc intervals as shown in FIG. 8B. It becomes something like 8 (c). When this received signal is sampled by the AD converters 506 and 507 at the timing as shown in FIG. 9D (this sampling timing is ideal), the most efficient way to take this received signal into the digital circuit is , It is necessary to pass a complex waveform shaping filter having a tap coefficient sequence as shown in FIG. Also,
When the received signal is sampled at the timing deviated from the ideal timing by d as shown in FIG. 9F, in order to capture the received signal into the digital circuit most efficiently, as shown in FIG. 9G. It is necessary to pass a complex waveform shaping filter having a tap coefficient sequence. The timing error d is calculated by the above coherent timing error detection circuit 510 and is given to the complex waveform shaping filter tap coefficient calculator 512 in the form of the error signal Err.
The complex waveform shaping filter tap coefficient calculator 512 first calculates the tap coefficient calculated based on the error signal Err. Next, the phase due to the quasi-coherent detection of the correlator outputs XI and XQ is detected, the phase compensation complex coefficient that cancels the detected phase error is calculated, and the above tap coefficient is multiplied to obtain the complex tap coefficient. Ask. Then, the calculated complex tap coefficient is given to the complex waveform shaping filter circuit 508.

Here, the complex waveform shaping filter circuit 508
When the configuration of FIG. 11 or 12 is adopted, the same complex tap coefficient is given to all the complex tap coefficient variable complex waveform shaping filters in the complex waveform shaping filter circuit 508. When the complex waveform shaping filter circuit 508 has the configuration of FIG. 13, among all the complex tap coefficient variable complex waveform shaping filters in the complex waveform shaping filter circuit 508,
The Early filter 607 includes the Demod filter 609.
A complex tap coefficient in a form that is earlier by δ than the complex tap coefficient given to is given to the Late filter 608, and a complex tap coefficient that is delayed by δ from the complex tap coefficient given to the Demod filter 609 is given to the Late filter 608.

As described above, according to the second embodiment,
Since the system clock for operating all digital circuits including the AD converter is a free-running clock that is asynchronous with the received signal, the voltage-controlled clock oscillator and the DA converter that generates the control voltage for the system are unnecessary. The number of analog elements in the device can be reduced. Further, since the phase compensation is performed before the correlator, it is not necessary to use a squarer in the timing error detection circuit, and the characteristics of the timing error detection circuit are improved. Furthermore, since the phase compensation circuit before the code determiner is unnecessary, the hardware scale can be reduced.

(Third Embodiment) FIG. 16 shows the configuration of a spread spectrum receiver in a third embodiment corresponding to claim 3 of the present invention. In FIG. 16, 80
Reference numeral 0 is a receiving antenna, and 801 is a quasi-synchronous detection circuit. 8
02 and 803 are mixers, 804 is a π / 2 phase shifter, and 805
Is a local oscillator for quasi-synchronous detection. Mixers 802, 80
The outputs of 3 are the I component and the Q component of the baseband signal, respectively, and are connected to the individual AD converters (analog / digital converters) 806 and 807, respectively. AD
The circuits after the converters 806 and 807 are all realized by digital circuits, and the same number of paths as RAKE combining is provided. The output digital signals of the AD converters 806 and 807 are buses of several bits, and the number-of-stage variable shift registers 808, 809, 810, 811, 812, 8
Waveform shaping filter circuits 814, 815, 8
16 is input. Waveform shaping filter circuits 814 and 81
The outputs DI and DQ of the No. 5 and 816 are the correlators 817 and 81, respectively.
8 and 819, and correlators 817, 818 and 819
Outputs XI, XQ of the phase compensation circuits 820, 821, 8
22 and the phase compensation circuits 820, 821, 822.
The outputs YI and YQ of are input to adders 823 and 824, and the outputs thereof are input to the sign determination unit 825. Also,
Output E of waveform shaping filter circuits 814, 815, 816
I, LI, EQ, and LQ are timing error detection circuits 82.
6, 827, 828 and the output Err of the timing error detection circuits 826, 827, 828 are input to the waveform shaping filter tap coefficient calculators 829, 830, 831 and the waveform shaping filter tap coefficient calculators 829, 83.
From 0 and 831, waveform shaping filter circuits 814 and 81
Setting information of the tap coefficient is given to 5, 816.

Here, the waveform shaping filter circuits 814, 8
15, 816 may have any of the configurations of FIG. 2, FIG. 3, FIG. 4 and FIG. In addition, the timing error detection circuit 826,
The configurations of 827 and 828 are the same as those shown in FIG.
The configurations of correlators 817, 818, and 819 are the same as those shown in FIG.

Next, the operation of the third embodiment will be described. First, the signal received from the receiving antenna 800 is quasi-coherently detected by a quasi-coherent detection circuit 801 including mixers 802, 803, a π / 2 phase shifter 804, and a quasi-coherent detection local oscillator 805, and I of the baseband signal is detected. Component and Q component, each of which is an individual AD converter 80
6, 807, and converted into digital data RI, RQ. Here, this AD converter 8
The circuits from 06 and 807 all operate at a frequency of 1 to 4 times the chip frequency of the received signal and operate according to a free-running clock whose phase is asynchronous with respect to the chip phase of the received signal. Therefore, the input data of the AD converters 806 and 807 are sampled with deviation from the ideal timing chart 9 (d) as shown in FIG. 9 (f), and RI,
It becomes RQ. Waveform shaping filter circuits 814, 815, 8
As shown in FIG. 9G, the tap coefficient of the demodulation tap coefficient variable waveform shaping filter in 16 is set so as to obtain the largest output when the signals RI and RQ whose sampling timings are shifted are input. ing. This timing error is caused by timing error detection circuits 826, 8 described later.
27, 828. Further, the timing of the path to be demodulated has a difference of several chips, but this timing difference is almost eliminated by the stage number variable shift registers 808 to 813, and the precise timing adjustment is performed by the waveform shaping filter circuits 814 and 815. 816.

Waveform shaping filter circuits 814, 815, 8
The output of 16 is multiplied by the spread code inside the correlators 817, 818, and 819 and integrated by one symbol period,
It becomes the correlator outputs XI and XQ. Phase compensation circuit 820, 8
21 and 822 detect a phase error due to the quasi-coherent detection of the correlator outputs XI and XQ, perform a phase compensation calculation for canceling the detected phase error on XI and XQ, and output YI,
Give YQ. The adders 823 and 824 combine the outputs YI and YQ having the number of paths to be RAKE combined into I and Q individually. The code determination unit 825 determines whether the outputs of the adders 823 and 824 are positive or negative, and determines the code determination outputs SI and S.
Give Q. Where XI, XQ, YI, YQ, SI,
SQ is a signal of 1 sample per 1 symbol.

Next, the operation of the timing error detection circuits 826, 827, 828 will be described with reference to FIGS. 6 and 7. Timing error detection circuit 826, 82
Early Spread Code Generator 302 and Late in 7,828
The spread code generator 307 is a correlator 817, 81 for demodulation.
Generates the same spreading code as that generated by spreading code generator 401 in 8, 819. Waveform shaping filter circuit 81
When the configuration of FIG. 2 is used for 4, 815 and 816, E
The timing of the spreading code generated by the arly spreading code generator 302 is set earlier than the timing of the spreading code generated by the spreading code generator 401 in the correlators 817, 818, and 819 for demodulation by a certain time δ, The timing of the spreading code generated by the Late spreading code generator 307 is the spreading code generator 401 in the correlators 817, 818 and 819 for demodulation.
Is delayed by a certain time δ after the timing of the spreading code. Waveform shaping filter circuits 814 and 81
When using the configuration of FIG. 3 or FIG.
The timing of the spreading code generated by the Early spreading code generator 302 and the Late spreading code generator 307 is the spreading code generator 401 in the demodulating correlators 817, 818, and 819.
Is the same as the timing of the spreading code.

With the above settings, when the sampling timing of the AD converters 806 and 807 is later than the ideal sampling timing, the amplitude of the output of the Early branch correlator 300 becomes large and the AD converters 806,
When the sampling timing of 807 is earlier than the ideal sampling timing, the amplitude of the output of the Late branch correlator 301 becomes large. Next, the Early branch correlator 300 and
The output power of the Late branch correlator 301 is calculated by the Early branch power measuring device 312 and the Late branch power measuring device 313,
The subtractor 321 takes the difference to obtain the output Err of the timing error detection circuits 826, 827, 828. With the above configuration, when the sampling timing of the AD converters 806 and 807 is later than the ideal sampling,
When Err has a negative value and the sampling timing of the AD converters 806 and 807 is earlier than the ideal sampling, Err has a positive value.

Next, the waveform shaping filter circuits 814 and 81
A method of setting the tap coefficient of the waveform shaping filter in Nos. 5 and 816 will be described. The received signal that has been quasi-coherently detected and converted into a baseband signal is generated by arranging and adding the root Nyquist single pulses shown in FIG. 8A at chip cycle Tc intervals as shown in FIG. 8B. It becomes something like 8 (c). This received signal is the AD converter 106, 1
When the signal is sampled by 07 at the timing as shown in FIG. 9D (this sampling timing is ideal), in order to capture the received signal into the digital circuit most efficiently, as shown in FIG. 9E. It is necessary to pass a waveform shaping filter having a tap coefficient sequence. Further, when the received signal is sampled at a timing deviated from the ideal timing by d as shown in FIG. 9F, in order to capture the received signal into the digital circuit most efficiently, the signal shown in FIG. It is necessary to pass a waveform shaping filter having such a tap coefficient sequence. The timing error d is the timing error detection circuit 826, 82 described above.
7, 828 and waveform shaping filter tap coefficient calculators 829, 830, 83 in the form of the error signal Err.
Given to one. Waveform shaping filter tap coefficient calculator 8
29, 830, and 831 use the tap coefficients calculated based on the error signal Err as waveform shaping filter circuits 814 and 81.
5, 816

Here, the waveform shaping filter circuits 814, 8
When the configuration of FIG. 2 or FIG.
The same tap coefficient is given to all the tap coefficient variable waveform shaping filters in the waveform shaping filter circuits 814, 815, and 816. Waveform shaping filter circuits 814, 815, 8
When 16 has the configuration of FIG. 4, among all the tap coefficient variable waveform shaping filters in the waveform shaping filter circuits 814, 815, 816, the EI and EQ filters 209,
212 is given a tap coefficient that is earlier by δ than the tap coefficient given to the DI and DQ filters 211 and 214, and DI and DI are given to the LI and LQ filters 210 and 213.
A tap coefficient which is delayed by δ from the tap coefficient given to the DQ filters 211 and 214 is given.

As described above, according to the third embodiment,
Since the system clock for operating all digital circuits including the AD converter is a free-running clock that is asynchronous with the received signal, the voltage-controlled clock oscillator and the DA converter that generates the control voltage for the system are unnecessary. The number of analog elements in the device can be reduced. Further, the signals of all paths are sampled at the optimum sampling timing without increasing the sampling frequency of the AD converter in the main path tracking method or providing an independent system clock for each path in the independent tracking method. A value can be obtained, and high communication quality can be maintained without increasing current consumption or hardware scale.

(Fourth Embodiment) FIG. 17 shows the configuration of a spread spectrum receiver according to a fourth embodiment of the present invention. In FIG. 17, 90
Reference numeral 0 is a receiving antenna, and 901 is a quasi-synchronous detection circuit. 9
02 and 903 are mixers, 904 is a π / 2 phase shifter, and 905
Is a local oscillator for quasi-synchronous detection. Mixers 902, 90
The outputs of 3 are the I component and the Q component of the baseband signal, respectively, and are connected to the individual AD converters (analog / digital converters) 906 and 907, respectively. AD
The circuits after the converters 906 and 907 are all realized by digital circuits, and the same number of paths as RAKE combining is provided. The output digital signals of the AD converters 906 and 907 are buses of several bits, and the number-of-stages variable shift registers 908, 909, 910, 911, 912 and 913.
Through the complex waveform shaping filter circuits 914, 915, 9
16 is input. Complex waveform shaping filter circuit 914,
The outputs DI and DQ of 915 and 916 are the correlators 917 and 9 respectively.
18, 919, and the correlators 917, 918, 91
The outputs XI and XQ of 9 are input to the adders 920 and 921, and the outputs thereof are input to the code determination unit 922. Also,
The outputs SI and SQ of the code determiner 922 are input to the coherent timing error detection circuits 923, 924 and 925. Complex waveform shaping filter circuits 914, 915, 9
The 16 outputs EI and EQ are input to the coherent timing error detection circuits 923, 924, and 925, and the coherent timing error detection circuits 923, 924, and 92 are input.
The output Err of No. 5 is input to the complex waveform shaping filter tap coefficient calculators 926, 927, 928, and the complex waveform shaping filter tap coefficient calculators 926, 927, 928 output the complex waveform shaping filter tap coefficients 914, 915, 916.
Setting information of tap coefficients is given.

Here, the complex waveform shaping filter circuit 91
4, 915, and 916 are shown in FIGS. 11, 12, 13, and 1.
Any of the configurations of 4 may be used. The coherent timing error detection circuits 923, 924, 925 have the same configurations as those shown in FIG. 15, and correlators 917, 918,
The configuration of 919 is the same as that shown in FIG.

Next, the operation of the fourth embodiment will be described. First, the signals received from the receiving antenna 900 are the mixers 902, 903, the π / 2 phase shifter 904,
The quasi-synchronous detection circuit 901 composed of the local oscillator for quasi-synchronous detection quasi-coherently detects the I-component and the Q-component of the baseband signal, and the respective AD converters 9
Sampled by 06 and 907 and converted into digital data RI and RQ. Here, the circuits after the AD converters 906 and 907 are all free-running clocks whose frequency is about 1 to 4 times the chip frequency of the received signal and whose phase is asynchronous with the chip phase of the received signal. Work according to. Therefore, the AD converters 906 and 907
As shown in FIG. 9F, the input data of is sampled with deviation from the ideal timing, and becomes RI and RQ. Complex complex waveform shaping filter circuits 914, 915, 9
As shown in FIG. 9G, the tap coefficient of the demodulation tap coefficient variable complex waveform shaping filter in 16 is such that the maximum output is obtained when the signals RI and RQ whose dumping timings are shifted are input. Is set to. This timing error is calculated by coherent timing error detection circuits 923, 924, and 925 described later. Although the timing of the path to be demodulated differs by several chips, the number of stages variable shift registers 908-9
By 13 to eliminate this timing difference,
For precise timing adjustment, the complex waveform shaping filter circuit 9
14, 915, 916.

Complex waveform shaping filter circuits 914 and 91
The outputs of Nos. 5 and 916 are multiplied by the spread code inside the correlators 917, 918 and 919, and integrated for one symbol period to become correlator outputs XI and XQ. Adders 920, 9
21 is an output XI having the number of paths to be RAKE-combined,
XQ is synthesized separately for I and Q. The sign determiner 922 determines whether the outputs of the adders 920 and 921 are positive or negative,
The code determination outputs SI and SQ are given. Where XI, X
Q, SI, and SQ are signals of 1 sample per 1 symbol.

Next, the operation of the coherent timing error detection circuits 923, 924, 925 will be described with reference to FIG. Early spreading code generator 7 in coherent timing error detection circuit 923, 924, 925
02 and Late spreading code generator 707 generate the same spreading code as that generated by spreading code generator 401 in correlators 917, 918, and 919 for demodulation. When the configuration of FIG. 11 is used for the complex waveform shaping filter circuits 914, 915, and 916, the timing of the spreading code generated by the Early spreading code generator 702 is set to the demodulation correlator 917,
The timing of the spreading code generated by the spread code generator 707 in 918, 919 is set earlier than the timing of the spreading code generated by the spread code generator 401 by a certain time δ, and the timing of the spreading code generated by the Late spread code generator 707 is set to The timing of the spreading code generated by the spreading code generator 401 in 918 and 919 is delayed by a certain time δ. When the configuration of FIG. 12 or 13 is used for the complex waveform shaping filter circuits 914, 915, 916, the Early spreading code generator 7 is used.
02 and the timing of the spread code generated by the Late spread code generator 707 are set by the correlators 917, 918, 9 for demodulation.
The timing of the spreading code generated by the spreading code generator 401 in 19 is the same.

With the above settings, when the sampling timing of the AD converters 906 and 907 is later than the ideal sampling timing, the amplitude of the output of the Early branch correlator 700 becomes large and the AD converter 906,
When the sampling timing of 907 is earlier than the ideal sampling timing, the amplitude of the output of the Late branch correlator 701 becomes large. Next, the Early Branch Correlator 700 and
The output power of the Late branch correlator 701 is calculated by the Early branch power measuring device 712 and the Late branch power measuring device 713,
The subtracter 721 calculates the difference and outputs the outputs Err of the coherent timing error detection circuits 923, 924, and 925.
Get.

Early branch power measuring instrument 7 in timing error detection circuit 826, 827, 828 shown in the third embodiment.
12 and the Late branch power measuring device 713 use a squarer as a means for collecting the phases of the input signals in a fixed direction for power measurement. However, since the squared operation deteriorates the signal-to-noise ratio, the timing error Detection circuits 826, 827,
The performance of the 828 is relatively poor. On the other hand, the coherent timing error detection circuits 923, 924, 925
The early branch power measuring device 712 and the late branch power measuring device 713 are provided with multipliers 714, 715, 718, and 719 for performing multiplication with the code determination output instead of the squarer. Complex waveform shaping filter circuits 914, 915, 9
The 16 outputs EI, LI, EQ, and LQ have already been phase-compensated, and by multiplying the output of the code decision unit 922, the Early branch power measuring unit 712 and Late
The phase of the output signal of the branch power measuring device 713 can be aligned in a fixed direction. Also, since the square operation is not used,
It has good characteristics without deterioration of signal-to-noise ratio. With the above configuration, when the sampling timing of the AD converters 906 and 907 is later than the ideal sampling,
When Err has a negative value and the sampling timing of the AD converters 906 and 907 is earlier than the ideal sampling, Err has a positive value.

Next, the complex waveform shaping filter circuit 914,
A method of setting tap coefficients of the complex waveform shaping filter in 915 and 916 will be described. The received signal that has been quasi-coherently detected and converted into a baseband signal is generated by arranging and adding the root Nyquist single pulses shown in FIG. 8A at chip cycle Tc intervals as shown in FIG. 8B. 8
It becomes something like (c). When this received signal is sampled by the AD converters 906 and 907 at the timing as shown in FIG. 9D (this sampling timing is ideal), this received signal is most efficiently taken into the digital circuit. , It is necessary to pass a complex waveform shaping filter having a tap coefficient sequence as shown in FIG. Further, when the received signal is sampled at a timing deviated from the ideal timing by d as shown in FIG. 9F, in order to capture the received signal into the digital circuit most efficiently, the signal shown in FIG. It is necessary to pass a complex waveform shaping filter having such a tap coefficient sequence. The timing error d is calculated by the coherent timing error detection circuits 923, 924, 925 and is given to the complex waveform shaping filter tap coefficient calculators 926, 927, 928 in the form of the error signal Err. Complex waveform shaping filter tap coefficient calculators 926, 927,
928 first calculates the tap coefficient calculated based on the error signal Err. Next, the phase due to the quasi-coherent detection of the correlator outputs XI and XQ is detected, the phase compensation complex coefficient that cancels the detected phase error is calculated, and the above tap coefficient is multiplied to obtain the complex tap coefficient. Ask. Then, the calculated complex tap coefficient is applied to the complex waveform shaping filter circuit 91.
4,915,916.

Here, the complex waveform shaping filter circuit 91
4, 915 and 916 have the complex waveform shaping filter circuits 914 and 91 when they have the configuration of FIG. 11 or 12.
The same complex tap coefficient is given to all the complex tap coefficient variable complex waveform shaping filters in 5, 916. When the complex waveform shaping filter circuits 914, 915, and 916 have the configuration shown in FIG. 13, the complex waveform shaping filter circuit 914,
Among all the complex tap coefficient variable complex waveform shaping filters in 915 and 916508, the Early filter 607 is given a complex tap coefficient of δ earlier than the complex tap coefficient given to the Demod filter 609, and the Late filter is used. The complex tap coefficient 608 is delayed by δ from the complex tap coefficient given to the demod filter 609.

As described above, according to the fourth embodiment,
Since the system clock for operating all digital circuits including the AD converter is a free-running clock that is asynchronous with the received signal, the voltage-controlled clock oscillator and the DA converter that generates the control voltage for the system are unnecessary. The number of analog elements in the device can be reduced. Further, the signals of all paths are sampled at the optimum sampling timing without increasing the sampling frequency of the AD converter in the main path tracking method or providing an independent system clock for each path in the independent tracking method. A value can be obtained, and high communication quality can be maintained without increasing current consumption or hardware scale. Furthermore, since phase compensation is performed before the correlator, it is not necessary to use a squarer in the timing error detection circuit, and the characteristics of the timing error detection circuit are improved. Furthermore, since the phase compensation circuit before the code determiner is unnecessary, the hardware scale can be reduced.

[0055]

According to the present invention, as is clear from the above embodiment, the system clock for operating all the digital circuits including the AD converter is sufficient to be a free-running clock asynchronous with the received signal. The voltage-controlled clock oscillator and the DA converter that generates the control voltage for the voltage-controlled clock oscillator are not required, and the number of analog elements in the device can be reduced. Further, the signals of all paths are sampled at the optimum sampling timing without increasing the sampling frequency of the AD converter in the main path tracking method or providing an independent system clock for each path in the independent tracking method. A value can be obtained, and high communication quality can be maintained without increasing current consumption or hardware scale.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a spread spectrum receiver according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a waveform shaping filter circuit according to the first and third embodiments of the present invention.

FIG. 3 is a block diagram showing another configuration of the waveform shaping filter circuit according to the first and third embodiments of the present invention.

FIG. 4 is a block diagram showing still another configuration of the waveform shaping filter circuit according to the first and third embodiments of the present invention.

FIG. 5 is a block diagram showing still another configuration of the waveform shaping filter circuit according to the first and third embodiments of the present invention.

FIG. 6 is a block diagram showing a configuration of a timing error detection circuit according to the first and third embodiments of the present invention.

FIG. 7 is a block diagram showing the configuration of a correlator according to each embodiment of the present invention.

8A is a waveform diagram of a root Nyquist single pulse in each embodiment of the present invention. FIG. 8B is a waveform diagram in which root Nyquist single pulses in FIG. 8A are arranged at intervals of a chip period Tc. Waveform diagram of the received baseband signal with the waveform of b) added

(D) Waveform diagram of root Nyquist single pulse sampled at ideal timing (e) Tap coefficient of waveform shaping filter matching the waveform of root Nyquist single pulse sampled at ideal timing (F) Waveform diagram of root Nyquist single pulse sampled at timing with error (g) Tap coefficient of waveform shaping filter matching the waveform of root Nyquist single pulse sampled at timing with error Characteristic diagram showing

FIG. 10 is a block diagram showing a configuration of a spread spectrum receiver according to a second embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a complex waveform shaping filter circuit according to the second and fourth embodiments of the present invention.

FIG. 12 is a block diagram showing another configuration of the complex waveform shaping filter circuit according to the second and fourth embodiments of the present invention.

FIG. 13 is a block diagram showing still another configuration of the complex waveform shaping filter circuit according to the second and fourth embodiments of the present invention.

FIG. 14 is a block diagram showing still another configuration of the complex waveform shaping filter circuit according to the second and fourth embodiments of the present invention.

FIG. 15 is a block diagram showing the configuration of a coherent timing error detection circuit according to the second and fourth embodiments of the present invention.

FIG. 16 is a block diagram showing a configuration of a spread spectrum receiver according to a third embodiment of the present invention.

FIG. 17 is a block diagram showing a configuration of a spread spectrum receiver according to a fourth embodiment of the present invention.

FIG. 18 is a block diagram showing a configuration of a spread spectrum receiver in a conventional example.

FIG. 19 is a block diagram showing another configuration of the spread spectrum receiver in the conventional example.

FIG. 20 is a block diagram showing still another configuration of the spread spectrum receiver in the conventional example.

[Explanation of symbols]

101, 501, 801, 901 Quasi-synchronous detection circuit 106, 107, 506, 507, 806, 807, 9
06, 907 AD converter 108, 814, 815, 816 Waveform shaping filter circuit 508, 914, 915, 916 Complex waveform shaping filter circuit 109, 509, 817, 818, 819, 917, 9
18, 919 Correlator 110, 820, 821, 822 Phase compensation circuit 111, 511, 825, 922 Code decision device 112, 826, 827, 828 Timing error detection circuit 510, 923, 924, 925 Coherent timing error detection circuit 113 , 829, 830, 831 Waveform shaping filter tap coefficient calculator 512, 926, 927, 928 Complex waveform shaping filter tap coefficient calculator 808, 809, 810, 811, 812, 813, 9
08, 909, 910, 911, 912, 913 Shift registers 823, 824, 920, 921 Adder

Claims (4)

[Claims] 1. A quasi-synchronous detection circuit for converting a received spread spectrum signal into a two-system baseband signal of I and Q by multiplying a local oscillation signal having a frequency substantially equal to its carrier frequency, and the quasi-synchronous detection circuit. An analog-to-digital converter that samples the output signal of the detection circuit with a fixed sampling clock whose frequency is approximately equal to several times the chip frequency of the received spread spectrum signal, and the analog-digital converter that is driven by the fixed sampling clock.
A waveform shaping filter circuit using a variable tap coefficient digital FIR filter for shaping the output of the digital converter, and a demodulation spread code generator for demodulating a received spread spectrum signal with the output of the waveform shaping filter circuit as an input. Correlator for demodulation, which comprises a multiplier, a digital multiplier, and an adder, and a phase error generated at the time of quasi-coherent detection for determining the sign of the output signal of the demodulator correlator. A phase compensation circuit that estimates by observing the output signal of the correlator and compensates the error component of the output signal of the demodulation correlator, and the positive and negative of the output of the phase compensation circuit as I component and Q component. A code determiner that individually determines with, a timing error detection circuit that measures the timing error of the received spread spectrum signal and the demodulated spread code,
Based on the timing error signal received from the timing error detection circuit, the tap coefficient that most efficiently acquires the energy of the received spread spectrum signal is calculated, and the tap coefficient of the variable tap shaping filter circuit is used. And a spread spectrum receiver for updating a waveform shaping filter tap coefficient calculator. 2. A demodulation correlator that is generated at the time of quasi-coherent detection instead of a phase compensation circuit in the latter stage of the demodulation correlator and is used instead of the waveform shaping filter tap coefficient calculator and the variable tap coefficient waveform shaping filter circuit. A complex waveform shaping filter tap coefficient calculator that estimates the output phase error and multiplies the signal for compensating the phase error by the tap coefficient specified for the variable tap coefficient waveform shaping filter circuit,
The spread spectrum receiver according to claim 1, further comprising: a variable complex tap coefficient type waveform shaping filter circuit whose characteristic is determined by a complex tap coefficient given from the complex waveform shaping filter tap coefficient calculator. 3. A quasi-synchronous detection circuit for converting a received spread spectrum signal into a baseband signal of two systems of I and Q by multiplying a local oscillation signal having a frequency substantially equal to its carrier frequency, and the quasi-synchronous detection circuit. An analog digital converter for sampling the output signal of the detection circuit with a fixed sampling clock whose frequency is approximately equal to several times the chip frequency of the received spread spectrum signal, and the analog digital converter driven by the fixed sampling clock.
A set of variable-stage shift registers for preliminarily removing the timing difference of the path to be demodulated by inputting the output of the digital converter, and the fixed sampling clock drive the waveform of the shift register output. A waveform shaping filter circuit using a variable tap coefficient type digital FIR filter, a demodulation correlator for demodulating a received spread spectrum signal with the output of the waveform shaping filter circuit as an input, and an output of the demodulation correlator In order to determine whether the signal is positive or negative, the phase error generated at the time of quasi-coherent detection is estimated by observing the output signal of the demodulation correlator, and the error is relative to the output signal of the demodulation correlator. Phase compensation circuit for compensating for the component, and the phase-compensated demodulation correlator outputs of all paths to be RAKE-combined separately for the I component and the Q component. An adder for calculation, and individually determining the code decision unit at the sign of the addition result as I and Q components,
A timing error detection circuit that measures the timing error between the received spread spectrum signal and the demodulated spread code, and the most efficient way to obtain the energy of the received spread spectrum signal based on the timing error signal received from the timing error detection circuit. And a waveform shaping filter tap coefficient calculator for calculating the tap coefficient to update the tap coefficient of the variable tap shaping filter circuit, the shift register set, the waveform shaping filter circuit, and the demodulation correlator. A spread spectrum receiver with a RAKE function, which is provided with a phase compensation circuit, a timing error detection circuit, and a waveform shaping filter tap coefficient calculator as many as the number of paths to be RAKE combined. 4. A demodulation correlator that is generated at the time of quasi-coherent detection, instead of a phase compensation circuit in the subsequent stage of the demodulation correlator, instead of the waveform shaping filter tap coefficient calculator and the variable tap coefficient waveform shaping filter circuit. A complex waveform shaping filter tap coefficient calculator that estimates the output phase error and multiplies the signal for compensating the phase error by the tap coefficient specified for the variable tap coefficient waveform shaping filter circuit,
The spread spectrum receiver according to claim 3, further comprising: a variable complex tap coefficient type waveform shaping filter circuit whose characteristic is determined by a complex tap coefficient given from the complex waveform shaping filter tap coefficient calculator.