JPH09312094A - Refresh control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To curtail hardware by the composition that the memory area control means and the refresh control means are controlled by software. SOLUTION: When a memory access address is inputted from a CPU 20 into a memory area control register 2, the register 2 makes the data bit effective which corresponds to the memory area including the access address in accordance with the program. At the same time, the access address is inputted also to a refresh control register 3, which makes the data bit corresponding to the memory area including the access address in accordance with the program regrettable. A memory manager 4 reads out the contents of the register 2 and the register 3 to output the control signal for refreshing the memory area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refresh control system, and more particularly to a refresh control system for a dynamic random access memory (hereinafter referred to as DRAM).

[0002]

2. Description of the Related Art In a DRAM, the electric charge stored in a capacitor decays with time, and therefore it is necessary to regenerate (refresh) at regular intervals. Therefore, DRAM
Is provided with a refresh control circuit.

However, if the entire area of the memory is constantly refreshed, current consumption will increase.

Therefore, Japanese Patent Laid-Open No. 3-66092 discloses a technique for refreshing only a memory area that has been accessed.

FIG. 5 is a block diagram of a conventional refresh control system (Japanese Patent Laid-Open No. 3-66092).

In the figure, an address decoder 51,
The RAS timing control unit 52 including the data holding units F0 to Fn is used for the plurality of memory areas M0 to Mn of the DRAM.
Refresh control.

By decoding an address signal of an arbitrary bit number j by the address decoder 51, a plurality of decode signals AM0 to AM corresponding to the memory areas M0 to Mn are obtained.
n to generate the signals AM0 to AMn and hold them in the data holding means F.
0 to Fn, and in synchronization with the refresh timing signal φ synchronized with the refresh cycle, each of the signals AM0 to AMn is RAS (Row Address).
Strobe) signals RAS0 to RASn are supplied to the memory areas M0 to Mn.

By supplying a refresh address signal having an arbitrary number of bits in synchronization with the cycle of the refresh operation, the refresh operation is performed in cooperation with the RAS signals RAS0 to RASn.

Then, the decode signal of the memory-accessed memory area is held as a true value in the data holding means corresponding to this memory area, so that only the memory area related to the actual processing is refreshed. Is configured.

[0010]

However, in the conventional refresh control system, since the RAS timing control unit is composed of hardware, each of the memory areas M0 to Mn.
In order to generate the decode signals AM0 to AMn that correspond to each other on a one-to-one basis, the decode unit (address decoder 51)
However, there was a problem that the external circuit scale of would become very large.

Further, if the circuit structure of the decoding unit is simplified (for example, the number of bits of the address to be decoded is reduced), when the CPU (central processing unit) accesses an area outside the memory area, it is completely Since it cannot be decoded, even if you do not access the memory area,
Decode signals AM0 to AMn may be generated, and in this case, there is also a problem that the refresh operation cannot be completely stopped.

On the contrary, this hardware decoder has a structure capable of refreshing only the accessed memory area, and enables or stops the refreshing operation on any memory area which is not accessed. There was a problem that I could not do it.

Therefore, an object of the present invention is to provide a refresh control system capable of reducing the circuit scale and enabling / disabling an arbitrary access area.

[0014]

In order to solve the above-mentioned problems, the present invention is a refresh control system for a dynamic memory cell, in which each of a plurality of memory areas is enabled or disabled according to a memory access address. Area control means, refresh control means for enabling or disabling each of a plurality of memory areas, and refresh execution means for executing refresh of dynamic memory cells based on control results of the memory area control means and refresh control means. It is characterized by consisting of.

[0015]

According to the present invention, when a memory access address is input from the CPU, the memory area control means validates the memory area including the memory access address. Further, the refresh control means makes the memory area including the memory access address refreshable. The refresh execution means executes the refresh of the memory area based on the control results of the memory area control means and the refresh control means.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of an example of a refresh control system according to the present invention. The same components as those in the conventional example are designated by the same reference numerals, and the description thereof will be omitted.

The refresh control system 1 comprises a memory area control register 2, a refresh control register 3 and a memory manager 4.

A memory access address from the CPU 20 is input to the memory area control register 2 and the refresh control register 3, and a signal output from the memory manager 4 causes the memory areas M0 to Mn (n is a positive integer) of the DRAM to be changed. Be refreshed.

The memory area control register 2 enables or disables each of the memory areas M0 to Mn. The refresh control register 3 enables (refreshable) or invalid (unrefreshable) the refresh function of each of the memory areas M0 to Mn.

The memory manager 4 also monitors these registers 2 and 3 and controls the DRAM control signals RAS0-RAS0.
RASn, CAS (Column Address St
robe), WE (write signal), etc. are generated.

The bits of the memory area control register 2 and the refresh control register 3 are controlled by software.

That is, the memory area control register 2
When the data bit corresponding to the memory area Mi of is validated (represented by Mi1), the memory area Mi becomes a valid memory area. On the other hand, when the data bit corresponding to the memory area Mi is invalidated (represented by Mi0), the memory area Mi becomes an invalid memory area (image area).

The data bit corresponding to the memory area Mi of the refresh control register 3 is validated (R
(Represented by EFi1) and the refresh function of the memory area Mi are enabled. On the other hand, when the data bit corresponding to the memory area Mi is invalidated (represented by REFi0), the refresh function of the memory area Mi is invalidated.

When the memory manager 4 reads the memory area control register 2 and recognizes Mi1 indicating that it is a valid memory area, it controls the memory access control signal corresponding to the memory area Mi.

When the memory manager 4 reads the refresh control register 3 and recognizes REFi1 indicating that the refresh is a valid memory area, it controls the refresh control signal corresponding to the memory area Mi.

Next, the operation will be described. First, the first operation of refreshing only the memory area Mi including the memory access address will be described. FIG. 2 shows the first
6 is a flowchart showing the operation of the first embodiment.

When the memory access address is input to the memory area control register 2 from the CPU 20, only the data bit corresponding to the memory area Mi of the memory area control register 2 is validated (S1). All the bits corresponding to the memory area in which the memory is not accessed are invalidated.

Next, only the data bit corresponding to the memory area Mi of the refresh control register 3 is validated (S2). All the bits corresponding to the memory area in which the memory is not accessed are invalidated.

When the writing to these registers 2 and 3 is completed, the memory manager 4 reads the contents of the memory area control register 2 (S3).

Then, the memory manager 4 confirms the existence of a valid memory area (S4).

Since only the memory area Mi is valid now,
The memory manager 4 validates the control signal (RASi, CAS, WE, etc.) corresponding to the valid memory area Mi according to the memory write, read timing, etc. (S
5). As a result, the memory area Mi becomes valid.

On the other hand, since the memory areas other than the memory area Mi are invalid in S4, the memory manager 4 causes the memory manager 4 to control signals (RASi, CAS, WE) corresponding to the invalid memory areas.
Etc.) are all invalidated (S6). As a result, the memory areas other than the memory area Mi become invalid.

Next, the memory manager 4 reads the contents of the refresh control register 3 (S7).

The memory manager 4 confirms the existence of a memory area in which refresh is effective (S8).

Since the refresh is valid only in the memory area Mi, the memory manager 4 controls the control signal (RASi,
(CAS, WE, etc.) are enabled according to the refresh timing and refresh method (S9). As a result, refresh becomes effective in the memory area Mi.

On the other hand, in S8, memory areas other than the memory area Mi have invalid refresh, so the memory manager 4 always invalidates all the control signals (RASi, CAS, WE, etc.) corresponding to the invalid refresh memory areas. Yes (S10). As a result, refresh becomes invalid in the memory areas other than the memory area Mi.

As a result, only the memory area Mi is refreshed.

Next, access to the valid memory area Mi is started (S11), and the operation ends.

Although the processing in the memory area control register 2 is performed before the processing in the refresh control register 3 in this embodiment, the order may be reversed.

Next, the accessed memory area Mi
A second operation for invalidating only refresh will be described. FIG. 3 is a flowchart showing the second operation.

First, at the end of access to the memory area Mi,
Immediately before a program entering another process, the data bit corresponding to the memory area Mi of the memory area control register 2 is invalidated (S21).

Next, the data bit corresponding to the memory area Mi of the refresh control register 3 is invalidated (S22). For other memory areas, the data bits of the memory area control register 2 and the refresh control register 3 are not changed.

When the writing to these registers 2 and 3 is completed, the memory manager 4 reads the contents of the memory area control register 2 (S23).

Next, the memory manager 4 sets the memory area M
It is recognized that the data bit corresponding to i is invalid (S24).

Then, the memory manager 4 sends control signals (RASi, CAS, WE, etc.) corresponding to the memory area Mi.
Is always invalidated (S25). As a result, the memory area of the memory area Mi becomes invalid.

Next, the memory manager 4 reads the contents of the refresh control register 3 (S26).

Next, the memory manager 4 sets the memory area M
It is recognized that the data bit corresponding to i is invalid (S27).

Then, the memory manager 4 causes the refresh control signals (RASi, CA) corresponding to the memory area Mi.
S, WE, etc.) are always disabled (S28).

As a result, the memory area Mi is not refreshed.

At this time, with respect to the memory areas other than the memory area Mi, since the data bits of the memory area control register 2 and the refresh control register 3 are not changed, the state does not change.

With this, access to the memory area Mi ends (S29), access to another process starts next (S30), and the operation ends.

In the second operation, the order of the processing in the memory area control register 2 and the processing in the refresh control register 3 may be reversed, as in the case of the first operation.

Next, both the memory area containing the accessed address and the memory area containing the previously accessed address can be refreshed.
The operation of will be described. FIG. 4 is a flowchart showing the third operation.

First, by the operation similar to the first operation, refresh is enabled only in the memory area Mj (which is the memory area accessed immediately before) (S41).

Next, access to the memory area Mj is started (S42), and when the access is completed (S4).
3) Access to another process is started (S4)
4).

However, in S44, the operation such as the second operation is not performed on the memory area control register 2 and the memory area Mj of the refresh control register 3 immediately before entering another process. That is, the memory area Mj keeps the refresh valid.

Next, the other process ends (S45),
The next memory access is made.

The memory area containing the next memory access address is called a memory area Mi.

First, the data bits corresponding to the memory area Mi of the memory area control register 2 and the refresh control register 3 are enabled (S4).
6).

Next, the memory manager 4 reads the contents of the memory area control register 2 and the refresh control register 3 (S7).

The memory manager 4 confirms the existence of a valid memory area. Since the memory areas Mj and Mi are valid now, the memory manager 4 determines that the valid memory area M
Control signals (RASi, CAS, WE) corresponding to j and Mi
Etc.) is enabled according to the memory write, read timing, etc. (S48). As a result, the memory areas Mj, M
i is valid.

Next, the memory manager 4 confirms the existence of a memory area in which refresh is effective. Since the refresh is valid in the memory areas Mj and Mi, the memory manager 4 determines that the refresh is effective in the memory areas Mj and Mi.
Control signal corresponding to Mi (RASi, CAS, WE, etc.)
Are enabled according to the refresh timing and refresh method (S49). As a result, the memory area M
Refresh is valid for j and Mi.

Next, access to the valid memory area Mi is started (S50). In this case, since the refresh of the memory area Mj is enabled, the memory area Mj
The data in can be used.

It should be noted that the CPU 20 has finished accessing the memory area Mj and cannot access another process.
It is also possible to access the memory area Mi immediately.

In this case, immediately after accessing the memory area Mi, the operation like the second operation is not performed on the memory area control register 2 and the memory area Mj of the refresh control register 3. That is, the memory area Mj keeps the refresh valid.

[0066]

According to the present invention, the memory area control means for enabling or disabling each of the plurality of memory areas according to the memory access address, and the refresh control for enabling or disabling each of the plurality of memory areas. Means and
The memory area control means and the refresh control means are provided with a refresh execution means for executing the refresh of the dynamic memory cell based on the control results, and the memory area control means and the refresh control means are configured to be controlled by software. Wear can be reduced. Therefore, the circuit scale can be reduced.

Further, since it is possible to make any access area refreshable or not refreshable, it is possible to completely stop the refresh operation for a memory area that does not need to be refreshed, and to access any access area. It is possible to enable or stop the refresh operation for a memory area that has not been opened.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of a refresh control system according to the present invention.

FIG. 2 is a flowchart showing a first operation.

FIG. 3 is a flowchart showing a second operation.

FIG. 4 is a flowchart showing a third operation.

FIG. 5: Conventional refresh control system
66092).

[Explanation of symbols]

 1 refresh control system 2 memory area control register 3 refresh control register 4 memory manager

Claims (4)

[Claims] 1. A refresh control system for a dynamic memory cell, comprising: memory area control means for enabling or disabling each of a plurality of memory areas according to a memory access address; and refreshing each of the plurality of memory areas. A refresh control system comprising: a refresh control means for disabling and a refresh execution means for refreshing a dynamic memory cell based on a control result by the memory area control means and the refresh control means. 2. The memory area control means validates a memory area including the memory access address according to a program, and the refresh control means makes the memory area including the memory access address refreshable according to a program, and the refresh. 2. The execution means executes the refresh of the memory area based on the control result of these control means.
The described refresh control system. 3. The memory area control means invalidates a memory area including an address whose memory access has ended according to a program, and the refresh control means refreshes a memory area including an address whose memory access has ended according to a program. 2. The refresh control system according to claim 1, wherein the refresh execution means prohibits refreshing of the memory area based on a control result of the control means. 4. The memory area control means validates both a memory area including the memory accessed address and a memory area including the immediately previous accessed address according to a program, and the refresh control means Both the memory area including the memory access address and the memory area including the previously accessed address are refreshable according to a program,
2. The refresh control system according to claim 1, wherein the refresh execution means executes refresh of both memory areas based on the control results of these control means.