JPH09311833A - Communication controller and communication system using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a small-scale circuit to easily deal with a system bus width larger than the bus width of a communication controller main body by controlling the DMA(direct memory access) transfer and also generating a signal to show that plural data are continuous. SOLUTION: The DMA transfer of plural data are performed between external devices such as a CPU 53, a memory 54, etc., via an external data bus 50. This DMA transfer is controlled by a DMAC control circuit 30 of a communication controller 1. The circuit 30 produces a signal to show that plural data are continuous. Therefore, the alignment of data is controlled by the circuit 30 and the fast transfer of data is attained. Furthermore, plural data can be turned into a single piece of data by such a simple alignment circuit 48 as a buffer circuit, etc.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a communication control device and a communication system used in the field of data communication.

[0002]

2. Description of the Related Art Conventionally, in a high-speed communication control device of several tens of Mbps to 500 Mbps, it is necessary to improve the throughput of transmitted / received data, and a data bus width of a microprocessor (hereinafter abbreviated as CPU) has been widened. . Usually, the bus width of the communication control device has been expanded by the following method in order to cope with a large bus width. As an example, a communication control device with a 16-bit data bus width is a 32-bit CP.
A communication system that performs DMA (Direct Memory Access) transfer corresponding to U will be described.

FIG. 5 shows an example of the configuration of a conventional communication system.

55 is a transmitter, a receiver, a transmission FIFO,
It is a communication control device main body incorporating a reception FIFO and a DMA controller. The communication control device is usually installed in a data processing device, and is a semiconductor integrated circuit device (L) for communicating between a plurality of data processing devices.
SI). Reference numerals 58 and 62 denote latch registers, which hold addresses of data to be transferred.
Reference numeral 60 denotes a comparison calculator, which compares the addresses held by 58 and 62.

Reference numeral 63 is a buffer, which is used for temporarily holding the data to be transferred.

70 and 71 are 32-bit CPUs,
The external memories, 56 and 57 are the communication control device 55, respectively.
Address bus, data bus, 65, 66, 67, 6
Reference numerals 8 and 69 are external buses.

Next, the operation of the communication system will be described with reference to FIG.
This will be described with reference to FIG. FIG. 6 is a time chart of address signals and data bus signals. For convenience, the width of the data bus 57 is 16 bits and the width of the external buses 65 to 69 is 32 bits.

When performing DMA transfer of data having a data bus width of 16 bits between the external memory 71 and the communication control device via the 32-bit external bus 67, the current data is transferred to the latch register 58 in the first cycle of the DMA transfer. The target address ADR1 is set to the address bus 56 of the communication control unit.
Hold more. The lower data DAT1 is held in the buffer 63 via the data bus 57.

In the second DMA transfer cycle, the next address ADR2 is held in the latch register 62 from the address bus 56 of the communication controller. Further, the upper data DAT2 is held in the buffer 63 through the data bus 57 of the communication control device. After the value of the latch register 63 is determined, the comparison calculator 60 determines whether ADR1 and ADR2 are continuous. If the addresses are continuous, a match signal is output from the signal line 64 to the buffer 63. The buffer 63 outputs the data DAT3, which is 32-bit data composed of the data DAT1 and DAT2, to the external bus 66, and transfers the data with the external memory 71.

As described above, in the conventional communication system, in addition to the main body of the communication control device, a circuit for determining whether or not addresses for data transfer are continuous is required, so that the scale of the entire system becomes large.

[0011]

SUMMARY OF THE INVENTION An object of the present invention is to realize a communication control device and a communication system which can easily cope with a system bus width larger than the bus width of the communication control device main body with a small scale circuit.

Another object of the present invention is to realize high-speed data transfer in the above bus expansion configuration.

[0013]

A communication control apparatus according to the present invention transfers a plurality of data to and from an external device such as a CPU or a memory via an external data bus.
y Access) Transfer. The DMA transfer is controlled by the DMA controller in the communication control device. Furthermore, DM
The A controller generates a signal indicating that the plurality of data are continuous data.

In the communication system according to the present invention, the external device is connected to the external data bus, and the communication control device is connected via the data alignment circuit. The marshaling circuit receives a plurality of data and the signal from the communication control device, marshals the plurality of data into a single data according to the input of the signal, and outputs the marshaled data to the external data bus.

According to the present invention, the DMA in the communication control unit
Since data alignment is controlled by the controller, high-speed data transfer is possible, and a plurality of data can be made into a single data by a simple alignment circuit such as a buffer circuit.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described.

The configuration of the communication system and the configuration of the communication control device according to the first embodiment of the present invention will be described with reference to FIG.

Reference numeral 1 denotes a communication control device, which may be composed of a plurality of parts, or one or a plurality of LSIs. Reference numerals 6 and 8 denote transmitters, which are transmission FIFOs 14,
The parallel transmission data input from 16 is converted to serial and transmitted as transmission data 2 and 4.

Numerals 7 and 9 are receivers, which receive the serial reception data 3 and 5 and convert them into parallel data, and then store them in the reception FIFOs 15 and 17.

In the present embodiment, two transmitters and two receivers are drawn, and two serial channels are drawn.
The present invention does not limit the number of serial channels, and of course does not particularly limit the number of transmitters and receivers.

In the present embodiment, the transmitter and the receiver can be processed by a plurality of protocols such as a bit synchronization protocol, a byte synchronization protocol, and an asynchronous communication protocol, but different combinations of these may be used.
Ethernet, frame relay, ATM, ISDN, and other protocols may be used alone or in combination to enable processing.

26 to 29 are DMAC (Direct Memoyr Ac
cess controler) channel, which is given the bus right by the bus arbitration circuit 40, and the transmission FIFOs 14 and 16 and the reception FIFO1.
Data is transferred between 5, 17 and the internal data bus 39, the bus interface 43 is controlled, and C is transferred via the external data buses 50, 51, 52 and the alignment circuit 48.
Data transfer is performed between the PU 53 and the external memory 54.

In this embodiment, signal lines for four DMAC channels are drawn, but the present invention does not limit the number of DMAC channels.

When the bus acknowledge signal 41 is returned from the external bus master, the bus arbitration circuit 40 activates any one of the channel selection signal lines 31 to 34 to connect the bus to any one of the connected DMAC channels 26 to 29. Give the right.

The bus arbitration method may be a rotation priority method in which the bus right is sequentially given to each channel, a fixed priority method in which the bus right is preferentially given to a specific channel, or a bus right is given randomly. However, the present invention does not limit the priority determination method. The bus master may be provided outside the communication control device or, of course, may be built in the communication control device. Further, the number of bus masters may be one or plural.

In this embodiment, the external memory 54 and the CPU 53 are connected to the end of the external bus 44, but in the present invention, either or both of the bus master and the peripheral device may be connected to the external bus.

The configurations of the DMAC channels 26 to 29 and the DMAC control circuit 30 shown in FIG. 1 will be described in detail with reference to FIG.

Reference numerals 14 and 16 are transmission FIFOs, and 15,
Reference numeral 17 is a reception FIFO.

Reference numerals 72 to 75 denote BURST generation circuits, which are B
Output the URST signal.

76 to 79 are DMAC channels 2 respectively
6-29 is one of the built-in registers, DM
A: The number of data words to be transferred is set and held, and decremented by one each time one word is transferred.

80 to 83 are DMAC channels 2 respectively
6 to 29, which is one of the registers incorporated therein, holds the address of the memory where the DMAC channel to which the bus right is given by the bus arbitration circuit 40 first starts the DMA data transfer.

Reference numeral 84 denotes an address generation circuit, which takes in address data of a register which holds an address of a memory which starts data transfer at the beginning of a DMAC channel to which the bus right is given by the bus arbitration circuit 40, and outputs consecutive addresses. To generate. Further, the buffer control signal line 46 outputs a signal for controlling whether the data held in the marshaling circuit 48 is upper data or lower data.

Reference numeral 85 denotes a BURST control circuit, which outputs a BURST signal output from a DMAC channel given a bus right from the bus arbitration circuit 40 through a signal line 45.

The alignment circuit 4 shown in FIG. 1 will be described with reference to FIG.
8 will be described.

This is a circuit for aligning two consecutive data into a single data.

Reference numeral 45 is a BURST signal line, 46 is a buffer control signal line, 47 is a local data bus of the communication control device, and 49 is an external bus.

Reference numerals 86 and 87 are buffers, and BURST
Data is held or passed through depending on the states of the signal line 45 and the buffer control signal line 46.

The operation of this embodiment will be described with reference to FIG.

With respect to the internal bus width of N bits, the width of the system bus to which continuous data is DMA data transferred is 2N.
The case of a bit will be described. FIG. 4 is a time chart showing the operation. For convenience, the bus right given by the bus arbitration circuit 40 is the DMAC channel 27.
Have been given to.

In the first cycle of the DMA transfer, the BURST generating circuit 74 has the number of remaining data transfer words of the data word number setting register 78 of 2N / 8 (8 is the number of bits of the DMAC transfer unit).
If there is a word count and the number of remaining data of the reception FIFO 15 output from the signal line 23 is 2N / 8, it is judged that the data to be transferred by the DMA data is continuous, and B is shown to the outside.
BURST the URST signal through the BURST control circuit 85
The BURST signal is output to the outside through the ST signal line 45. The BURST signal is input to the alignment circuit 48 and the BURST signal is input.
While the ST signal is asserted, the buffer control signal passing through the buffer control signal line 46 controls the head data of a plurality of continuous data to be held in the buffer 86, and the local data bus 47 of the communication control device 1 is controlled. The data DAT1 is held in the buffer 86 via the data. Also,
The address held in the register 82 is input to the address generation circuit 84 to generate the address of the external memory for DMA data transfer. Then, in the second cycle of the DMA transfer, the buffer control signal line 46 controls so as to hold the subsequent data DAT2 in the buffer 87 via the local data bus 47 of the communication control device, thereby converting continuous data into a single data. Can be aligned. BU
The RST generation circuit 74 uses the BURST signal line 45 for DMA.
A signal whose polarity is inverted from that in the first transfer cycle is output.
At this time, the sorted data DAT5 is output to the external bus 49 by the sorting circuit 48. Address generation circuit 8 at the same time
From 4, the first DMA data transfer start address AD
R1 is output to the external bus 44 and data is transferred between the external memories 54. Thereafter, operations similar to those in the first and second cycles of the DMA transfer are performed in the third and fourth cycles of the DMA transfer, respectively.

In this embodiment, the BURST signal line 45 is D
Although the signal is asserted in the first cycle of the MA transfer and negated in the second cycle of the DMA transfer, it may be a signal negated in the first cycle of the DMA transfer and asserted in the second cycle of the DMA transfer. Further, the serial speed and the system clock frequency may be any values. The DMA cycle may be 2 clocks / cycle, 1 clock / cycle, or any other number of cycles. Furthermore, the DMA speed does not impose any limitation.

[0042]

According to the present invention, there is an effect that it is possible to realize a communication control device and a communication system having a high degree of freedom capable of coping with an arbitrary system bus width and having high transfer efficiency.

Further, the system can be downsized and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a communication control device showing an embodiment of the present invention.

FIG. 2 is a block configuration diagram supplementing the communication control device in FIG.

FIG. 3 is a block configuration diagram supplementing the communication control device in FIG.

FIG. 4 is a time chart explaining the operation of the embodiment of FIG.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a time chart explaining the operation of a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Communication control device, 14, 16 ... Transmission FIFO, 15,
17 ... Reception FIFO, 22 ... (Output of remaining data number of transmission FIFO 14) Signal line, 23 ... (Output of remaining data number of reception FIFO 15)
Signal line, 24 ... (output of remaining data number of transmission FIFO 16) signal line, 25 ... (output of remaining data number of reception FIFO 17) signal line, 2
6, 27, 28, 29 ... DMAC channel, 30 ... DM
AC control circuit, 40 ... Bus arbitration circuit, 41 ... Bus acknowledge, 42 ... Bus request, 44 ... External bus, 45
... BURST signal line, 46 ... buffer control signal line, 47
... local data bus of communication control device, 48 ... alignment circuit, 54 ... external memory, 72, 73, 74, 75 ... BU
RST generation circuit, 76, 77, 79, 80, 81, 8
2, 83 ... Register, 78 ... Data word number setting register,
84 ... Address generation circuit, 85 ... BURST control circuit,
86, 87 ... buffer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Keiji Ichige 3-1-1, Saiwaicho, Hitachi, Ibaraki Hitachi Ltd. Hitachi factory (72) Inventor Shigeo Kuboki Sanukicho, Hitachi, Ibaraki 1-chome 1-1 Hitachi Ltd. Hitachi factory (72) Inventor Yoshiaki Yasuma 3-2-1 yukicho, Hitachi-shi, Ibaraki Hitachi Engineering Co., Ltd. (72) Inventor Yoshinori Atsuwa Ibaraki prefecture 3-1, 1-1 Saiwaicho, Hitachi, Ltd. Hitachi, Ltd. Hitachi factory (72) Inventor Isao Saito 3-10-2 Bentencho, Hitachi City, Ibaraki Hitachi, Haramachi Electronics Co., Ltd. (72) Inventor Iwama Satoko 3-2-1, Saiwaicho, Hitachi, Ibaraki Hitachi Engineering Co., Ltd. (72) Inventor Fujinaga ▲ Taka ▼ Tadashi 3-1-1, Saiwaicho, Hitachi, Ibaraki Stand Works Hitachi in the factory

Claims (16)

[Claims] 1. A communication control device for performing DMA (Direct Memory Access) transfer of a plurality of data to and from an external device via an external data bus, wherein the DMA transfer is controlled and the plurality of data are continuous data. And a DMA controller that generates a signal indicating that 2. The communication control device according to claim 1, wherein the number of bits of the external data bus is larger than the number of bits of each of the plurality of data. 3. The communication control device according to claim 1, wherein the number of bits of the external data bus is a sum of each of the plurality of data. 4. The communication control device according to claim 1, wherein the number of bits of each of the plurality of data is N bits, and the number of bits of the external data bus is 2N bits. . 5. The communication control device according to claim 1, wherein the signal is synchronized with the plurality of data. 6. The communication control device according to claim 1, wherein the plurality of data are at least first data and the first data.
Communication data, which is continuous with the second data, and the signal is synchronized with the first data. 7. The communication control device according to claim 1, wherein the signal is synchronized with a DMA cycle. 8. A communication control for performing DMA (Direct Memory Access) transfer of a plurality of data between an external data bus, an external device connected to the external data bus, and the external device via the external data bus. A communication control device for controlling the DMA transfer and having a DMA controller for generating a signal indicating that the plurality of data are continuous data; and a communication controller between the external data bus and the communication control device. And a plurality of data and the signal are input from the communication control device, and the plurality of data are aligned into a single data according to the input of the signal and output to the external data bus. And a communication system comprising: 9. The communication system according to claim 8, wherein the number of bits of the external data bus is larger than the number of bits of each of the plurality of data. 10. The communication system according to claim 8, wherein the number of bits of the external data bus is a sum of each of the plurality of data. 11. The communication system according to claim 8, wherein the number of bits of each of the plurality of data is N bits, and the number of bits of the external data bus is 2N bits. 12. The communication system according to claim 8, wherein the signal is synchronized with the plurality of data. 13. The communication system according to claim 8, wherein the plurality of data includes at least first data and second data that is continuous with the first data, and the signal is the first data. A communication system characterized by being synchronized with the data of. 14. The communication system according to claim 8, wherein said signal is synchronized with a DMA cycle. 15. The communication system according to claim 8, wherein the plurality of data are at least a first data and a second data continuous to the first data in one DMA cycle.
Of the first data and the second data, the single data having a total number of bits of at least the first data and the second data, and the signal is A communication control device characterized by being synchronized with data. 16. The communication system according to claim 8, wherein the plurality of data are at least a first data and a second data continuous to the first data in one DMA cycle.
The number of bits of the first data and the second data is N bits, the number of bits of the single data is 2N bits, and the signal is A communication control device characterized in that the communication control device is synchronized with the first data.