JPH09308261A - Over-current protection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To hold a switching element in the off-state by judging an irregular short circuit of the feeding path from the operating condition (operation frequency) of over-current protection. SOLUTION: This circuit protects, when a comparator 26 detects an over- current, transistors Tr1, Tr3 from over-current, by outputting a power feeding cutoff signal Sc only for the preset period from an RS flip-flop 28 to forcibly turn off the transistors Tr1, Tr3. In this case, when the RS flip-flop 28 outputs the power feeding cutoff signal Sc, the subsequent elapsed time is metered by an operation frequency monitoring timer 32. When the elapsed time reaches the preset monitoring time, the transistors Tr1 to Tr4 are held in the off-state. Meanwhile, the RS flip-flop 28 stops outputting the power feeding cutoff signal Sc, the elapsed time until output of the next power feeding cutoff signal Sc is metered with an operation frequency monitoring canceling timer 30 and when such elapsed time reaches the canceling time, the operation frequency monitoring timer 32 is reset.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive device for driving an electric load by turning on / off a switching element such as a transistor provided in its energization path, and detecting an overcurrent flowing in the switching element to drive the switching element. The present invention relates to an overcurrent protection circuit that protects a switching element from overcurrent by forcibly turning off.

[0002]

2. Description of the Related Art Conventionally, for example, Japanese Laid-Open Patent Publication No. 5-30073.
As disclosed in Japanese Patent Publication No. 1, a current flowing through an electric load through a transistor is detected from a voltage across a resistor provided in a current-carrying path of the electric load, and when the detected current becomes an overcurrent of a predetermined value or more. , Forcibly turn off the transistor for a certain period of time to protect the transistor from overcurrent, and also monitor the operating status of such overcurrent protection, and overcurrent protection (that is, forced off of the transistor) was frequently executed. In that case, there is known an overcurrent protection circuit which holds the transistor in an off state and prohibits the transistor from being turned on again.

In this type of overcurrent protection circuit, if the transistor is held in the OFF state at the time when the overcurrent is detected, the overcurrent may temporarily flow in the energizing path of the electric load due to noise or the like. However, since the electric load cannot be driven, the transistor is forcibly turned off for a predetermined protection time when an overcurrent is detected, and the frequency monitoring circuit determines the frequency of such forced off. If you monitor it and its frequency exceeds a certain level,
It is determined that an abnormality such as a short circuit has occurred in the energization path of the electric load, and the transistor is held in the off state.

[0004]

However, in the conventional frequency monitoring circuit, the capacitor is charged with a predetermined charging time constant during the protection period in which the overcurrent is detected and the transistor is forcibly turned off, and the transistor is forcibly forced. It consists of a capacitor charging / discharging circuit that discharges the capacitor with a predetermined discharge time constant within the recovery period when the off state is released.
When the voltage across the capacitor of the charge / discharge circuit (that is, the amount of charge charged) reaches a predetermined level, it is determined that the frequency of forced off has reached a predetermined degree or more, and the transistor is held in the off state. Therefore, for example, when the abnormality of the energization path is intermittently eliminated by vibration or the like, the abnormality may not be detected.

That is, when the abnormality of the energization path is intermittently eliminated, the capacitor is discharged during the elimination period, so that the voltage across the capacitor does not reach a predetermined level and the transistor is held in the off state. It is impossible to shift to the holding operation. When it is not possible to shift to the holding operation to hold the transistor in the OFF state in this way, an overcurrent flows to the transistor and the operation of overcurrent protection to forcibly turn off the transistor for a certain period of time is repeatedly executed. Gradually deteriorates, and eventually the electric load cannot be driven well,
Such a problem occurs.

The frequency monitoring circuit is constructed so as to count the number of overcurrent detections within a predetermined monitoring time, and when the count value reaches a predetermined value, it judges an abnormality in the energizing path. It is also considered to keep the transistor in the off state, but even in this case, when the abnormality of the energization path is intermittently eliminated, the count value is a predetermined value for determining the abnormality of the energization path. Since the value is never reached, the same problem as above occurs.

The present invention has been made in view of these problems, and in an overcurrent protection circuit for detecting an overcurrent and forcibly turning off a switching element such as a transistor for a certain period of time,
An object of the present invention is to reliably determine an abnormality in the energization path from the operation state of the overcurrent protection and to be able to shift to the holding operation for holding the switching element in the off state.

[0008]

In the overcurrent protection circuit according to the first aspect of the present invention, which is made to achieve the above object, the detecting means detects an overcurrent of a predetermined current value or more flowing in the switching element, When the detection means detects the overcurrent, the protection means forcibly turns off the switching element for a predetermined protection time. Then, the frequency monitoring means monitors the frequency at which the protection means turns off the switching element, and when the frequency becomes greater than a predetermined degree, the switching element is forcibly turned off and the off state is maintained.

In the frequency monitoring means, once the protection means turns off the switching element, the first timer means measures the elapsed time thereafter, and the protection means forcibly turns off the switching element as the protection time elapses. When the command is released, the second timer means measures the elapsed time in the normal time until the detection means detects the overcurrent thereafter.

Then, the second timer means resets the first timer means to stop the time counting by the first timer means when the elapsed time in the normal time reaches a predetermined release time. Further, the first timer means generates a holding command for holding the switching element in the off state when the elapsed time after the switching element is forcibly turned off, which is measured by itself, reaches a preset monitoring time. Then, when the holding instruction is output from the first timer means, the holding means turns off the switching element and starts a holding operation for holding the off state.

That is, in the overcurrent protection circuit of the present invention, the frequency at which the switching element is forcibly turned off is monitored by charging and discharging the capacitor during the off period and the on period of the switching element as in the conventional case. not,
(1) Basically, when the detection means detects an overcurrent and the protection means operates, the first timer means measures the elapsed time thereafter, and the elapsed time is equal to a predetermined monitoring time. At this point, the holding means starts a holding operation for holding the switching element in the off state, and (2)
The first timer means is activated only when the time when the overcurrent is not detected after the forced off of the switching element is reached reaches the predetermined release time within the monitoring time when the holding means enters the holding operation after the overcurrent detection. It is reset so that the holding means is prohibited from entering the holding operation of the switching element.

Therefore, according to the present invention, when the switching element is forcibly turned off once the overcurrent is detected and the off state is released, the normal time until the overcurrent is detected again becomes If the release time is shorter than the release time, regardless of the number of overcurrent detections within the frequency monitoring time, after the overtime is detected for the first time, the switching operation to hold the switching element in the off state is performed after the monitoring time elapses. Therefore, even when the abnormality of the energization path is intermittently eliminated by vibration or the like, it is possible to reliably determine the abnormality and prohibit the switching element from being turned on.

Therefore, according to the present invention, as in the prior art,
Even if there is a short circuit abnormality in the energization path, it is possible to prevent the switching element from deteriorating due to failure to shift to the holding operation to hold the switching element in the OFF state, and the switching element is reliably protected from overcurrent. It becomes possible to protect.

As the release time from when the second timer means starts counting time until when the first timer means is reset, as described in claim 1, the first timer means starts counting time. It is necessary to set the time shorter than the time (monitoring time-protection time) obtained by subtracting the protection time for which the protection unit forcibly turns off the switching element from the monitoring time from when the holding command is issued until the holding command is generated. This is because when the release time is set to a time longer than the time obtained by subtracting the protection time from the monitoring time, the holding means is set before the second timer means measures the release time and resets the first timer means. Frequency monitoring to prevent the switching element from being held in the off state when the switching element enters a holding operation to hold the switching element in the off state and a temporary overcurrent flows through the switching element due to noise or the like. This is because the intended purpose of the means cannot be achieved.

Next, the overcurrent protection circuit according to claim 2 is
This is for protecting a switching element from an overcurrent in a drive device in which a switching element is turned on / off by a pulse width modulation signal to duty-drive an electric load. Then, in this overcurrent protection circuit, the protection means forcibly turns off the switching element based on the clock signal of a constant cycle used for generating the pulse width modulation signal for driving the switching element in the driving device. Set the release timing of the later off state.

In other words, as a drive device for duty-driving an electric load by turning on / off a switching element with a pulse width modulation signal (hereinafter, simply referred to as a PWM signal),
Conventionally, a triangular wave generating circuit is used to generate a triangular wave whose signal level increases and decreases in a constant cycle, and the generated triangular wave and a control signal are compared in magnitude by using a comparator or the like, so that a PWM for driving a switching element is generated. Consisting of analog circuits configured to generate a signal,
Use a digital timer or the like to generate a pulse signal for a period corresponding to the duty ratio at regular intervals, and generate a PWM signal
It is known to use a digital circuit that outputs a signal to a switching element, but in such a drive device, a clock signal of a constant cycle is generated in order to keep the generation cycle of a triangular wave or a pulse signal constant. An oscillator is provided.

Therefore, in the present invention (claim 2), in the protection means, based on the clock signal from this oscillator,
By setting the release timing to release the OFF state after the switching element is forcibly turned off, the protection means can be configured without providing any special timing means for measuring the protection time after the switching element is forcibly turned off. is there. Therefore, according to the present invention, it is possible to simplify the configuration of the protection means, and further, the configuration of the overcurrent protection circuit.

Next, the overcurrent protection circuit according to claim 3 is
As a switching element, a pair of positive-electrode side switching elements provided respectively between two terminals for power supply of an electric load and a positive electrode side of a DC power supply, and a pair of switching elements provided between the two terminals for power supply and a negative electrode side of a DC power supply. A so-called H-bridge type drive that includes a pair of negative side switching elements, and can switch the direction of the current flowing through the electric load bidirectionally by combining the pair of positive side and negative side switching elements in the ON state. It is applied to the device.

In the present invention, the positive side detecting means and the positive side protecting means are provided for the pair of positive side switching elements which are so-called high side switches, and the negative side is provided for the pair of negative side switching elements which are so-called low side switches. Side detecting means and negative side protecting means are provided respectively, and when an overcurrent flows in any of the positive side switching elements, the positive side detecting means detects that fact, and the positive side protecting means makes a pair of If the positive electrode side switching element is forcibly turned off for the protection time and an overcurrent flows in any of the negative electrode side switching elements, the negative electrode side detection means detects that fact and the negative electrode side protection means detects it. The pair of negative electrode side switching elements are forcibly turned off for the protection time.

In the frequency monitoring means, when at least one of the positive electrode side protection means and the negative electrode side protection means turns off the switching element, the first timer means starts counting the elapsed time thereafter, and the second timer means The timer means counts the elapsed time until the overcurrent is detected by either the positive electrode side detecting means or the negative electrode side detecting means after the forced off of the switching element is released.

Therefore, according to the present invention, in the H-bridge type driving device, one of the two terminals for power supply of the electric load is short-circuited to the positive side or the negative side of the DC power source, and among the four switching elements. When an overcurrent starts to flow in any of the above, it is possible to determine that by using one frequency monitoring means and prevent the switching element from being deteriorated by the overcurrent. Further, overcurrent detection and overcurrent protection (forced off only for the protection time) for the four switching elements can be performed by two systems of detection means and protection means on the positive electrode side and the negative electrode side.

Therefore, according to the present invention, in the H-bridge type driving device, each switching element is surely protected from an overcurrent without providing a detection means, a protection means, and a frequency monitoring means for each switching element. Can be protected.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram illustrating a configuration of a driving device of a DC motor 10 that opens and closes a throttle valve of an engine.

In this embodiment, the DC motor 10
The upper limit of the throttle opening is restricted by a restricting member that is displaced according to the amount of depression of the accelerator pedal, and the throttle valve that is opened and closed is biased in the opening direction (in other words, the restricting member direction) by a spring. DC motor 10
Controls the throttle opening by driving the throttle valve in the closing direction against the biasing force of the spring.

As shown in FIG. 1, terminals connected to both ends of the DC motor 10 via wire harnesses (for power feeding 2
MO) of P channel (Pch) to terminals A and B, respectively.
S-type FET (hereinafter referred to as transistor) Tr1 and Tr3 drains and N-channel (Nch) MOS-type FET
The drains of Tr2 and Tr4 (hereinafter referred to as transistors) are connected to each other.

The transistors Tr1 and Tr3 are for applying a positive voltage to the terminals A and B (positive side switching element), and their sources are connected via a resistor Rs for current detection and an ignition switch 4. And is connected to the positive terminal of the battery 2. Also, the transistor T
r2 and Tr4 are for applying a negative voltage to the terminals A and B, respectively (negative side switching element), and the source thereof is a ground line (hereinafter referred to as GND) having the same potential as the negative terminal of the battery 2. It is connected. That is, the DC motor 10 is provided with the H-bridge type drive circuit 6 including these four transistors Tr1 to Tr4.

In the H-bridge type drive circuit 6 as described above, when all the transistors Tr1 to Tr4 are in the off state, the transistor Tr1 on the positive electrode side connected to the terminal A,
If the transistor Tr4 on the negative electrode side connected to the terminal B is turned on at the same time, a current can flow from the terminal A to the terminal B side with respect to the DC motor 10 to rotate the DC motor 10 in one direction. When the transistor Tr3 on the positive electrode side connected to the terminal B and the transistor Tr2 on the negative electrode side connected to the terminal A are simultaneously turned on, a current flows from the terminal B to the terminal A side with respect to the DC motor 10, DC motor 10
Can be rotated in the opposite direction. Further, in the present embodiment, when the DC motor 10 is de-energized, the throttle valve is opened to the maximum opening degree according to the depression amount of the accelerator pedal by the above-mentioned spring, and the rotational position of the DC motor 10 is also maintained at that position. It

Therefore, in this embodiment, when the throttle opening is controlled, the DC motor 10 is indicated by an arrow in the drawing in order to drive the throttle valve in the closing direction against the biasing force of the spring. The motor current iM is made to flow only in a fixed direction (from the terminal A to the terminal B). Further, since the motor current iM can be controlled to control the rotational position (and thus the throttle opening) of the DC motor 10, the drive control of the DC motor 10 in this embodiment is performed by the four transistors Tr1 to Tr1. Of Tr4, the positive-side transistor Tr1 connected to the terminal A is held in the ON state and the negative-side transistor Tr2 is held in the OFF state, respectively, and the negative-side transistor Tr4 and the positive-side transistor Tr3 connected to the terminal B are connected. Is performed by alternately switching the on / off state of.

That is, the P-channel transistor Tr1,
The drive signals O1 and O3 input to the gate of Tr3 are low
When it is at the level, it is turned on, and the N-channel transistors Tr2 and Tr4 are driven by the drive signal O input to the gate.
When O2 and O4 are high level, it is turned on. Therefore, in the present embodiment, as shown in FIG. 2 (refer to the normal region), the drive signals O1 and O2 of the transistors Tr1 and Tr2 are both held at the low level, so that the transistor T
By turning on r1 and turning off transistor Tr2, and inputting drive signals O3 and O4 of the same level whose duty is controlled according to the target throttle opening to transistors Tr3 and Tr4, the transistors Tr3 and Tr4 are turned on. Alternates the off state alternately.

As a result, the drive signals O3 and O4 become High level, the transistor Tr3 is turned off, and the transistor Tr4 is turned on.
When is turned on, the motor current iM rises,
When the drive signals O3 and O4 are at low level, the transistor Tr3 is on and the transistor Tr4 is off, the magnetic energy accumulated in the DC motor 10 regenerates the transistors Tr3, Tr1 and the closed circuit of the DC motor 10. A current flows, the motor current iM is attenuated, and finally the motor current iM becomes zero. Then, a torque is generated in the DC motor 10 according to the on / off time ratio (duty ratio) of the transistor Tr4, and the DC motor 10 (and hence the throttle valve) generates the generated torque and the biasing force of the spring. Are controlled to a balanced position.

Next, the drive signals O1 to O4 of the respective transistors Tr1 to Tr4 for such throttle control receive a control signal representing a target throttle opening degree from an engine control circuit (not shown), and this control signal and the triangular wave generating circuit 14 are supplied.
The PWM control circuit 16 generates a pulse width modulation signal (PWM signal) by comparing the generated triangular wave with the triangular wave.

In this embodiment, each transistor T
In order to protect r1 to Tr4 from overcurrent, the PWM signals generated by the PWM control circuit 16 are not directly used as the drive signals O1 to O4 of the transistors Tr1 to Tr4, but to the transistors Tr1 and Tr3, PWM control circuit 16
The PWM signal generated at is input via the OR circuits 21 and 23, and the PWM is applied to the transistors Tr2 and Tr4.
The NOR circuit 2 receives the PWM signal generated by the control circuit 16.
Input via 2, 24.

That is, in this embodiment, the PWM control circuit 1
By providing OR circuits 21 and 23 or NOR circuits 22 and 24 in the drive signal input system from 6 to each of the transistors Tr1 to Tr4, a high level energization cutoff signal output from an overcurrent protection circuit described later is provided to each of these. Circuits 21-24
To each transistor Tr1 to Tr4 forcibly turning off.

As described above, the drive signal input system from the PWM control circuit 16 to each of the transistors Tr1 to Tr4 has an O
Since the R circuits 21 and 23 and the NOR circuits 22 and 24 are provided, the PWM control circuit 16 outputs the low power-off signal.
When it is at the level, the PWM signal is generated so that the drive signals O1 to O4 output from these circuits 21 to 24 change as shown in the normal region of FIG. That is, P
The WM control circuit 16 generates a PWM signal that goes to a low level when turning on the transistor and goes to a high level when turning off the transistor, and the drive signal O1 input to each of the transistors Tr1 to Tr4 under normal conditions. .About.O4 is varied as shown in FIG.

Next, in the drive device of the DC motor 10 of this embodiment, the comparator 26 and the RS flip-flop 2 are provided.
8, frequency monitoring cancellation timer 30, frequency monitoring timer 32, R
An overcurrent protection circuit including an S flip-flop 36 is provided. The comparator 26 corresponds to the detection means of the present invention, and has a voltage VRS across the resistor Rs provided in the energization path from the positive terminal of the battery 2 to the DC motor 10 and a reference voltage VT for overcurrent determination. And compare
When VRS ≧ VT, it is determined that an overcurrent has flown in the transistor Tr1 or Tr3, and the high level detection signal Sa
Occurs.

Next, the RS flip-flop 28 corresponds to the protection means of the present invention, and its set terminal S
The detection signal Sa from the comparator 26 is input to. When the RS flip-flop 28 is set by the detection signal Sa, the RS flip-flop 28 generates a high-level energization cutoff signal Sc from the output terminal Q, which outputs the OR circuit 21,
By outputting it to 23, the transistors Tr1 and Tr3 are forcibly turned off.

At the reset terminal R of the RS flip-flop 28, the pulse signal S from the pulse generating circuit 12 is sent.
When b is input and the RS flip-flop 28 receives the pulse signal Sb, the RS flip-flop 28 stops outputting the energization cutoff signal Sc. The pulse generation circuit 12 is the triangular wave generation circuit 1
An internal clock used to generate a triangular wave at 4 is used to generate a pulse signal Sb synchronized with the PWM signal.

Next, the frequency monitoring cancel timer 30 corresponds to the second timer means which constitutes the frequency monitoring means of the present invention, and includes the charging / discharging capacitor C1 and the internal power supply voltage (constant voltage). ), The resistor R1 that charges the capacitor C1 with a constant time constant is compared with the reference voltage V1 and the voltage Vd across the capacitor C1.
Is high when the voltage Vd across both ends is higher than the reference voltage V1.
Comparator 30 for outputting level reset signal Se
a and the energization cutoff signal S from the RS flip-flop 28
It is composed of an NPN type bipolar transistor (hereinafter simply referred to as a transistor) Q1 which is turned on upon receiving c (High level) and discharges the electric charge accumulated in the capacitor C1.

Therefore, in the frequency monitoring cancel timer 30, the energization cutoff signal Sc is sent from the RS flip-flop 28.
(High level) is output and the transistors Tr1 and Tr3 are output.
Is forcibly turned off, the transistor Q1 is turned on, the capacitor C1 is discharged, the output of the energization cutoff signal Sc (High level) from the RS flip-flop 28 is stopped, and the transistors Tr1 and Tr3 are forced to be forced. When the off state is released, the transistor Q1 is turned off and the capacitor C1 is charged with a constant time constant.

When the capacitor C1 is charged,
Until the voltage Vd across the capacitor C1 reaches the reference voltage V1, the low-level reset signal Se is output from the comparator 30a and the voltage Vd across the capacitor C1 is reached.
When d reaches the reference voltage V1 (in other words, when the charging time of the capacitor C1 reaches the release time corresponding to the reference voltage V1), the comparator 30a outputs the high-level reset signal Se.

The reset signal Se is input to one input terminal of the OR circuit 34. OR circuit 3
The other input terminal of 4 has a release signal input terminal 40 and N
A cancellation signal from the outside is input via the OT circuit 41 via the NOT circuit 41. Then, the OR circuit 34 inputs a high level signal to the frequency monitoring timer 32 when at least one of the reset signal Se and the release signal input to these two input terminals is at a high level.

Next, the frequency monitoring timer 32 corresponds to the first timer means constituting the frequency monitoring means of the present invention, and receives the charging / discharging capacitor C2 and the internal power supply voltage (constant voltage). The resistor R2 that charges the capacitor C2 with a constant time constant, and the voltage V across the capacitor C2.
f is compared with the reference voltage V2, and when the voltage Vf across the capacitor C2 is equal to or higher than the reference voltage V2, the comparator 32a that outputs the holding signal Sg at the High level and the input signal from the OR circuit 34 are at the High level. It is composed of an NPN bipolar transistor (hereinafter simply referred to as transistor) Q2 which is turned on at a certain time and discharges the electric charge accumulated in the capacitor C2.

Therefore, in the frequency monitoring timer 32, the high level reset signal S from the frequency monitoring canceling timer 30.
e is output or Lo is externally applied to the release signal input terminal 40.
When the w-level cancellation signal is input, the output signal (High level) from the OR circuit 34 turns on the transistor Q2 to discharge the capacitor C2, and the reset signal from the frequency monitoring cancellation timer 30 becomes Low level. Yes, the release signal input to release signal input terminal 40 from outside is high
When it is at the level, the output signal (Low
Level) turns off the transistor Q2 and charges the capacitor C2 with a constant time constant.

When the capacitor C2 is charged,
Until the voltage Vf across the capacitor C2 reaches the reference voltage V2, the low-level holding signal Sg is output from the comparator 32a, and the voltage Vf across the capacitor C2 reaches the reference voltage V2 (in other words, the capacitor C2
(When the charging time of S reaches the monitoring time corresponding to the reference voltage V2), the holding signal S of High level is output from the comparator 32a.
g is output.

Next, the RS flip-flop 36 corresponds to the holding means which constitutes the frequency monitoring means of the present invention, and the holding signal Sg from the frequency monitoring timer 32 is input to the set terminal S thereof. Then, in the RS flip-flop 36, the holding signal Sg becomes High level,
When set, a high-level energization cutoff signal Sh is generated from the output terminal Q, and this is ORed through the OR circuit 38.
By outputting to the circuits 21 and 23 and the NOR circuits 22 and 24, respectively, the transistors Tr1 to Tr4 are forcibly turned off.

The reset terminal R of the RS flip-flop 36 is externally supplied with the release signal input to the release signal input terminal 40 through the NOT circuit 41, and is reset when the release signal becomes low level. Then, the output of the energization cutoff signal Sh (High level) is stopped. Also,
This energization cutoff signal Sh (High level) is supplied to the OR circuit 21,
The release signal externally input to the release signal input terminal 40 via the NOT circuit 41 is also input to the other input terminal of the OR circuit 38 that outputs to the 23 and the NOR circuits 22 and 24, respectively.

Next, the operation of the overcurrent protection circuit of the present embodiment constructed as described above will be explained using the time charts shown in FIGS. In the following description, the release signal input terminal 40 is assumed to be held at High level. As shown in FIG. 2, when the PWM control for controlling the throttle opening to the target opening is being executed, for example,
At time t0, when the wire harness connecting the terminal A and the DC motor 10 is shorted to GND, the transistor Tr1
The current flowing therethrough sharply rises, and accordingly the voltage VRS across the resistor Rs also sharply rises. When the voltage VRS reaches the reference voltage VT for overcurrent determination, the comparator 26
To that effect (that is, overcurrent) is detected, and the detection signal S
a becomes High level (time t1).

Then, the RS flip-flop 28 is set by the detection signal Sa, the high level energization interruption signal Sc is output from the RS flip-flop 28, and the drive signals O1 and O3 of the transistors Tr1 and Tr3 are Hig.
At the h level, these transistors Tr1 and Tr3 are turned off. As a result, the transistor Tr1 is protected from overcurrent.

Next, since the RS flip-flop 28 is reset by the pulse signal Sb from the pulse generating circuit 12, even if the overcurrent protection is temporarily entered at the time t1, the protection set by the pulse signal Sb is set. After the lapse of time, the energization cutoff signal Sc returns to the low level. Then, the transistor Tr1 is turned on again by the output from the PWM control circuit 16, so that the transistor Tr1 is turned on.
An overcurrent flows to the transistor 26, which is detected by the comparator 26, and the RS flip-flop 28 outputs the high-level energization cutoff signal Sc again, and the transistors Tr1 and T1.
r3 is forced off. Then, after that, the RS flip-flop 28 is reset by the pulse signal from the pulse generating circuit 12, so that the operation of the overcurrent protection is repeatedly executed, and the transistor Tr1 is periodically turned on / off. .

When the operation for overcurrent protection is started at time t1, the DC motor 10 is not driven and the throttle opening becomes the maximum opening according to the amount of depression of the accelerator pedal. Therefore, the PWM control is performed. Transistor Tr4 from circuit 16
A pulse width modulation signal with a duty ratio of 100% for continuously turning on is output, and the drive signals O3 and O4 of the transistors Tr3 and Tr4 are held at the high level.

On the other hand, as described above, the energization cutoff signal Sc (High level) from the RS flip-flop 28 at time t1.
Is output, the capacitor C1 in the frequency monitoring cancel timer 30 is discharged, and the output (reset signal Se) from the frequency monitoring cancel timer 30 becomes low level, so that the transistor Q2 of the frequency monitoring timer 32 is turned off. Become,
The capacitor C2 is charged with a constant time constant determined by the capacitance of the capacitor C2 and the resistance value of the resistor R2.

Further, the RS flip-flop 28 is reset by the pulse signal Sb from the pulse generating circuit 12 after the output of the energization cutoff signal Sc (High level) is started, and the output is stopped. When the wire harness connecting to the motor 10 is short-circuited, the overcurrent is detected by the comparator 26 as described above,
It is reset again, and the output of the energization cutoff signal Sc (High level) is restarted in a short time. Therefore, the capacitor C1 in the frequency monitoring cancellation timer 30 is for a short period of time after the RS flip-flop 28 is reset by the pulse signal Sb from the pulse generation circuit 12 and before the overcurrent is detected by the comparator 26. Capacitance of capacitor C1 and resistor R
Although it is charged with a constant time constant determined by the resistance value of 1, the voltage Vd across it is never reached the reference voltage V1.

Therefore, when the wire harness between the terminal A and the DC motor 10 is short-circuited and the overcurrent protection circuit enters the overcurrent protection operation (time point t1), both ends of the capacitor C2 of the frequency monitoring timer 32 are thereafter. At the time t2 when the voltage Vf reaches the predetermined monitoring time corresponding to the reference voltage V2, the frequency monitoring timer 32 outputs the holding signal Sg (High level).

The RS flip-flop 36 is set by the holding signal Sg, so that the time t2
After that, the energization cutoff signal Sh (High level) is input to the OR circuits 21 and 23 and the NOR circuits 22 and 24, and all the four transistors Tr1 to Tr4 forming the drive circuit 6 are held in the off state. become.

The holding operation of holding each of the transistors Tr1 to Tr4 in the off state is held until the release signal input to the release signal input terminal 40 of the RS flip-flop 36 becomes low level. That is, after the time point t2 when the overcurrent protection circuit enters the holding operation for holding each of the transistors Tr1 to Tr4 in the off state, at the time point t3, the voltage Vd across the capacitor C1 in the frequency monitoring cancellation timer 30 is changed to the reference voltage V1. Even if it reaches, the holding operation is continued until the frequency of the release signal input terminal 40 is once set to the Low level and the frequency monitoring timer 32 and the RS flip-flop 36 are reset.

Next, as shown in FIG. 3, a short circuit to GND of the wire harness between the terminal A and the DC motor 10
In the case of intermittent cancellation due to vibration of the engine or a vehicle equipped with this engine, even if the overcurrent protection circuit once enters the overcurrent protection operation, during the normal recovery period (time t11 to t12) Therefore, the comparator 26 temporarily stops detecting the overcurrent.

At this time, the transistors Tr1 to Tr4
If the holding operation to hold the switch in the off state is not started, the drive device returns to the normal PWM control during the normal return period, but the wire harness between the terminal A and the DC motor 10 is short-circuited to GND again. At time t12, the transistor Tr1
Since an overcurrent flows in the overcurrent protection circuit, the overcurrent protection circuit starts the overcurrent protection operation again after time t13 after the current rises.

On the other hand, since such a temporary normal restoration period (time points t11 to t12) is short, the voltage V across the capacitor C1 in the frequency monitoring cancellation timer 30 is reduced during this restoration period.
d will never reach the reference voltage V1 and therefore the capacitor C2 in the frequency monitoring timer 32 will not be discharged.

As a result, the capacitor in the frequency monitoring timer 32 is continuously charged after the wire harness is first short-circuited and an overcurrent is detected, and the overcurrent protection circuit is initially charged. After the overcurrent is detected, at a time point t14 when a predetermined monitoring time has elapsed, the holding operation for holding the transistors Tr1 to Tr4 in the off state is started.

That is, in the overcurrent protection circuit of this embodiment,
No matter how many times the short circuit to GND of the wire harness connecting the terminal A and the DC motor 10 is eliminated, the duration of each time is equal to the reference voltage V1 at the voltage Vd across the capacitor C1 in the frequency monitoring cancellation timer 30. When it is shorter than the release time required to become, the time from first detecting the overcurrent to holding the transistors Tr1 to Tr4 in the off state does not change, and this time is the frequency monitoring timer 32.
This is a constant time (monitoring time) required to charge the capacitor C2 to the reference voltage V2.

Therefore, according to the overcurrent protection circuit of the present embodiment, even if the short circuit abnormality of the wire harness is temporarily eliminated by vibration as described above, the abnormality can be reliably judged. , The transistors Tr1 to Tr4 can be held in the off state, and the transistors Tr1 to Tr4 can be reliably protected from overcurrent.

On the other hand, in the overcurrent protection circuit of this embodiment, when an overcurrent flows through the transistor Tr1 due to noise or the like and the comparator 26 determines that, an increase in the transistors Tr1 and Tr3 is performed in the same manner as above. Is forcibly turned off, but when such a temporary abnormality occurs, even if it enters overcurrent protection, it will immediately return to normal,
After that, the normal state will be continued.

In the overcurrent protection circuit of this embodiment,
As shown in FIG. 4, the elapsed time from the normal recovery (time t
The elapsed time after 21) is measured by a frequency monitoring cancellation timer 30 that measures the elapsed time after the RS flip-flop 28 cancels the output of the energization cutoff signal Sc (High level) by charging the capacitor C1. When the measured time reaches the release time and the voltage Vd across the capacitor C1 becomes equal to or higher than the reference voltage V1 (time point t22), the frequency monitoring timer 3
A reset signal Se (High level) is input to 2, the transistor Q2 is turned on, and the capacitor C2 in the frequency monitoring timer 32 is quickly discharged.

In this state, the comparator 26 detects the next overcurrent, and the RS flip-flop 28
Is continued until the energization cutoff signal Sc is output from.
Therefore, according to the overcurrent protection circuit of the present embodiment, the transistors Tr1 to Tr4 are used when a temporary abnormality occurs, such as when an overcurrent flows through the transistor Tr1 due to noise or the like.
Does not shift to the holding operation to hold the
The DC motor 10 can be continuously driven and controlled.

As shown in FIG. 5, in the frequency monitoring timer 32, the monitoring time Δt2 until the voltage Vf across the capacitor C2 reaches the reference voltage V2 is equal to the voltage Vd across the capacitor C1 in the frequency monitoring cancellation timer 30. 0V
To the reference voltage V1 from the release time .DELTA.t1 to the release time .DELTA.td at which the RS flip-flop 28 outputs the energization cutoff signal Sc after the overcurrent is detected (time .DELTA.t1 +
When it is shorter than Δtd, the frequency monitoring timer 32 is reset by the reset signal Se (that is, the capacitor C
2 cannot be discharged) and the holding operation for holding each of the transistors Tr1 to Tr4 in the off state is started only by detecting the overcurrent once.

Therefore, when the overcurrent protection circuit of this embodiment is realized, the time constant for charging the capacitors C1 and C2 in the frequency monitoring cancel timer 30 and the frequency monitoring timer 32, that is, the capacitance of the capacitors C1 and C2. And resistor R
The resistance values of 1 and R2 must be at least the monitoring time Δt2
Release time Δt1 plus holding time Δtd (Δt1 +
Longer than Δtd) {(Δt1 + Δtd) <Δt
2}, it is necessary to set.

Since the holding time Δtd is determined by the pulse signal Sb from the pulse generating circuit 12, it is more certain that the monitoring time Δt2 is at least the release time Δt1 from the pulse generating circuit 12 when the monitoring time Δt2 is released. Pulse signal S
The generation frequency of b (in other words, the generation cycle of the PWM signal on the driving device side) is longer than the time (Δt1 + ΔtR) plus ΔtR {(Δt1 + ΔtR) <Δt2} The charging time constants of the capacitors C1 and C2 in the monitoring cancel timer 30 and the frequency monitoring timer 32 may be set.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment.
Various embodiments can be adopted. For example, in the above embodiment, the current detection resistor Rs is provided in the energization path on the battery 2 side.
Is provided so that an overcurrent flowing through the positive-polarity transistors Tr1 and Tr3 forming the H bridge can be detected. At the time of overcurrent detection, these transistors Tr1 and Tr3 are detected.
The above description has been made on the case of forcibly turning off at the same time to protect from an overcurrent, but as shown in FIG. 6, a resistor RSG for current detection is also provided on the GND side of the energizing path of the DC motor 10,
The voltage across both ends VRSG and the reference voltage VTG are judged by a comparator 52 as a detection means, and when VRSG ≧ VTG, an RS flip-flop 54 as a protection means is set to interrupt the energization from the RS flip-flop 54. When the negative polarity transistors Tr2 and Tr4 forming the H bridge are forcibly turned off by the signal, the wire harness connecting the terminal A or the terminal B and the DC motor 10 is short-circuited to the positive terminal side of the battery 2. It is also possible to protect the transistors Tr2 and Tr4 from overcurrent by detecting the overcurrent flowing in the transistors Tr2 and Tr4.

In this case, the RS flip-flop 2
The power-off signal Sc from the RS 8 and the RS flip-flop 5
If the energization interruption signal from 4 is input to the frequency monitoring cancellation timer 30 via the OR circuit 56, the terminal A
Alternatively, even if the wire harness connecting the terminal B and the DC motor 10 is short-circuited to GND or short-circuited to the positive electrode terminal side of the battery 2, the short-circuit abnormality is judged and each The holding operation of holding the transistors Tr1 to Tr4 in the off state can be performed, and the transistors Tr1 to Tr4 can be protected from overcurrent more reliably.

FIG. 6 shows the drive device of the above embodiment shown in FIG. 1 with the resistor RSG and the comparator 5 described above.
2, an RS flip-flop 54 and an OR circuit 56 are provided, and the configuration other than these parts is exactly the same as that of FIG. 1, and therefore detailed description thereof is omitted.

On the other hand, the resistor RSG for detecting an overcurrent is also provided on the GND side of the energizing path in this way, and the overcurrent protection can be satisfactorily executed when the wire harness is short-circuited to the positive terminal side of the battery 2. In such a case, the energization cutoff signals output from the comparators 26 and 54 as the protection means are turned off.
It is necessary to input to the frequency monitoring cancellation timer 30 via the R circuit 56. However, for example, when a driving device including such an overcurrent protection circuit is integrated into an IC, due to the influence of the terminal arrangement and the like,
It may be extremely difficult to form a wiring that connects the outputs from the RS flip-flops 28 and 54 and the OR circuit 56 provided near the frequency monitoring cancel timer 30.

Therefore, in such a case, for example, as shown in FIG.
As shown in FIG. 5, the outputs from the comparators 26 and 52 and the output from the pulse generation circuit 12 are wired to the vicinity of the frequency monitoring cancellation timer 30, respectively, and the OR circuit 56 and the RS are provided near the frequency monitoring cancellation timer 30. A flip-flop 60 is provided, the outputs from the comparators 26 and 52 (that is, the overcurrent detection signal) are input to the OR circuit 56, and the output of the OR circuit 56 is further input to the RS flip-flop 6.
The output from the pulse generation circuit 12 may be input to the reset terminal R of the RS flip-flop 60 to the set terminal S of 0, and the output of the RS flip-flop 60 may be input to the frequency monitoring cancellation timer 30. Good.

That is, even if the overcurrent protection circuit of this embodiment is configured as described above, the frequency monitoring cancel timer 30 can measure the operation time in a normal state, and therefore, the device shown in FIG. The same effect can be obtained. In this case, when the drive device including the overcurrent protection circuit is integrated into an IC, it is not necessary to wire the outputs from the RS flip-flops 28 and 54 to the vicinity of the frequency monitoring cancel timer 30.
Although it is necessary to separately provide the RS flip-flop 60, it becomes possible to easily realize an IC. It should be noted that such a circuit change for IC implementation is an example,
When actually configuring the driving device, it may be appropriately performed in consideration of the manufacturing cost, the size of the IC, and the like.

Further, in the above-described embodiment, the frequency monitoring cancel timer 30 and the frequency monitoring timer 32 use timer circuits for respectively clocking the cancellation time and the monitoring time by the charging circuits of the capacitors C1 and C2, respectively. However, as each of the timers 30 and 32, it is also possible to use a digital timer that counts a clock signal input from the outside in a predetermined cycle and measures the time from the count value.

Then, for example, the frequency monitoring cancellation timer 30
When a digital timer is realized by the digital timer, as shown in FIG.
Energization cutoff signal Sc output from the flip-flop 28
Pulse signal Sb periodically input from the pulse generation circuit 12 to the clock terminal CLK of the digital timer.
The digital timer, and the pulse signal S
The reset signal Se (high level) may be output from the output terminal Q when the count value of b reaches a predetermined value (for example, the value 4).

That is, when the frequency monitoring cancellation timer 30 is configured in this way, the frequency monitoring cancellation timer 30 outputs the energization cutoff signal Sc (High level) from the RS flip-flop 28 as shown in FIG. 8B. Each time it is cleared, the energization cutoff signal Sc from the RS flip-flop 28
Output is stopped, and the stop time is the pulse generation circuit 1
At a time point (shown in the drawing) when the predetermined number (for example, four) of the pulse signals Sb are output from 2, the high-level reset signal Se is output.

Therefore, as shown in FIG. 9, when the wire harness is short-circuited to GND, even if the short-circuited state is intermittently eliminated, the normal recovery time is the pulse generation. The pulse signal S output from the circuit 12
If the predetermined number of b (that is, the release time) is not reached,
The reset signal Se (High level) is not output from the output terminal Q, and the frequency monitoring timer 32 can continue the time count as in the above embodiment.

On the other hand, in the above embodiment, the case where the overcurrent protection circuit of the present invention is applied to the drive device of the DC motor 10 has been described, but the present invention turns on / off the switching elements such as transistors and thyristors. If it is a drive device that switches energization / de-energization of an electric load, for example,
The invention can be applied to a driving device that drives an actuator such as a DC motor or a solenoid, or a driving device for voltage such as a DC-DC converter.

Furthermore, in the above-described embodiment, in order to detect the overcurrent of the transistor, the resistor provided in the energizing path of the electric load (that is, the DC motor) is used to detect the current flowing through the transistor. However, some so-called power transistors used as switching elements for driving an electric load include a resistor for current detection and a temperature sensor for detecting heat generation due to passing current.
When performing overcurrent protection for such a transistor, it is not necessary to provide a current detection resistor in the energization path of the electric load, and the current detection function of the transistor can be used to detect the overcurrent.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a configuration of an entire drive device of a DC motor including an overcurrent protection circuit according to an embodiment.

FIG. 2 is a time chart showing the operation of the overcurrent protection circuit when a short circuit abnormality occurs.

FIG. 3 is a time chart showing the operation of the overcurrent protection circuit when the short circuit abnormality is intermittently eliminated.

FIG. 4 is a time chart showing the operation of the overcurrent protection circuit when an overcurrent is temporarily generated.

FIG. 5 is an explanatory diagram illustrating a relationship between time counts of a frequency monitoring cancel timer and a frequency monitoring timer.

FIG. 6 is a schematic configuration diagram showing a configuration of an overcurrent protection circuit in which a GND side overcurrent detection function is added to the circuit of FIG. 1.

7 is a schematic configuration diagram showing another configuration example of the overcurrent protection circuit shown in FIG.

FIG. 8 is an explanatory diagram when a digital timer is used as a frequency monitoring cancellation timer.

9 is a time chart explaining the operation of the overcurrent protection circuit when the digital timer of FIG. 8 is used.

[Explanation of symbols]

2 ... Battery 4 ... Ignition switch 10
... DC motor 12 ... Pulse generation circuit 14 ... Triangular wave generation circuit 1
6 ... PWM control circuit 21, 23 ... OR circuit 22, 24 ... NOR circuit 26 ... Comparator (detection means) 28 ... RS flip-flop (protection means) 30 ... Frequency monitoring cancellation timer (second timer means) 32 ... Frequency monitoring Timer (first timer means) 34 ...
OR circuit 36 ... RS flip-flop (holding means) 38 ... O
R circuit 40 ... Release signal input terminal 41 ... NOT circuit 52 ... Comparator (detection means) 54 ... RS flip-flop (protection means) 56 ... OR circuit 60 ... RS flip-flop

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H02P 3/08 H02P 3/08 A

Claims (3)

[Claims] 1. A detection means for detecting an overcurrent of a predetermined current value or more flowing in a switching element for connecting / disconnecting a current-carrying path of an electric load, and a predetermined protection time when the detection means detects the overcurrent. And a protection means for forcibly turning off the switching element, and a frequency with which the protection means turns off the switching element, and when the frequency exceeds a predetermined degree, the switching element is forcibly turned off, In an overcurrent protection circuit including a frequency monitoring unit that holds the off state, the frequency monitoring unit measures the elapsed time after that when the protection unit once turns off the switching element, and the elapsed time is When a preset monitoring time is reached, a first timer means for generating a holding command for holding the switching element in an off state, and the protection means Every time the command to forcibly turn off the switching element is released with the lapse of time, the elapsed time in the normal time until the overcurrent is detected by the detection means is measured, and the elapsed time in the normal time is measured. Second, when the time reaches a predetermined release time shorter than the time obtained by subtracting the protection time from the monitoring time, the first timer means is reset to stop the time counting by the first timer means.
And a holding means for turning off the switching element in response to a holding command from the first timer means and holding the off state, the overcurrent protection circuit. 2. An overcurrent protection circuit is provided in a drive device for duty-driving the electric load by turning on / off the switching element with a pulse width modulation signal, and the protection means is provided in the drive device. 2. The over-time release timing after the switching element is forcibly turned off is set based on a clock signal of a constant cycle used to generate the width modulation signal. Current protection circuit. 3. The overcurrent protection circuit includes, as the switching element, a pair of positive side switching elements provided respectively between the two terminals for feeding the electric load and the positive side of the DC power source, and the power feeding side. A pair of negative side switching elements respectively provided between the two terminals and the negative side of the DC power supply, and a current flowing through the electric load by a combination of the ON states of the pair of positive side and negative side switching elements. Provided in a drive device capable of switching the direction bidirectionally, the detection means, a positive electrode side detection means for detecting an overcurrent flowing in any of the pair of positive electrode side switching elements,
Negative electrode side detection means for detecting an overcurrent flowing in any one of the pair of negative electrode side switching elements, and the protection means comprises a pair of positive electrode sides when the positive current side detection means detects an overcurrent. A positive electrode side protection means forcibly turning off the switching element for the protection time, and a negative electrode forcibly turning off the pair of negative electrode side switching elements when the overcurrent is detected by the negative electrode side detection means. Side protection means, and in the frequency monitoring means, the first timer means,
At least one of the positive electrode side protection means and the negative electrode side protection means measures the elapsed time after the switching element is once turned off, and the second timer means is configured to release the positive side protection means and the positive side protection means after the switching element is forcibly turned off. The overcurrent protection circuit according to claim 1 or 2, wherein an elapsed time until an overcurrent is detected by any one of the negative electrode side protection means is measured.