JPH09307865A - Compressed image audio decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure an operation margin of a CPU by providing a reception buffer with respect to other packets than image data into a memory RAM of the CPU and providing a reception buffer for an image packet into a packet separator, and to omit a memory exclusively for a data buffer. SOLUTION: An image packet is fed to an exclusive reception buffer 27 and data are transferred via a decoder interface 24 on request of a video decoder 5. Furthermore, an audio packet reception buffer 134, an additional data packet reception buffer 135 or the like are provided in the inside of a RAM 13 in addition to a system decoding work area 131 or the like and packets other than the image are transferred to a packet reception buffer to each element via a bus interface 26. A CPU 11 reads transport stream packets stored in each reception buffer in the order of arrival according to a control program stored in a ROM 12 and conducts the processing to each element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention receives related data such as image, audio and character information compressed and packet-multiplexed by a digital compression encoding method such as MPEG.
The present invention relates to a device (compressed video / audio decoder device) for separating / decoding and outputting as a television signal, an audio signal and a character graphic signal, and is particularly suitable for use in a television receiver or an optical disk / magnetic tape player. The present invention relates to a compressed image / audio decoder device.

[0002]

2. Description of the Related Art In the fields of broadcasting and communication, it has become possible to perform data compression by compressing the redundancy of moving image signals and audio signals. As the image data compression method, a method of performing discrete cosine transform and motion compensation predictive coding such as MPEG standard is generally used. Also for audio signals, compression coding using frequency conversion and auditory characteristics is widely used.

According to the MPEG standard, the system layer for controlling the transmission and display of these coded elements, that is, additional data such as image, audio data and character data, is ITU-T Rec.H.222.0. | ISO / IEC13818-1: 1994
Information technology-Coding of moving pictures
and associated audio-Defined in Part1: Systems. By applying this, the above elements that share the content and time axis are multiplexed to form one program (program) as one unit for transmission and storage.
It is possible to multiplex these programs and transmit them on the same channel.

In the MPEG system, elements and programs are multiplexed in units of program stream (hereinafter abbreviated as PS) packet and transport stream (hereinafter abbreviated as TS) packet, respectively. Based on the standard, for example, from a PS packet reproduced from a storage medium or a TS packet transmitted from a broadcasting station, an image belonging to one program,
After extracting and separating voice and character data, distribute them to video, audio and character graphic decoders respectively.
A device that outputs to a monitor or a speaker can be configured. Such an apparatus is disclosed in, for example, Japanese Patent Application Laid-Open No. 7-170490.
No., published in Japanese Unexamined Patent Publication No. Although the device disclosed in this prior application targets the former PS packet,
An apparatus for processing program-multiplexed TS packets in the upper hierarchy based on this is shown in FIG. 5 as a general conventional example.

The device shown in FIG. 5 will be described below. The input to the device is a transmission medium such as cable television or satellite broadcasting,
Alternatively, it is a bit stream supplied from a recording medium such as an optical disk. The bit stream is MPEG T
Error correction code is added to S packet, and QAM and QPSK are added.
The transmission line modulation such as the modulation is performed, and the demodulation device 1 performs the demodulation and the error correction process, and outputs T as an output.
Get an S packet. The packet demultiplexer 2 extracts only desired packets from the program-multiplexed TS packets and sends them to the subsequent stage.

Here, the structure of the TS packet is shown in FIG. The content of the TS packet is classified into (a) of FIG. 6 or (b) of FIG. 6 depending on the type of information transmitted.

FIG. 6A shows a data format for transmitting additional data such as image data, voice data, characters, etc., which are elements of the program. A 188-byte TS packet is composed of a transport stream header (hereinafter, abbreviated as TS header) and a payload including the element.

[0008] The TS header always includes a packet ID (hereinafter abbreviated as PID) indicating the attribute of the TS packet, and time information for recovering the system clock used as a time base during element coding on the decoding side. Where is the program clock reference (hereinafter P
(Abbreviated as CR)).

The payload is a part of a packetized elementary stream (hereinafter abbreviated as PES) packet. The PES packet is a unit of element determined by each element and the format of the recording medium, and is a variable-length packet. This PES packet is
It is composed of data of each element and a PES header. The PES header includes a stream ID that describes the contents of the element, a PES packet length, and a time stamp that describes the time when the element should be displayed (hereinafter, PT).
(Abbreviated as S)) and the like. The unit of the element indicated by the PTS is called an access unit, and means, for example, one picture for an image and one frame for an audio.

On the other hand, FIG. 6B shows a data format for transmitting program-specific information (hereinafter abbreviated as PSI) which is information for system control.

[0011] The payload of the TS packet is a part of PSI described in the unit of section, and the section is a section header, PSI, and a cyclic redundancy code (CRC) which is an error detecting means. ) And. The section header represents the attribute and section length of the PSI that follows. PSI has a hierarchical structure,
Program information included in the bitstream data transmitted as TS (specifically, P of PMT described later)
Information required for system control, such as a program association table (hereinafter abbreviated as PAT) that describes IDs, and a program map table (hereinafter abbreviated as PMT) that represents the correspondence between elements and PIDs in each program. Is included. A packet including service information (hereinafter abbreviated as SI), which is information peculiar to a service such as program information, is also sent in the section format.

Here, the internal structure of the packet separation device 2 will be described. The multiplexed TS packet is supplied from the demodulation device 1, and the PID filter 22 extracts the PSI / SI data and the image, audio and additional data which are the constituent elements of the desired program by the PID identification. The PID of the packet to be extracted is supplied from the PID table 23. The PID table 23 is a CP
Plural PIs written from U11 via data bus
Holds D.

Each of the extracted packets is a packet reception buffer for each element provided in the data buffer 4, that is, an image packet reception buffer (V) 41.
A voice packet reception buffer (A) 42, an additional data packet reception buffer (T) 43, and a PSI / S
It is temporarily stored in the I-packet reception buffer (S) 44.

The accumulated image packet and audio packet are sent out via the decoder interfaces 24 and 25, respectively, in accordance with the requests from the video decoder 5 and the audio decoder 7. Additional data packet and P
Regarding the SI / SI packet, the information is expanded in another area in the data buffer 4 and accessed by the CPU 11 via the bus interface 26 for processing, or TS
After the CPU 11 makes access in the form of a packet or PES packet, information may be expanded by software and processed.

On the other hand, regarding the PCR packet, a PCR which is time information is extracted from the header, and the internal PCR is extracted.
The value of the counter 21 is compared. By supplying a control signal using this difference value to the clock generator 3,
A clock that follows the frequency of the system clock used on the transmission side can be restored. The generated clock becomes a basic clock signal for operating the video decoder 5 and the audio decoder 7.

The CPU 11 controls the system processing. C
On the data bus of the PU 11, a ROM 12 that mainly stores a processing program, a RAM 13 that is a work area for processing, and a user interface device 10 that receives an input from a user are arranged.

Inside the RAM 13, a work area 131 for system decoding for analyzing PSI / SI and a work area 133 for analyzing additional data such as character data.
And a system control work area 132 for controlling the entire decoder device. For example, the CPU 11 receives a channel switching command from the user via the user interface device 10, and PI of the packet to be extracted.
Set D. Next, the decode timing for synchronous reproduction is calculated, and an instruction is given to each decoder via the data bus. Such an operating procedure is performed by the control program R
It is stored in the OM 12.

The video decoder 5 is a decoding buffer 6
The audio decoder 7 also has a decoding buffer inside. Outputs from the decoders 5 and 7 are converted into analog signals by digital / analog converters (hereinafter abbreviated as DAC) 8 and 9 and supplied to a speaker and a monitor.

[0019]

The capacity of the packet receiving buffer provided in the data buffer 4 is 5 for each program by the MPEG system.
It is specified as 12 bytes or more. The reason why the data buffer 4 is provided is that its capacity is not fixed. That is, since the number of elements forming the program is arbitrary, if the maximum value of the assumed number of elements is N, the receiving side must prepare a 512 × N-byte packet reception buffer for this, and therefore the capacity In many cases, it is provided in the data buffer 4 with a sufficient margin. Since the data buffer 4 is a dedicated memory connected to the packet separation device 2, this increases the number of parts of the device and raises the price.

On the other hand, by providing the packet receiving buffers for all the elements in the RAM, which is the work area of the CPU, if the conventional dedicated data buffer is to be reduced, image packets having a high bit rate will be transferred to the data bus. Occupied ratio increases, CPU
We found a problem that interferes with the original processing.

The present invention has been made in view of the above points, and it is an object of the present invention to achieve both reduction of the dedicated memory and securing of the operation margin of the CPU, and cost reduction without deterioration of performance.

[0022]

In order to achieve the above object, according to the present invention, a packet containing image data is sent to a video decoder via a packet reception buffer having a capacity of 512 bytes as in the conventional case, and other data is transmitted. For a packet including, the receiving buffer is provided in the RAM which is the work area of the CPU, and the conventional dedicated data buffer is reduced.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a compressed video / audio decoder device according to the first embodiment of the present invention. The input to the apparatus of the first embodiment is a program-multiplexed and transmission-path-modulated MPEG TS packet supplied from a transmission medium such as cable television or satellite broadcasting, or a recording medium such as an optical disc.

In the demodulator 1, demodulation of transmission line modulation and error correction processing are performed, and a program-multiplexed TS packet is obtained as an output. This program multiplexed TS
The packet becomes an input to the packet separation device 2, and the PID
In the filter 22, PSI / SI based on PID identification
The data and the image, voice, and additional data that are the constituent elements of the desired program are extracted. The PID of the packet to be extracted is supplied from the PID table 23. The PID table 23 holds a plurality of PIDs written from the CPU 11 via the data bus.

Of the extracted packets, for the PCR packet, first, PCR which is time information is extracted from the header and compared with the value of the internal PCR counter 21. The clock generator 3 outputs the control signal using this difference value.
The system clock used on the transmitting side is recovered by supplying the signal to the transmitter. The generated clock becomes a basic clock signal for operating the video decoder 5 and the audio decoder 7.

The image packet is sent to a dedicated reception buffer (V) 27 (image packet reception buffer (V)) 27 having a capacity of 512 bytes or more, and data is transmitted via the decoder interface 24 in accordance with a request from the video decoder 5. To transfer. The format of the transferred image data depends on the specifications of the video decoder 5, and may be a format such as PES, elementary stream or picture. Since the capacity of the reception buffer (V) 27 is 512 bytes or more,
As long as it satisfies the MPEG system standard and the video decoder 5 reproduces at the same speed as the transmitting side, overflow /
Buffering is possible without causing underflow.

The video decoder 5 decodes the MPEG image data by using the video decoding buffer 6, and D
The AC 8 receives this decoded data output and converts it into an analog image signal.

Packets other than images are transferred to the packet reception buffer for each element provided in the RAM 13 via the bus interface 26.
In the RAM 13, a system decoding work area 131 for analyzing PSI / SI, an additional data decoding work area 133 for analyzing additional data such as character data, and a system control work area for controlling the entire decoder device. 132, and in addition to these, a voice packet reception buffer (A) 1 having a capacity of 512 bytes or more
34 and reception buffer (T) 13 for additional data packet
5, and a PSI / SI packet reception buffer (S) 13
6 are provided.

The CPU 11 reads the TS packets stored in the respective reception buffers in the order of arrival according to the control program stored in the ROM 12, and performs the process for each element.

Regarding the voice packet, the PES packet or the elementary stream is extracted from the payload and transmitted to the audio decoder 7 via the data bus. The audio decoder 7 decodes the MPEG audio data, and the DAC 9 in the subsequent stage receives the audio data output and converts it into an analog audio signal.

For PSI / SI packets, section data is read from the payload and analyzed, and PA
Data necessary for system control such as T and PMT is expanded as a table in the system control work area 132. The control program manages system information about the selected program using this table, adjusts the decoding timing that affects the quality of image / audio, and displays the program information as feedback to the user. Carry out. As a result, the user can enjoy the program in a state where the image / sound is not disturbed or shifted, and can operate the device with good usability by applying the service information.

Regarding the additional data packet such as character data, the additional data element is read from the payload, converted into a file format accessed by the application program using the data, and stored in the work area 133 in the RAM 13, or Performs processing such as transfer to dedicated hardware connected to the bus.

The processing performed by the CPU 11 is defined as an independent program execution procedure called a task, and is registered in an operating system (hereinafter abbreviated as OS) on which the CPU 11 operates. Which task should be executed is determined by the OS according to each defined priority and an event that sequentially occurs in the CPU 11, for example, a state that changes with the input of an interrupt signal or the passage of time. When execution switching is performed between a plurality of tasks on the OS in this manner, the time load due to the control being transferred to the OS is added as an overhead each time, so generally, compared to the case where each task is executed independently, CPU
The operation margin of 11 is reduced.

In the first embodiment, a packet containing voice and system data having a relatively low bit rate is CP
Captured in U11 memory and up to 15 according to MPEG standard
Image data packets that are allowed up to a bit rate of megabits / second are not sent to the data bus, so that the operation of the CPU 11 is not stressed for bus access. On the contrary, it is necessary to provide a reception buffer 27 dedicated to the image data packet inside the packet separation device 2. However, since this has a fixed memory with a capacity of 512 bytes, the increase in cost is large. Compared with connecting a dedicated memory device to the outside, it can be kept sufficiently low.

As described above, in the first embodiment,
A packet reception buffer for a packet having elements other than image data is provided inside the RAM used by the CPU as a main memory, and an image packet reception buffer is provided inside the packet separation device, so that it is dedicated to the conventional data buffer. The memory can be omitted, and at the same time, the operating margin of the CPU can be secured. Although the video decoder 5 and the audio decoder 7 are treated as separate elements for convenience here, the same effect can be obtained by using a video / audio decoder in which the both are integrated.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of a compressed image / sound data device according to the second embodiment of the present invention. In FIG. 2, the same parts as those in the first embodiment of FIG. , The description is omitted to avoid duplication.

The second embodiment differs from the first embodiment in that the audio decoder is omitted in the second embodiment and the CPU 11 decodes the audio data by software. is there.

In the RAM 13 of the second embodiment, P
A system decoding work area 131 for analyzing SI / SI, an additional decoding work area 133 for analyzing additional data such as character data, and a system control work area 132 for controlling the entire decoder device, Voice packet reception buffer (A) 134, additional data packet reception buffer (T) 135, and PSI / SI
A packet reception buffer (S) 136 and an audio decoding work area 137 are provided in addition to these. Further, a voice data rate buffer 14 is provided on the data bus. The ROM 12 stores an audio decoding program in addition to the processing program in the first embodiment.

When the CPU 11 reads out the packet data from the audio packet reception buffer (A) 134, it performs a decoding process according to the audio decoding program.
The audio decoding work area 137 is used for decoding and temporary storage of data. The decrypted data is P
It is sent to the rate buffer 14 at the reproduction time designated by the TS and is output to the DAC 9 in accordance with the audio reproduction rate.

In the second embodiment, the audio decoding is performed by software, thereby reducing the hardware audio decoder from the system and further reducing the cost. Also in such a configuration, as in the first embodiment, a packet reception buffer for packets having elements other than image data is provided inside the RAM used by the CPU as the main memory, and the image packet reception buffer is separated into packets. By providing it inside the device, it is possible to obtain the effect that the dedicated memory required for the conventional data buffer can be omitted and the operation margin of the CPU can be secured.

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 3 is a block diagram showing the configuration of a compressed image / sound data device according to the third embodiment of the present invention. In FIG. 3, those common to the first and second embodiments of FIGS. The same reference numerals are given and the description thereof is omitted to avoid duplication.

The third embodiment differs from the second embodiment in that in the third embodiment, a graphic display buffer 15 is provided on the data bus, and output data of the video decoder 5 and output of the graphic display buffer 15 are provided. A mixing circuit 16 for synthesizing and is provided, and a graphic display work area 138 is further provided inside the RAM 13. That is, although there are character data such as subtitles in addition to images and sounds as the constituent elements of the program, in the third embodiment, the pixel expansion for displaying the character data on the screen is performed by software. .

The CPU 11 reads the character data of the element from the additional data packet reception buffer (T) 135, obtains pixel data from a correspondence table called a bitmap table, and expands the pixel data in the graphic display work area 138. In addition to the character data, graphic data indicating the shape of the graphic can be considered. In this case, the graphic data is developed in the graphic display work area 138 by calculation. The graphic data is temporarily displayed in the graphic display buffer 15
And is read in synchronization with the output timing from the video decoder 5. The mixing circuit 16 plays a role of enabling overlay display, and can perform replacement, addition averaging, or the like in units of pixels or in units of certain display portions.
The output from the mixing circuit 16 is converted into an analog signal by the DAC 8 and sent to a display device such as a monitor.

As described above, in the third embodiment, the configuration is shown in which not only the voice but also the graphic data such as the character is expanded by the software, and the combined output with the image data is possible. Also in such a configuration, as in the first embodiment, a packet reception buffer for packets having elements other than image data is provided inside the RAM used by the CPU as the main memory, and the image packet reception buffer is separated into packets. By providing it inside the device, it is possible to obtain the effect that the dedicated memory required for the conventional data buffer can be omitted and the operation margin of the CPU can be secured.

Finally, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram showing the configuration of a compressed image / sound data device according to the fourth embodiment of the present invention. In FIG. 4, the same parts as those in the first embodiment of FIG. , The description is omitted to avoid duplication.

The fourth embodiment differs from the first embodiment in that the DTS (I) detection circuit 28 is provided inside the packet separation device 2 in the fourth embodiment.

DTS (I) means a DTS attached to an I picture that has been subjected to basic in-screen compression when an image is reproduced in MPEG. When switching channels or displaying images from the initial state, the first
In order to start from a picture, it is necessary to put an I picture as a reference for decoding in the video decoding buffer 6.

In the fourth embodiment, in order to realize this, the DTS (I) detection circuit 2 inside the packet separation device 2 is used.
At 8, the DTS (I) is extracted from the image data so that the CPU 11 can load it via the bus interface 26. The DTS (I) detection circuit 28 further issues an interrupt signal to the CPU 11,
It indicates that the data corresponding to (I) is input to the video decoder 5. CPU 11 receives this and receives DTS (I)
Is read and the time indicated by DTS (I) is set in a built-in timer or the like, and when the time arrives, a decoding start instruction is given to the video decoder 5. With the series of operations described above, decoding can be started with the I picture at the beginning, and it is possible to output an image without disturbance due to overflow / underflow in the video decoding buffer 6 from the first image. Become.

Also in the fourth embodiment having such a configuration, as in the first embodiment, a packet reception buffer having elements other than image data is provided inside the RAM used by the CPU as a main memory, and an image is displayed. By providing the packet receiving buffer inside the packet separating device, it is possible to obtain the effect that the dedicated memory required for the conventional data buffer can be omitted and the operation margin of the CPU can be secured. Although the fourth embodiment has been described here as a structure complementary to the first embodiment, the fourth embodiment can be applied to a configuration based on the second and third embodiments. Needless to say, in such a case as well, it is possible to output an image without disturbance due to overflow / underflow in the video decoding buffer 6 from the first image.

[0050]

As described above, according to the present invention, the CPU uses the packet reception buffer for packets having elements other than image data as the main memory.
By disposing the image packet reception buffer inside the AM and the packet separation device inside the packet separation device, the dedicated memory required for the conventional data buffer is omitted, and at the same time, C
The operation margin of the PU can be secured, so that the cost can be reduced without deteriorating the performance.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a compressed video / audio decoder device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a compressed image / audio decoder device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a compressed image / audio decoder device according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a compressed image / audio decoder device according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a compressed image / audio decoder device according to a conventional technique.

FIG. 6 is an explanatory diagram showing an internal structure of a packet.

[Explanation of symbols]

 1 Demodulator 2 Packet Separator 21 PCR Counter 22 PID Filter 23 PID Table 24 Decoder Interface (Decoder I / F) 26 Bus Interface (Bus I / F) 27 Image Packet Reception Buffer (V) 28 DTS (I) Detection Circuit 3 Clock Generator 5 Video Decoder 6 Video Decode Buffer 7 Audio Decoder 10 User Interface Device 11 CPU 12 ROM 13 RAM 131 System Decode Work Area 132 System Control Work Area 133 Additional Data Decode Work Area 134 Voice Packet Reception Buffer ( A) 135 Additional data packet reception buffer (T) 136 PSI / SI packet reception buffer (S) 137 Audio decoding work area 138 Work area for rough display 14 Rate buffer for audio data 15 Graphic display buffer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hironori Omi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd. Hitachi, Ltd. Multimedia Systems Development Division

Claims (6)

[Claims] 1. A bitstream in which a set of compression-encoded image data, audio data accompanying the image data, and system control data such as data identification information is packetized and a plurality of sets are multiplexed. An apparatus for receiving and outputting a set of an image signal and an audio signal, comprising: an image decoding unit for decoding the compression-encoded image data; and an audio decoding unit for decoding the compression-encoded audio data. A means for extracting an image packet containing image data belonging to a specific set from the bitstream; a means for extracting a packet belonging to the specific set not containing image data from the bitstream; And an image packet reception buffer that sequentially stores packets, and a first packet that sequentially stores packets that do not include the image data.
Of the memory and the first memory, the packets are sequentially read, the voice data is extracted from the packet containing the voice data and supplied to the voice decoding means, and the system control data is extracted from the packet containing the system control data and processed. And a processor for storing and further controlling the system of the device, a second memory used by the processor as means for processing and storing system control data, and data for executing a program for the processor to control the system of the device. And a third memory used as means for processing and accumulating data, and the first, second, and third memories are provided on the same memory device. apparatus. 2. A bitstream in which a set of compression-encoded image data and audio data accompanying the image data and system control data such as data identification information are packetized and a plurality of sets are multiplexed is received. A device for outputting a set of image signal and audio signal, the image decoding means for decoding the compressed and encoded image data, and an image packet including image data belonging to a certain set from the bit stream. Means for extracting a packet that does not include image data that belongs to the specific set from the bitstream, an image packet reception buffer that sequentially stores the image packets, and a packet that does not include the image data. First to accumulate sequentially
Of the memory and the first memory, the packets are sequentially read, the voice data is extracted from the packet containing the voice data and decoded, the system control data is extracted from the packet containing the system control data, and is processed and stored. A processor for performing system control of the device, a second memory used by the processor as means for decoding voice data and processing and storing system control data, and data for executing a program for the processor to perform system control of the device. And a third memory used as means for processing and accumulating data, and the first, second, and third memories are provided on the same memory device. apparatus. 3. A set of compression-encoded image data, a set of audio data accompanying the image data and graphic data such as character data, and system control data such as data identification information are packetized to form a plurality of sets. An apparatus for receiving a multiplexed bit stream and outputting a set of an image signal, an audio signal, and a graphic such as a character, the image decoding means for decoding the compression-encoded image data, and the compression unit. Audio decoding means for decoding the encoded audio data, a graphic display buffer for displaying the graphic such as the character, a mixing circuit for mixing the image data and the graphic such as the character, and A means for extracting an image packet containing image data belonging to a specific set; Means for extracting packets that do not include image data and belong to the group, an image packet reception buffer that sequentially stores the image packets, and a first buffer that sequentially stores packets that do not include the image data.
Of the memory and the first memory, the packets are sequentially read, the voice data is extracted from the packet containing the voice data and supplied to the voice decoding means, and the system control data is extracted from the packet containing the system control data and processed. A processor for storing and accumulating, extracting graphic data from a packet containing graphic data such as characters, processing and transferring the packet to the graphic display buffer, and further performing system control of the device; and a processor for processing graphic data and system control data. And a third memory used as a storage means, and a third memory used as a data processing and storage means for the processor to execute a program for system control of the apparatus. The second and third memories are provided on the same memory element. A compressed video / audio decoder device characterized by being provided. 4. A set of compression-encoded image data, a set of audio data accompanying the image data and graphic data such as character data, and system control data such as data identification information are packetized to form a plurality of sets. An apparatus for receiving a multiplexed bit stream and outputting a set of an image signal, an audio signal, and graphics such as characters, the image decoding means for decoding the compression-encoded image data, and the characters. A graphic display buffer for displaying a graphic such as a character, a mixing circuit for mixing the image data with a graphic such as the character, and means for extracting an image packet including image data belonging to a certain set from the bit stream And means for extracting from the bitstream a packet that belongs to the specific set and does not include image data, An image packet receiving buffer that sequentially stores image packets, and a first buffer that sequentially stores packets that do not include the image data.
Of the memory and the first memory, the packets are sequentially read out, the voice data is extracted from the packet containing the voice data and decoded, the system control data is extracted from the packet containing the system control data, processed and accumulated, and the characters are stored. Extract the graphic data from the packet containing the graphic data, process it and transfer it to the graphic display buffer,
Further, a processor for performing system control of the device, a second memory used by the processor as means for decoding voice data and processing and storing graphic data and system control data, and a processor for executing a program for system control of the device A third memory used as means for processing and accumulating data in order to achieve the above, and the first, second, and third memories are provided on the same memory element. Compressed video and audio decoder device. 5. The device according to claim 1, further comprising: a unit for extracting an image packet containing image data belonging to a specific set from the bitstream, and the specific unit for extracting the image packet from the bitstream. Means for extracting a packet that belongs to the group and does not include image data includes a circuit that compares a packet identifier indicating the attribute of each packet with an identifier indicating a specific packet group, and an identifier indicating a specific packet group. And a table that stores an identifier indicating a packet containing system control data, an interface circuit with the data bus of the processor, an interface circuit with the image decoding means, and a time stamp indicating a time reference as an initial value. A compressed video and audio decoder device including a self-running counter. 6. The time stamp extraction circuit according to claim 5, wherein the output of the image packet reception buffer is provided with a time stamp extraction circuit for extracting a time stamp indicating the decoding or display time of the image compressed in the screen. The output is connected to an interface circuit with the data bus of the processor, the time stamp can be acquired by the processor, and a means for giving the extraction timing of the time stamp to the processor is provided. Audio decoder device.