JPH09307540A - Multi-frame synchronizing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the number of latches in use form being increased and the prevent a scale of a synchronization circuit from being increased even when an increased length of a multi-frame synchronization pattern is received. SOLUTION: A data selector 4 inserts a state bit 106 outputted from a transmission multi-frame phase state bit counter 2 to each frame of serial data and sends the result externally. A pattern detection section 6 receiving the serial data detects a singular part in existence in a multi-frame synchronization pattern to detect a multi-frame synchronizing signal and to output a synchronization detection signal 120 to allow a reception multia-frame phase state bit counter 8 to load and shift state bits in this timing thereby expanding a received multi-frame phase state bit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiframe synchronization method in digital communication.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram showing a conventional multi-frame synchronization method.
Reference numeral 20 is a transmission frame number counter that outputs a frame number 140 at an internal frame timing based on the clock 104. Reference numeral 22 is a multi-frame synchronization pattern 200 that is expanded to a selector input and the transmission frame number counter 20 outputs the frame number 140.
The sync pattern selector 4 selects and outputs the frame sync bit 142 based on the frame sync bit 142. The sync pattern selector 4 inserts the frame sync bit 142 output by the sync pattern selector 22 into the serial data 102 into the frame at a predetermined timing. It is a data selector that creates transmission serial data 144 to be output to. Reference numeral 24 denotes an S / which creates a reception synchronization bit pattern candidate 146 by latching only one frame synchronization bit for one multiframe from a bit string obtained by performing serial / parallel conversion while separating transmission serial data 144 input from the opposite device for each frame. The P conversion unit 26 is a pattern comparison unit that compares the reception synchronization bit pattern candidates 146 created by the S / P conversion unit 24 with the frame synchronization pattern. 28 is the pattern comparison unit 2
When "0" is loaded and cleared by the pattern coincidence detection timing pulse 148 output when the frame synchronization pattern is coincidentally detected in 6, the number of received frames is counted for each frame, and the count value is 1 A reception frame number counter that outputs a multi-frame timing pulse 150 when a predetermined value forming a multi-frame is reached, 10 is a pattern match detection timing pulse 148 output by the pattern comparison unit 26 and a multi-frame output by the reception frame number counter 28. It is a synchronization protection circuit that performs synchronization protection processing by the frame timing pulse 150.

Next, the operation will be described. The sender operates as follows. The synchronization pattern selector 22 selects one frame synchronization bit from the multi-frame synchronization pattern 200 one by one according to the frame number 140 output from the transmission frame number counter 20, and sequentially outputs the selected frame synchronization bit 142 as a serial output to the data selector 4. Send out. The data selector 4 outputs the sync pattern selector 2 to the serial data 102 to be output to the outside.
The frame synchronization bit 142 output by 2 is inserted at a predetermined timing for each frame to create transmission serial data 144 and output to the outside. The receiving side operates as follows. Upon receiving the transmission serial data 144 from the outside, the S / P conversion unit 24 rearranges the transmission serial data 144 in parallel at intervals of each frame to create a reception synchronization bit pattern candidate 146 and outputs it to the pattern comparison unit 26. The pattern comparison unit 26 compares the input reception synchronization bit pattern candidate 146 and the multi-frame synchronization pattern to determine whether they match, and outputs a pattern matching detection timing pulse 148 when a match is detected. When the pattern match detection timing pulse 148 is input to the reception frame number counter 28, "0" is loaded and cleared. After that, the frame pulse is counted, and when the count value reaches a predetermined value forming one multiframe, the multiframe is counted. Timing pulse 150
Is output. This multi-frame timing pulse 15
0 and the pattern matching detection timing pulse 148 output from the pattern comparison unit 26 are input to the synchronization protection circuit 10, and the synchronization protection circuit 10 compares the pattern matching detection timing pulse 148 and the multi-frame timing pulse 150 to forward protection. And provide rear protection.
The forward protection does not immediately become out of synchronization due to a single frame sync pattern mismatch, but is put into the out-of-sync state for the first time several times in succession, so that the synchronization error is accidentally out of sync due to a code error in the transmission path. This is the function to prevent The backward protection prevents false synchronization in the process of returning from the out-of-frame synchronization state to the synchronization state, and when the frame synchronization circuit is in the hunting state, a bit change occurs in the frame synchronization pattern due to a code error in the transmission line. This is a function of preventing the hunting state from returning to the hunting state again when the situation occurs.

[0004]

Since the conventional multi-frame synchronization method is configured as described above, there is a problem that the circuit scale becomes large when the pattern length of the multi-frame synchronization pattern becomes long. For example, I
TU-T Recommendation X. Taking the frame format of 50 as an example, since one multiframe is composed of 20 frames, the pattern length of the multiframe synchronization pattern is 20 bits. Therefore, a 20-to-1 selector and a 5-bit latch for counting the transmission frame number are required to selectively output the multi-frame synchronization pattern to the transmission side, and a 20-bit latch for holding the multi-frame synchronization pattern on the reception side, A 5-bit latch is required to form a 5-bit counter that counts the received frame number. That is, the conventional multi-frame synchronization method has a problem that a total of 30 bits of latches and 20: 1 selectors are required on the transmitting side and the receiving side. The present invention has been made to solve the above problems, and an object of the present invention is to obtain a multi-frame synchronization method that does not increase the circuit scale even if the pattern length of the multi-frame synchronization pattern becomes long.

[0005]

A multi-frame synchronization method according to the present invention is a method in which one multi-frame is composed of a plurality of frames and multi-frame synchronization of serial data transmitted and received in multi-frame units is achieved. That is, a predetermined bit among the status bits representing the phase status of the frames forming the multi-frame is used as the multi-frame synchronization bit.

In the multi-frame synchronization method according to the second aspect of the present invention, one multi-frame is composed of m frames (m is an integer of 2 or more), and each frame has an n-bit status bit for identifying each other. Allocation (n is a natural number determined by m), a predetermined bit of the status bits is used as a multi-frame synchronization bit, and the predetermined bit among the n number of status bits is set to be the same as the multi-frame synchronization bit. A multi-frame phase state bit for transitioning the state bits is generated, and the multi-frame phase state bit is used for multi-frame synchronization.

According to the third aspect of the present invention, there is provided a transmitting side with a transmitting multiframe phase status bit counter and a data selector, and a receiving side with a pattern detecting section and a receiving multiframe phase status bit counter. On the transmitting side, the transmit multi-frame phase status bit counter expands the transmit multi-frame phase status bit and outputs the status bit to the data selector, and the data selector inserts the status bit into the serial data for each frame and transmits the serial data. Generate data and send it to the outside. On the receiving side, the pattern detection unit that received the transmission serial data detects the unique portion existing in the multi-frame synchronization pattern, detects the multi-frame temporary synchronization, and outputs the temporary synchronization detection signal. The bit counter expands the received multi-frame phase status bit by loading and transitioning the status bit at the timing of the temporary synchronization detection signal.

A multi-frame synchronization method according to a fourth aspect of the present invention is a multi-frame synchronization method in which one frame is composed of a plurality of frames and the multi-frame synchronization of serial data transmitted / received in units of multi-frames is performed. A pattern detector, a received frame number counter, a sync pattern selector, and a sync protection circuit are provided on the side. The pattern detection unit detects a special pattern of the synchronization pattern from the transmission serial data, loads the received frame number counter and uses the multi-frame phase only for temporary pull-in, and after the temporary pull-in is established, the received frame number counter detects the frame phase. Take charge. The receive frame number counter outputs the temporary pull-in frame number based on the frame pulse, and the sync pattern selector outputs the temporary pull-in multi-frame sync pattern based on this frame number. Output bits.
The sync protection circuit performs a sync protection process using the multi-frame sync detection bit.

According to a fifth aspect of the multiframe synchronization method of the present invention, a transmission side is provided with a transmission multiframe phase status bit counter and a data selector, and a reception side is provided with a pattern detecting section, a reception multiframe phase status bit counter, and synchronization. Provide a protection circuit. On the transmission side, the transmission multi-frame phase status bit is expanded in the transmission multi-frame phase status bit counter, and one of the status bits (bit assigned in the same sequence as the synchronization pattern) is output to the data selector. Inserts a status bit into the serial data for each frame to generate transmission serial data and sends it to the outside.
On the receiving side, the pattern detection unit that has received the transmission serial data detects a unique portion existing in the multi-frame synchronization pattern to detect multi-frame temporary synchronization and output a temporary synchronization detection signal. The reception multi-frame phase status bit counter expands the reception multi-frame phase status bit by loading the status bit at the timing of the provisional synchronization detection signal and transitioning one bit in the status bit in the same sequence as the synchronization pattern. A synchronization pattern detection pulse is output when a predetermined number of times (the number of multi-frames) determined for establishing multi-frame synchronization is reached while comparing 1 bit in the status bit with the transmission serial data. The sync protection circuit performs a sync protection process with this sync pattern detection pulse.

According to a sixth aspect of the multiframe synchronization method of the present invention, a transmission multiframe phase status bit counter and a data selector are provided on the transmission side, and a pattern detection section, a transmission / reception multiframe phase difference comparison section and a phase difference are provided on the reception side. A delay unit and a sync protection circuit are provided. On the sending side,
The transmit multi-frame phase status bit is expanded in the transmit multi-frame phase status bit counter and the status bit is output to the data selector. The data selector inserts one bit of the status bit into the serial data for each frame and transmits the serial data. Generate data and send it to the outside. On the receiving side, the pattern detection unit that has received the transmission serial data detects a unique portion existing in the multi-frame synchronization pattern to detect multi-frame temporary synchronization and output a temporary synchronization detection signal. The transmission / reception multi-frame phase difference comparison unit compares the phase of the temporary synchronization detection signal with the phase of the transmission multi-frame to calculate the phase difference between the transmission multi-frame and the reception multi-frame and outputs the transmission / reception multi-frame phase difference signal. . The phase difference delay unit delays the transmission serial data by the transmission / reception multi-frame phase difference signal and outputs the delayed serial data. The synchronization protection circuit performs synchronization protection processing by monitoring this delayed serial data.

According to a seventh aspect of the multiframe synchronization method of the present invention, a pattern detecting section, a reception multiframe phase status bit counter, a memory, and a frame phase detecting circuit are provided on the receiving side. The pattern detection unit that receives the transmission serial data detects the unique portion existing in the multi-frame synchronization pattern to detect the multi-frame temporary synchronization and output the temporary synchronization detection signal. The reception multi-frame phase status bit counter outputs and stores the reception multi-frame phase status bit by loading and transitioning the status bit at the timing of the temporary synchronization detection signal. The frame phase detection circuit detects the phase of the received frame by comparing the transmitted serial data with the received multi-frame phase status bit stored in the memory.

According to an eighth aspect of the multi-frame synchronization method of the present invention, the receiving side is provided with a pattern detection section, a reception multi-frame phase status bit counter, a memory, and a synchronization protection circuit. The pattern detection unit that has received the transmission serial data detects the unique portion existing in the multi-frame synchronization pattern, detects the multi-frame temporary synchronization, and outputs the temporary synchronization detection signal. The reception multi-frame phase status bit counter outputs and stores the reception multi-frame phase status bit by loading and transitioning the status bit at the timing of the temporary synchronization detection signal. The synchronization protection circuit compares the transmission serial data with the received multi-frame phase state bit stored in the memory while reading and writing the synchronization state from the memory to perform the synchronization protection processing.

According to a ninth aspect of the multiframe synchronization method of the present invention, a transmission side is provided with a transmission multiframe phase status bit counter and a data selector, and a reception side is provided with a pattern detection section, a transmission / reception multiframe phase difference comparison section, and a phase difference. A delay unit, a memory, and a synchronization protection circuit are provided. On the transmission side, the transmission multi-frame phase status bit is expanded in the transmission multi-frame phase status bit counter and the status bit is output to the data selector. The data selector inserts the status bit into the serial data for each frame and transmits the serial data. Generate data and send it to the outside. On the receiving side, the pattern detection unit that has received the transmission serial data detects a unique portion existing in the multi-frame synchronization pattern to detect multi-frame temporary synchronization and output a temporary synchronization detection signal. The transmission / reception multi-frame phase difference comparison unit compares the phase of the temporary synchronization detection signal with the phase of the transmission multi-frame to calculate the phase difference between the transmission multi-frame and the reception multi-frame and outputs the transmission / reception multi-frame phase difference signal. To do. The phase difference delay unit delays the transmission serial data by the transmission / reception multi-frame phase difference signal, outputs the delayed serial data, and stores it in the memory. The synchronization protection circuit performs synchronization protection processing by monitoring the delayed serial data stored in the memory.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1. FIG. 1 is a block configuration diagram for realizing a multi-frame synchronization method according to a first embodiment of the present invention. In FIG. 1, reference numeral 2 denotes a multi-frame phase status bit composed of a plurality of status bits for identifying the multi-frame phase of a transmission frame. The transmission multi-frame phase state bit counter which develops and outputs one of them as the frame bit 106 at the timing of the clock 104 is inserted into the transmission serial data 102 by 4 and the frame bit 106 output by the transmission multi-frame phase state bit counter 2. And a data selector for generating the transmission serial data 108 to be output to the outside. Reference numeral 6 constantly monitors a specific bit pattern of a plurality of bits forming a frame bit in the received transmission serial data 108, and outputs a sync detection signal 120 when pattern matching, that is, multi-frame synchronization is detected. , 8 are reception multi-frame phase status bit counters that expand the reception multi-frame phase status bits used for identifying the multi-frame phase of the reception frame based on the synchronization detection signal 120 output from the pattern detection unit 6.

Next, the operation will be described. In the first embodiment, when one multi-frame is composed of m frames (m is an integer of 2 or more), n bits of status bits are assigned to each frame in order to identify the m frames from each other. (N is a constant of natural number determined by m,
For example, if m = 20, then n = 5). Then, a predetermined bit among the n status bits is used as the multi-frame synchronization bit itself, and the m number of status bits are transited in the same manner as the multi-frame synchronization bit (the predetermined bit is one bit or a plurality of bits, but The number of common bits depends on how many multi-frame sync bits are assigned to one frame). What realizes this is the transmission multi-frame phase status bit, which is expanded in the transmission multi-frame phase status bit counter 2. By providing the transmission multi-frame phase status bit counter 2, the transmission frame number counter 20 and the synchronization pattern selector 22 of the conventional example shown in FIG. 10 are provided.
Becomes unnecessary. That is, the transmission multi-frame phase status bit counter 2 shown in FIG. 1 requires the same number of latches as the transmission frame number counter 20 of the conventional example shown in FIG. 10, but the synchronization pattern selector 22 becomes unnecessary. When one multi-frame is composed of 20 frames, the synchronization pattern selector 22 of 20: 1 is required, so that the synchronization pattern selector 22 becomes unnecessary, and the effect of reducing the hardware amount is large.

On the other hand, on the receiving side, a peculiar portion existing in a multiframe synchronization pattern in which m bits of multiframe synchronization bits are arranged, for example, four "0" s "00" are consecutive.
The multi-frame synchronization is detected by detecting "00" or the like by the pattern detection unit 6. When the pattern detection unit 6 detects the multi-frame temporary synchronization, it outputs a temporary synchronization detection signal to the reception multi-frame phase status bit counter 8. The reception multi-frame phase status bit counter 8 that has received the temporary sync detection signal loads the status bit corresponding to the frame number of the timing next to the temporary sync detection signal reception timing, and thereafter increments the frame number from the multi-frame phase status bit. (However, the first frame is next to the maximum number of frames) The state bit that transits is selected and loaded. As described above, the receiving side does not need the pattern comparing section 26 that requires the m-bit latch and the m-to-m comparator shown in FIG. 10, and as shown in FIG. n
Bit reception multi-frame phase status bit counter 8
Since it is composed of, the number of latches used is n + 2 bits. For example, when m = 20, since n = 5, m
-(N + 2) = 20- (5 + 2) = 13, that is, 13
The number of bits of latches and the m-to-m comparator can be reduced.

Although the first embodiment has been described above by dividing it into the transmitting side and the receiving side, the number of reductions of the used latches for both the transmission and the reception according to the first embodiment with respect to the conventional example is m.
-(N + 2). For example, when m = 20, n = 5
Therefore, m− (n + 2) = 20− (5 + 2) = 13
Therefore, it is possible to reduce latches for 13 bits, 20: 1 selectors and 20: 1 comparators.

Next, the first embodiment will be described using a concrete example. ITU-T Recommendation X.1 where one multi-frame is composed of 20 frames. Taking the frame format of 50 as an example, 5 is used to identify the individual state of 20 frames.
Since we need bits, we introduce a 5 bit wide status bit. The multi-frame phase state bit is a transition of this state bit with the phase of the frame. FIG. 2 shows an example of multi-frame phase status bits. In FIG. 2, the frame numbers (frame N
o. ), Frame bits (Fbit), and status bits (F [4..0]) are shown respectively. The frame numbers increase in ascending order of 1, 2, 3, ..., When the frame number reaches 20, the frame number returns to 1. Frame bit (Fb
It) sequence "A11010010000101011
10 "is ITU-T Recommendation X.10. It is a multi-frame synchronization pattern defined by 50 ("A" is an alarm bit and takes a value of "1" or "0" depending on the synchronization state). In the first embodiment, the F4 bit of the status bits (F [4 ... 0]) is set so that the transition pattern of the status bits becomes the same as the multi-frame synchronization pattern.
That is, when the F4 bits are arranged so as to correspond to the frame number, "1110100100001010111"
0 ”, which is the same as the multi-frame synchronization pattern. In the first embodiment, the multi-frame phase status bit shown in FIG. 2 is held in the transmission multi-frame phase status bit counter 2 shown in FIG. The transmission multi-frame phase status bit counter 2 has status bits (F [4 ..
0]) is output as the frame bit 106. The frame bit 106 is inserted into the transmission serial data 102 by the data selector 4 at intervals of each frame, and the transmission serial data 108 is generated and sent to the outside.

The operation on the transmission side has been described above. On the reception side, the F4 bit having the same pattern as the multi-frame synchronization pattern is included in the status bits (F [4..0]) forming the transmission serial data 108 to be received. By performing the process of interest, the number of latches used for the synchronization process is reduced. Explaining in a specific example, a status bit (F [4..0]) is inserted at the beginning of each frame constituting the received transmission serial data 108, and when the F4 bits of this status bit are arranged in the order of reception. "1110
1001000010101110 ". In this bit string, there is only one part where four "0" s form "0000" consecutively (there is no other "0000" part). In the first embodiment, attention is paid to a portion where four "0" s of F4 bits form "0000" in succession, and the pattern detection unit 6 detects this and establishes multi-frame synchronization. . As will be described later, the pattern detection unit 6 can detect the multi-frame synchronization only by using the latch for 2 bits. Sync detection signal 12 output when the pattern detection unit 6 detects multi-frame synchronization
0 is input to the reception multi-frame phase status bit counter 8. As shown in FIG. 2, the portion where four "0" s of the F4 bit form "0000" in succession corresponds to the frame numbers 9 to 12, so the reception multi-frame phase status bit counter 8 is synchronized. At the timing when the detection signal 120 is received, the status bit (F [4..0]) corresponding to the frame number 13, that is, "10111" is loaded. Thereafter, the reception multi-frame phase status bit counter 8 loads the status bit corresponding to the frame number for each frame pulse. [Frame number, status bit F [4. . 0]], from the timing of receiving the synchronization detection signal 120, [13, “1011
1 "] [14," 00110 "] [15," 1011
0 ”] ... [20,“ 01110 ”] [1,“ 110
10 ”] [2,“ 10010 ”] ... Receive multi-frame phase status bit counter 8
Outputs the multi-frame timing pulse 124 when the frame state transition is repeated and multi-frame synchronization is established (the synchronization patterns of all frames match).

In the first embodiment, it is searched for that the synchronization pattern bit in the bit stream extracted at the reception frame timing becomes "0" four times in succession, but the coincidence "0" is counted four times in succession. Requires 2 bits. Next, details of the pattern detection unit 6 will be described with reference to FIG. In FIG. 3, reference numeral 62 is a binary counter that counts the number of bits that form a bit stream, and 63 is a number that latches a specific bit (“0”, hereinafter, referred to as a counter load pulse) that forms a specific bit string (for example, “0000”). 1 latch circuit, 64 is a second latch circuit that latches the carry 110 output from the binary counter 62, 65 is a control circuit that controls the first latch circuit 63 and the second latch circuit 64, and 66 is the first latch circuit 6
3 is an output of the third latch circuit 64 and an output 118 of the second latch circuit 64 are compared to perform a synchronization determination circuit.

Next, the operation will be described. When the transmission serial data 108 is input and the counter load pulse is latched by the first latch circuit 63, the binary counter 62 sets the number of counter load pulses to be counted as an initial value (for example, 4) and starts counting. The carry 110 is output when the count value reaches the initial value. The carry 110 is latched by the second latch circuit 64. The output 116 of the first latch circuit 63 and the output 118 of the second latch circuit 64 are input to the synchronization determination circuit 66. In the synchronization determination circuit 66, the counter load pulse is latched in the first latch circuit 63, and
When the carry 110 output from the binary counter 62 is latched in the latch circuit 64, the synchronization detection signal 12
Outputs 0.

In the first embodiment, a multi-frame synchronizing circuit, which is conventionally composed of an S / P converting section 24, a pattern comparing section 26 and a received frame number counter 28 as shown in FIG. 10, is shown in FIG. As shown in the figure, the pattern detector 6 and the reception multi-frame phase status bit counter 8 are used, so that the number of latches used on the reception side can be reduced. For example, one multiframe consists of ITU-T recommendation X.20. In the frame format of 50, the pattern comparison unit 26 is conventionally used.
20-bit latch is required for the received frame number counter 28 and 5-bit latch is used for the received frame number counter 28. All that is required is to use a 7-bit latch, which is 5 bits for 8. Therefore, 20 + 5-7 = 18, that is, 18 bits of latches can be reduced as compared with the conventional case.

The specific example of the first embodiment has been described above by dividing it into the transmitting side and the receiving side. However, the reduction number of the used latches for both transmitting and receiving according to the first embodiment is, for example, 20 for one multi-frame. ITU-T Recommendation X.1 consisting of frames. In the case of the frame format defined in 50,
It is possible to reduce the number of 18-bit latches, 20: 1 selectors, and 20/20 comparators described above. The number of latches used is reduced by PLD (programmable
Realizing a synchronous circuit using a logic device is very advantageous because it leads to downsizing of the circuit.

Embodiment 2 FIG. FIG. 4 is a block configuration diagram for realizing the multi-frame synchronization method according to the second embodiment of the present invention. In the figure, 6 is a specific bit pattern of a plurality of bits constituting a frame bit in the received transmission serial data 108. Is constantly monitored, and a pattern detection unit that outputs a sync detection signal 120 when pattern matching, that is, multi-frame synchronization is detected, and 9 receives a synchronization detection signal 120 output from the pattern detection unit 6 and thereafter multi-frame Received frame number counter that controls the phase and outputs the frame synchronization bit 126, 1
2 is a sync pattern selector which latches the frame sync bit 126 output from the received frame number counter 9 and outputs a multiframe sync bit 128 when it matches the multiframe sync pattern 200. 10 is a multiframe output from the sync pattern selector 12. This is a synchronization protection circuit that constantly compares the synchronization bit 128 and the transmission serial data 108 to perform forward protection processing and backward protection processing.

The pattern detecting section 6 has been described in detail with reference to FIG. 3, but is characterized in that a small-scale circuit including two latches and a peripheral circuit can detect the coincidence of the synchronization bit patterns. However, the concept of synchronization protection is not introduced in the pattern detection unit 6. There are two types of synchronization protection: forward protection and backward protection. The forward protection does not immediately become out of synchronization due to a single multi-frame synchronization pattern mismatch at the time of synchronization pull-in. This is a function to prevent the synchronization from being lost. The backward protection is not to establish the synchronization immediately by the single multi-frame synchronization pattern match in the process of returning from the multi-frame out-of-sync state to the synchronization state, but to establish the synchronization state only after several consecutive times. This function prevents missynchronization and also prevents the hunting state from returning to the hunting state when a bit change occurs in the multi-frame synchronization pattern due to a code error in the transmission path. The second embodiment takes advantage of the feature that the small-scale circuit of the pattern detection unit 6 can detect the coincidence of the synchronization bit patterns.
It also provides synchronization protection.

Next, the operation will be described. ITU-T Recommendation X.1 where one multi-frame is composed of 20 frames. 5
Taking the frame format of 0 as an example, the multi-frame synchronization pattern is “A110100100001010.
1110 "(" A "is an alarm bit and takes a value of" 1 "or" 0 "depending on the synchronization state). In this multi-frame synchronization pattern, there is only one part where four "0" s form "0000" (hereinafter referred to as a specific pattern), and no other specific pattern exists. The multi-frame synchronization pattern is separated into individual bits, inserted as frame bits at the beginning of each frame, and input to the pattern detection unit 6 as the transmission serial data 108. When the pattern detection unit 6 detects a specific pattern from the input transmission serial data 108, it outputs a synchronization detection signal 120 to the reception frame number counter 9. Once the reception frame number counter 9 receives the synchronization detection signal 120, it controls the multi-frame phase by itself, and the synchronization detection signal 120 output by the pattern detection unit 6
Are ignored until out of sync. As described above, in the second embodiment, the pattern detection unit 6 is used only for temporary pull-in of the multi-frame phase at the pull-in of synchronization. The reception frame number counter 9, which is now in charge of the multi-frame phase, outputs the frame synchronization bit 126 based on the frame pulse. This frame synchronization bit 126 is input to and latched by the synchronization pattern selector 12, and the synchronization pattern selector 12 determines that the pattern formed by the row of the latched frame synchronization bits 126 and the multiframe synchronization pattern match each other. Is output. The synchronization protection circuit 10 performs synchronization protection processing while comparing the multi-frame synchronization bit 128 and the transmission serial data 108.

As described above, according to the multi-frame synchronization method according to the second embodiment, the pattern detection unit 6 is used only for the temporary acquisition of the multi-frame phase at the time of synchronous acquisition, and after the temporary acquisition is established, the received frame is received. The number counter 9 outputs the frame synchronization bit 126, the synchronization pattern selector 12 establishes multi-frame synchronization, and after the multi-frame synchronization is established, the synchronization protection circuit 10
Is configured to perform the synchronization protection processing while comparing the multi-frame synchronization bit 128 and the transmission serial data 108, the feature of the pattern detection unit 6 that can detect the coincidence of the synchronization bit pattern with a small-scale circuit is utilized. , It becomes possible to realize synchronization protection.

Embodiment 3. FIG. 5 is a block configuration diagram for realizing a multi-frame synchronization method according to a third embodiment of the present invention. In the figure, a transmission multi-frame phase status bit counter 2, a data selector 4, a pattern detection unit 6, and a reception multi-frame phase are shown. The state bit counter 8 is the same as that of the first embodiment shown in FIG. 1, and therefore its explanation is omitted. Reference numeral 10 is a synchronization protection circuit for performing synchronization protection processing by the pattern matching detection timing pulse 122, the multiframe timing pulse 124 and the received transmission serial data 108 output from the reception multiframe phase status bit counter 8.

The third embodiment is a development of the second embodiment shown in FIG. 4, and includes a reception frame number counter 9 and a synchronization pattern selector 12 shown in FIG.
The number of latches used is reduced by using the reception multi-frame phase status bit counter 8 of the first embodiment shown in FIG. Corresponding to the reception side using the reception multi-frame phase status bit counter 8, the transmission side also uses the transmission multi-frame phase status bit counter 2. Since the transmission multi-frame phase status bit counter 2 and the reception multi-frame phase status bit counter 8 have been described in detail in the section of the first embodiment, the description thereof will be omitted here.

Next, the operation will be described. Transmission multi-frame phase status bit counter 2, data selector 4,
The operations of the pattern detection unit 6 and the reception multi-frame phase status bit counter 8 have been described in detail in the section of the first embodiment, and therefore a brief description will be given here while avoiding repetition. IT in which one multiframe consists of 20 frames
UT Recommendation X. Taking the frame format of 50 as an example, the multiframe phase state bits shown in FIG. 2 are also used in the third embodiment. Also in the third embodiment, the multi-frame phase status bit shown in FIG. 2 is held in the transmission multi-frame phase status bit counter 2 shown in FIG. The transmission multi-frame phase status bit counter 2 outputs status bits (F [4..0]) as frame bits 106 in the order of frame numbers at the timing of the clock 104. The frame bit 106 is inserted into the serial data 102 by the data selector 4 at intervals of each frame to generate the transmission serial data 108, which is sent to the outside.

On the receiving side, the pattern detection unit 6 converts the received transmission serial data 108 into an F4 bit having the same pattern as the multi-frame synchronization pattern in the status bits (F [4..0]) forming frame bits. Multi-frame synchronization is detected by performing the process of interest. When the pattern detection unit 6 detects multi-frame synchronization, it outputs a synchronization detection signal 120, and the synchronization detection signal 1
20 is input to the reception multi-frame phase status bit counter 8. The reception multi-frame phase status bit counter 8 outputs the pattern match timing pulse 122 when receiving the sync detection signal 120, and outputs the multi frame timing pulse 124 when the pattern match reaches a predetermined number of times determined to establish the multi frame synchronization. Output. The pattern matching timing pulse 122 and the multi-frame timing pulse 124 are input to the synchronization protection circuit 10, and the synchronization protection circuit 10 performs forward protection processing and backward protection processing by comparing these two pulses. The front protection process and the rear protection process have been described in detail in the section of the second embodiment, and therefore the description thereof will be omitted here.

In the third embodiment, instead of the reception frame number counter 9 and the synchronization pattern selector 12 of the second embodiment shown in FIG. 4, the reception multi-frame phase status bit counter of the first embodiment shown in FIG. Since it is configured to use eight, the number of latches used can be reduced. For example, one multiframe consists of ITU-T recommendation X.20. In the frame format of 50, a 20-bit latch is required to form the synchronization pattern selector 12, but the reception multi-frame phase status bit counter 8 can be realized by a 5-bit latch, so 20-5 = 15 bits. The latch of can be reduced. Reducing the number of latches used is very advantageous when realizing a synchronous circuit using a PLD, because it leads to downsizing of the circuit.

Embodiment 4 FIG. 6 is a block configuration diagram for realizing a multi-frame synchronization method according to a fourth embodiment of the present invention. In the figure, a transmission multi-frame phase status bit counter 2, a data selector 4, and a pattern detection unit 6 are shown in FIG. The same as that of the first embodiment and the synchronization protection circuit 10 is the same as that of the second embodiment shown in FIG. 4, and therefore the description thereof will be omitted. Reference numeral 14 is a transmission / reception multiframe phase difference comparison unit that compares the phase of the synchronization detection signal 120 output from the pattern detection unit 6 with the phase of the transmission multiframe and outputs a transmission / reception multiframe phase difference signal 130. Reference numeral 16 is a transmission / reception multiframe position. Transmission / reception multiframe phase difference signal 1 output from the phase difference comparison unit 14
A phase difference delay unit that delays the transmission serial data 108 based on 30.

Next, the operation will be described. In the fourth embodiment, the transmission / reception multi-frame phase difference comparison unit 14 compares the phase of the synchronization detection signal 120 output from the pattern detection unit 6 with the phase of the transmission multi-frame to determine the transmission multi-frame and the reception multi-frame. The phase difference is calculated and the transmission / reception multiframe phase difference signal 130 is output. The transmission / reception multi-frame phase difference signal 130 causes the phase difference delay unit 16 to delay the transmission serial data 108 by the phase difference between the transmission multi-frame and the reception multi-frame to generate delayed serial data 132 and input it to the synchronization protection circuit 10. . Since the delayed serial data 132 input to the synchronization protection circuit 10 is in phase with the transmission multiframe, the synchronization protection circuit 10 can perform forward and backward synchronization protection processing based only on the delayed serial data 132. As shown by the broken line in FIG. 6, the same state as that in which the transmission multi-frame phase state bit developed in the transmission multi-frame phase state bit counter 2 is also used on the receiving side is realized. Since the synchronization protection processing has been described in detail in the section of the second embodiment, the description thereof will be omitted here.

As described above, in the fourth embodiment, the received transmission serial data 108 is input to the synchronization protection circuit 10 as the delayed serial data 132. Since the delayed serial data 132 is in phase with the transmission multi-frame, it is not necessary for the reception side to expand the reception multi-frame phase status bit, and the transmission multi-frame phase status bit expanded in the transmission multi-frame phase status bit counter 2 Can be shared by both sender and receiver. As a result, the receiving side does not need to provide the receiving multi-frame phase status bit counter, and the number of latches used can be reduced accordingly.

Embodiment 5 FIG. 7 is a block configuration diagram for realizing a multi-frame synchronization method according to a fifth embodiment of the present invention. In the figure, the pattern detection unit 6 and the received multi-frame phase status bit counter 8 are the same as those of the first embodiment shown in FIG. Since it is the same as the one described above, its explanation is omitted here. Reference numeral 18 is a memory for storing the received multi-frame phase status bit 136, and 19 is a frame phase detection circuit. The multiframe synchronization method according to the present invention can be applied to a frame synchronization circuit that needs to detect not only the multiframe phase but also the frame phase by the multiframe synchronization bit pattern.
The fifth embodiment shows such an example.

Next, the operation will be described. ITU-T Recommendation X.1 where one multi-frame is composed of 20 frames. 5
Taking the frame format of 0 as an example, the multiframe phase state bits shown in FIG. 2 are also used in the fifth embodiment. The pattern detection unit 6 transmits the transmission serial data 1
The status bits (F
[4. . 0]), multi-frame synchronization is detected by performing processing focusing on the F4 bit having the same pattern as the multi-frame synchronization pattern. The synchronization detection signal 120 output when the pattern detection unit 6 detects multiframe synchronization is input to the reception multiframe phase status bit counter 8. As shown in Fig. 2, F4 bit "0"
The portion where four consecutive "0000" correspond to the frame numbers 9 to 12, so the reception multi-frame phase status bit counter 8 outputs the synchronization detection signal 12
At the timing of receiving 0, the status bit (F [4..0]) corresponding to the frame number 13, that is, "101
11 ”is loaded. Thereafter, the reception multi-frame phase status bit counter 8 loads the status bit corresponding to the frame number for each frame pulse. [Frame number, status bit F [4. . [0]]
From the timing of receiving the synchronization detection signal 120 [13, “1
0111 ”] [14,“ 00110 ”] [15,“ 10
110 ”] ... [20,“ 01110 ”] [1,“ 1
1010 ”] [2,“ 10010 ”] ... As described above, the phase of each frame can be identified from the reception multi-frame phase status bit 136 developed in the reception multi-frame phase status bit counter 8. Therefore, the reception multi-frame phase status bit 136 is stored in the memory 18, and the frame phase detection circuit 19 accesses the memory 18 to know the frame number corresponding to each status bit in the reception multi-frame phase status bit 136. It is possible to detect not only the multi-frame phase of the transmission serial data 108 but also the frame phase.

In the fifth embodiment, the reception multi-frame phase status bit 136 output from the reception multi-frame phase status bit counter 8 is stored in the memory 18,
Since the frame phase detector 19 is configured so as to access the memory 18 to know this, it is possible to detect not only the multi-frame phase of the transmission serial data 108 but also the frame phase.

Embodiment 6 FIG. FIG. 8 is a block configuration diagram for realizing a multi-frame synchronization method according to a sixth embodiment of the present invention. In the figure, the pattern detection unit 6 and the received multi-frame phase state bit counter 8 are the same as those of the first embodiment shown in FIG. The same as that of the second embodiment and the synchronization protection circuit 10 is the same as that of the second embodiment shown in FIG. 4, and therefore the description thereof is omitted here. Reference numeral 18 is a memory for storing the reception multi-frame phase status bit 136 and the sync protection status bit 138. Although the fifth embodiment shown in FIG. 7 shows an example in which not only the multiframe phase but also the frame phase is detected by the multiframe synchronization bit pattern, the sixth embodiment needs to detect the frame phase and perform synchronization protection. It shows an example of a certain frame synchronization circuit.

Next, the operation will be described. ITU-T Recommendation X.1 where one multi-frame is composed of 20 frames. 5
Taking the frame format of 0 as an example, the multiframe phase state bits shown in FIG. 2 are also used in the fifth embodiment. The pattern detection unit 6 transmits the transmission serial data 1
The status bits (F
[4. . 0]), multi-frame synchronization is detected by performing processing focusing on the F4 bit having the same pattern as the multi-frame synchronization pattern. The synchronization detection signal 120 output when the pattern detection unit 6 detects multiframe synchronization is input to the reception multiframe phase status bit counter 8. As shown in Fig. 2, F4 bit "0"
The portion where four consecutive "0000" correspond to the frame numbers 9 to 12, so the reception multi-frame phase status bit counter 8 outputs the synchronization detection signal 12
At the timing of receiving 0, the status bit (F [4..0]) corresponding to the frame number 13, that is, "101
11 ”is loaded. Thereafter, the reception multi-frame phase status bit counter 8 loads the status bit corresponding to the frame number for each frame pulse. [Frame number, status bit F [4. . [0]]
From the timing of receiving the synchronization detection signal 120 [13, “1
0111 ”] [14,“ 00110 ”] [15,“ 10
110 ”] ... [20,“ 01110 ”] [1,“ 1
1010 ”] [2,“ 10010 ”] ... As described above, the phase of each frame can be identified from the reception multi-frame phase status bit 136 developed in the reception multi-frame phase status bit counter 8. Therefore, the reception multi-frame phase status bit 136 and the sync protection status bit 138 representing the current status of sync protection (synchronization established status / out-of-sync status) are stored in the memory 18, and the sync protection circuit 10 stores the data in the memory 1.
By accessing 8 to obtain these values, not only the multi-frame phase but also the frame phase of the transmission serial data 108 can be detected. Therefore, the synchronization is protected in consideration of the frame phase.

In the fifth embodiment, the reception multiframe phase status bit 136 and the synchronization protection status bit 138 output from the reception multiframe phase status bit counter 8 are stored in the memory 18, and the synchronization protection circuit 10 stores the memory 18 therein. Since it is configured so that the user can access these to know these values, it is possible to detect not only the multi-frame phase of the transmission serial data 108 but also the frame phase. Will be able to do.

Embodiment 7 FIG. 9 is a block configuration diagram for realizing a multi-frame synchronization method according to a seventh embodiment of the present invention. In the figure, the transmission multi-frame phase status bit counter 2, data selector 4, and pattern detection unit 6 are shown in FIG. 6 is the same as that of the first embodiment, the synchronization protection circuit 10 is the same as that of the second embodiment shown in FIG. 4, and the transmission / reception multiframe phase difference comparison unit 14 and the phase difference delay unit 16 are the same as those of the first embodiment. Since it is the same as that of the fourth embodiment shown in FIG. 18
Is a memory in which the transmit multiframe phase status bits 134 and sync protection status signal 142 are stored.

Next, the operation will be described. In the seventh embodiment, the transmission / reception multi-frame phase difference comparison unit 14 determines the phase of the synchronization detection signal 120 output from the pattern detection unit 6 and the phase of the transmission multi-frame as in the fourth embodiment shown in FIG. By comparing, the phase difference between the transmission multiframe and the reception multiframe is calculated, and the transmission / reception multiframe phase difference signal 130 is output. This transmission / reception multi-frame phase difference signal 130 causes the phase difference delay unit 16
Delays the transmission serial data 108 by the phase difference between the transmission multi-frame and the reception multi-frame to generate delayed serial data 132 and stores it in the memory 18. Since the delayed serial data 132 stored in the memory 18 is in phase with the transmission multiframe, the transmission multiframe expanded in the transmission multiframe phase status bit counter 2 when the delayed serial data 132 is stored in the memory 18 The phase status bits 134 will be expanded in the memory 18. As a result, the same state as in which the transmission side and the reception side share the transmission multi-frame phase state bit 134 developed in the transmission multi-frame phase state bit counter 2 as shown by the broken line in FIG. 9 is realized. The synchronization protection circuit 10 accesses the memory 18 to obtain the transmission multi-frame phase status bit (step ST14
0), read / write the sync protection status (step S
(T142), frame phase level synchronization protection processing is performed. Since the synchronization protection processing has been described in detail in the section of the second embodiment, the description thereof will be omitted here.

As described above, in the seventh embodiment, the received transmission serial data 108 is stored in the memory 18 as the delayed serial data 132. Since the delayed serial data 132 is in phase with the transmission multi-frame, it is not necessary for the reception side to expand the reception multi-frame phase status bit, and the transmission multi-frame phase status bit expanded in the transmission multi-frame phase status bit counter 2 It becomes possible to share 134 on both the sending side and the receiving side. As a result, the receiving side does not need to provide the receiving multi-frame phase status bit counter, and the number of latches used can be reduced accordingly. Further, since the transmission multi-frame phase status bit 134 is stored in the memory 18, not only the multi-frame phase but also the frame phase can be detected.

[0045]

As described above, according to the first aspect of the invention, there is provided a multi-frame synchronization method for constructing one multi-frame with a plurality of frames and for synchronizing multi-frames of serial data transmitted / received in multi-frame units. ,
Since a predetermined bit among the status bits representing the phase status of the frames forming the multi-frame is used as the multi-frame synchronization bit, it is possible to reduce the number of latches used in the synchronization circuit.

According to the second aspect of the present invention, one multiframe is composed of m frames (m is an integer of 2 or more), and n bits of status bits for identifying each other are assigned to each frame (n: a natural number determined by m), using predetermined bits of the status bits as multiframe synchronization bits, and transitioning n status bits so that the predetermined bits of the n status bits are the same as the multiframe synchronization bits. Since the multi-frame phase state bit to be generated is generated, and the multi-frame phase state bit is used to perform multi-frame synchronization, the circuit can be made compact when the synchronization circuit is realized by using the PLD. There is.

According to the third aspect of the present invention, the transmitting side is provided with the transmitting multi-frame phase state bit counter and the data selector, the receiving side is provided with the pattern detecting section and the receiving multi-frame phase state bit counter, and the transmitting side is provided. The transmission multi-frame phase status bit counter expands the transmission multi-frame phase status bit and outputs the status bit to the data selector, and the data selector inserts a status bit into the serial data for each frame and transmits the serial data. Data is generated and sent to the outside, and on the receiving side, the pattern detection unit that receives the transmission serial data detects a unique portion present in the multiframe synchronization pattern to detect temporary multiframe synchronization and Synchronous detection signal is output and the received multi-frame phase Since the bit counter is configured to expand the received multi-frame phase status bit by loading and transiting the status bit at the timing of this provisional sync detection signal, the conventional sync pattern selector and pattern comparison unit can be used. Compared with this, the number of latches used in the synchronizing circuit can be reduced.

According to a fourth aspect of the present invention, there is provided a multi-frame synchronization method in which one frame is composed of a plurality of frames, and multi-frame synchronization of serial data transmitted / received in units of multi-frames is performed. A detection unit, a reception frame number counter, a synchronization pattern selector, and a synchronization protection circuit are provided, and the pattern detection unit detects a special pattern of the synchronization pattern from the transmission serial data and loads the reception frame number counter to determine the multiframe phase. Used only for temporary pull-in,
After the temporary pull-in is established, the received frame number counter controls the frame phase, the received frame number counter outputs the temporary pull-in frame number based on the frame pulse, and the synchronization pattern selector based on this frame number, the temporary pull-in multi-number. The frame synchronization pattern is output, and when it matches the received serial data, the multi-frame synchronization detection bit is output, and the synchronization protection circuit is configured to perform the synchronization protection processing by this multi-frame synchronization detection bit. There is an effect that a bit pattern match can be detected and synchronization can be protected.

According to the fifth aspect of the present invention, the transmitting side is provided with the transmitting multi-frame phase state bit counter and the data selector, and the receiving side is provided with the pattern detecting section, the receiving multi-frame phase state bit counter, and the synchronization protection circuit. On the transmitting side, the transmission multi-frame phase state bit is expanded in the transmission multi-frame phase state bit counter, and one bit of the state bits is output to the data selector, and the data selector sets a frame for serial data. A status bit is inserted for each of them to generate transmission serial data and send it to the outside. On the receiving side, the pattern detection unit that receives the transmission serial data detects a peculiar portion existing in the multi-frame synchronization pattern. Detects multi-frame temporary sync and outputs temporary sync detection signal The reception multi-frame phase status bit counter loads the status bit at the timing of the provisional synchronization detection signal and transitions one bit in the status bit in the same sequence as the synchronization pattern to develop the reception multi-frame phase status bit. Then, when a predetermined number of times determined to establish multi-frame synchronization is reached while comparing 1 bit in the status bit with the transmission serial data, a synchronization pattern detection pulse is output, and the synchronization protection circuit outputs the synchronization pattern. Since the synchronization protection processing is performed by the detection pulse, the number of latches used can be reduced.

According to the sixth aspect of the present invention, the transmitting side is provided with the transmitting multi-frame phase status bit counter and the data selector, and the receiving side is provided with the pattern detecting section, the transmitting / receiving multi-frame phase difference comparing section, the phase difference delaying section, and A synchronization protection circuit is provided, and on the transmission side, the transmission multi-frame phase status bit is expanded in the transmission multi-frame phase status bit counter and the status bit is output to the data selector. 1 bit of the status bit is inserted for each to generate the transmission serial data and send it to the outside. On the receiving side, the pattern detecting unit that receives the transmission serial data has a peculiar portion existing in the multi-frame synchronization pattern. Detecting multi-frame temporary synchronization by detecting the Then, the transmission / reception multi-frame phase difference comparison unit compares the phase of the temporary synchronization detection signal with the phase of the transmission multi-frame to calculate the phase difference between the transmission multi-frame and the reception multi-frame, and the transmission / reception multi-frame phase difference signal. The phase difference delay unit delays the transmission serial data by the transmission / reception multi-frame phase difference signal to output delayed serial data, and the synchronization protection circuit monitors the delay serial data to perform synchronization protection processing. Since it is configured to do so, it becomes possible to share the transmission multi-frame phase status bit on both the transmitting side and the receiving side, and there is no need to provide a receiving multi-frame phase status bit counter on the receiving side.
There is an effect that the number of latches used can be reduced accordingly.

According to the invention described in claim 7, a pattern detecting section, a reception multi-frame phase state bit counter, a memory, and a frame phase detecting circuit are provided on the receiving side, and the pattern detecting section which receives the transmission serial data is a multi-mode. Multiframe temporary synchronization is detected by detecting a unique portion existing in the frame synchronization pattern and a temporary synchronization detection signal is output, and the reception multiframe phase status bit counter outputs a status bit at the timing of this temporary synchronization detection signal. The received multi-frame phase status bit is output by loading and transitioning and stored in the memory, and the frame phase detection circuit compares the transmitted serial data with the received multi-frame phase status bit stored in the memory. Since it is configured to detect the phase of the received frame by Since it detected until frame phase as well as the multi-frame phase real data, there is an effect that it is possible to perform the protection of synchronization of considering frame phase.

According to the eighth aspect of the present invention, the receiving side is provided with a pattern detecting section, a receiving multi-frame phase state bit counter, a memory, and a synchronization protection circuit, and the pattern detecting section receiving the transmission serial data is a multi-frame. Multiframe temporary synchronization is detected by detecting a unique portion existing in the synchronization pattern and a temporary synchronization detection signal is output, and the reception multiframe phase status bit counter loads the status bit at the timing of this temporary synchronization detection signal. To output the received multi-frame phase status bit and store it in the memory, and the synchronization protection circuit reads and writes the synchronization status in the memory while transmitting serial data and the reception multi-frame stored in the memory. Configured to perform synchronization protection processing by comparing with the frame phase status bit Because, since detectable until just no frame phase multiframe phase of the transmission serial data, there is an effect that it is possible to perform the protection of synchronization of considering frame phase.

According to the ninth aspect of the invention, the transmitting side is provided with the transmitting multi-frame phase status bit counter and the data selector, and the receiving side is provided with the pattern detecting section, the transmitting / receiving multi-frame phase difference comparing section, the phase difference delay section, and the memory. , And a synchronization protection circuit are provided, and on the transmission side, the transmission multi-frame phase status bit is expanded in the transmission multi-frame phase status bit counter and the status bit is output to the data selector. State bit is inserted for each frame to generate transmission serial data and output to the outside.
The pattern detection unit that receives the transmission serial data detects multiframe temporary synchronization by detecting a unique portion existing in the multiframe synchronization pattern, and outputs a temporary synchronization detection signal, and the transmission / reception multiframe phase difference comparison unit Compares the phase of the temporary synchronization detection signal with the phase of the transmission multi-frame to calculate the phase difference between the transmission multi-frame and the reception multi-frame, and outputs the transmission / reception multi-frame phase difference signal. The transmission / reception multi-frame phase difference signal delays the transmission serial data, outputs the delay serial data and stores it in the memory, and the synchronization protection circuit monitors the delay serial data stored in the memory for synchronization protection. Since it is configured to perform processing, the delayed serial data is transmitted in phase with the transmitted multi-frame. Since it is complete, it is not necessary for the receiving side to expand the receiving multi-frame phase status bit, and the transmitting multi-frame phase status bit expanded in the transmitting multi-frame phase status bit counter must be shared by both the sending side and the receiving side. Will be possible. As a result, the receiving side does not need to provide a receiving multi-frame phase status bit counter, and the number of latches used can be reduced accordingly. Further, since the transmission multi-frame phase status bit is stored in the memory, not only the multi-frame phase but also the frame phase can be detected.

[Brief description of drawings]

FIG. 1 is a block configuration diagram for realizing a multi-frame synchronization method according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of multi-frame phase state bits.

FIG. 3 is a diagram showing details of a pattern detection unit.

FIG. 4 is a block configuration diagram for realizing a multiframe synchronization method according to a second embodiment of the present invention.

FIG. 5 is a block configuration diagram for realizing a multi-frame synchronization method according to a third embodiment of the present invention.

FIG. 6 is a block configuration diagram for realizing a multi-frame synchronization method according to a fourth embodiment of the present invention.

FIG. 7 is a block configuration diagram for realizing a multiframe synchronization method according to a fifth embodiment of the present invention.

FIG. 8 is a block configuration diagram for realizing a multi-frame synchronization method according to a sixth embodiment of the present invention.

FIG. 9 is a block configuration diagram for implementing a multi-frame synchronization method according to a seventh embodiment of the present invention.

FIG. 10 is a diagram showing a block configuration for implementing a conventional multi-frame synchronization method.

[Explanation of symbols]

2 Transmit multi-frame phase status bit counter, 4
Data selector, 6 pattern detection unit, 8 reception multi-frame phase status bit counter, 9 reception frame number counter, 10 synchronization protection circuit, 12 synchronization pattern selector, 14 transmission / reception multi-frame phase difference comparison unit, 16 phase difference delay unit, 18 memory , 19 frame phase detection circuit.

Claims (9)

[Claims] 1. A multi-frame synchronization method for constructing one multi-frame by a plurality of frames and for performing multi-frame synchronization of serial data transmitted / received in units of multi-frames, wherein the multi-frame synchronization method represents a phase state of frames constituting the multi-frame. A multi-frame synchronization method characterized in that a predetermined bit among status bits is used as a multi-frame synchronization bit. 2. One multi-frame is composed of m frames (m is an integer of 2 or more), n state bits for identifying each other are assigned to each frame (n is a natural number determined by m), and this state is set. Generate a multi-frame phase status bit that uses a predetermined bit of the bits as a multi-frame sync bit and transitions the n status bits so that the predetermined bit of the n status bits becomes the same as the multi-frame sync bit. The multiframe synchronization method according to claim 1, wherein the multiframe phase status bit is used to perform multiframe synchronization. 3. A transmission multi-frame phase status bit counter and a data selector are provided on the transmission side, a pattern detection unit and a reception multi-frame phase status bit counter are provided on the reception side, and the transmission multi-frame phase status bit is provided on the transmission side. The counter expands the transmission multi-frame phase status bit and outputs the status bit to the data selector, and the data selector inserts the status bit into the serial data for each frame to generate transmission serial data and sends it to the outside. Then, on the receiving side, the pattern detection unit that receives the transmission serial data detects a unique portion existing in the multiframe synchronization pattern to detect multiframe provisional synchronization and output a provisional synchronization detection signal, The receive multi-frame phase status bit counter is 3. The multiframe synchronization method according to claim 2, wherein the received multiframe phase status bits are expanded by loading and transitioning status bits at the timing of the detection signal. 4. A multi-frame synchronization method for constructing one multi-frame with a plurality of frames and synchronizing multi-frames of serial data transmitted / received in units of multi-frames, wherein a pattern detection unit, a reception frame number counter, A sync pattern selector and a sync protection circuit are provided, and the pattern detection unit detects a special pattern of the sync pattern from the transmission serial data, loads the reception frame number counter, and uses the multi-frame phase only for temporary pull-in. After the acquisition is established, the reception frame number counter controls the frame phase, the reception frame number counter outputs the temporary acquisition frame number based on the frame pulse, and the synchronization pattern selector based on this frame number, the temporary acquisition multiframe. 3. A multi-frame synchronization system according to claim 2, wherein a multi-frame sync detection bit is output when the multi-frame sync pattern is output, and a multi-frame sync detection bit is output when the received sync data matches with the received serial data. Frame synchronization method. 5. A transmission multi-frame phase status bit counter and a data selector are provided on the transmission side, and a pattern detection unit, a reception multi-frame phase status bit counter, and a synchronization protection circuit are provided on the reception side, and the transmission side performs the transmission. The transmission multi-frame phase status bit is expanded to the multi-frame phase status bit counter and one bit of the status bit is output to the data selector. The data selector inserts the status bit into the serial data for each frame. The transmission serial data is generated and transmitted to the outside, and at the receiving side, the pattern detection unit that receives the transmission serial data detects a unique portion existing in the multiframe synchronization pattern to detect multiframe temporary synchronization. To output a temporary sync detection signal, The phase status bit counter loads the status bit at the timing of the provisional sync detection signal and transitions one bit in the status bit in the same sequence as the sync pattern to expand the received multi-frame phase status bit, and the status bit When a predetermined number of times for establishing multi-frame synchronization is reached while comparing one bit in the data and the transmission serial data, a sync pattern detection pulse is output, and the sync protection circuit performs sync protection by this sync pattern detection pulse. The multi-frame synchronization method according to claim 2, wherein processing is performed. 6. A transmission multi-frame phase status bit counter and a data selector are provided on the transmission side, and a pattern detection unit, a transmission / reception multi-frame phase difference comparison unit, a phase difference delay unit, and a synchronization protection circuit are provided on the reception side, and the transmission is performed. On the side, the transmission multi-frame phase status bit is expanded in the transmission multi-frame phase status bit counter and the status bit is output to the data selector. The data selector outputs one bit among the status bits for each frame for serial data. To generate a transmission serial data and send it to the outside, and at the receiving side, the pattern detection unit that receives the transmission serial data detects a unique portion existing in the multiframe synchronization pattern, and The synchronization is detected and a temporary synchronization detection signal is output, and the transmission / reception multi-frame is output. The phase difference comparison unit compares the phase of the temporary synchronization detection signal and the phase of the transmission multi-frame to calculate the phase difference between the transmission multi-frame and the reception multi-frame, and outputs the transmission / reception multi-frame phase difference signal, The phase difference delay unit delays the transmission serial data by the transmission / reception multi-frame phase difference signal to output delayed serial data, and the synchronization protection circuit performs synchronization protection processing by monitoring the delayed serial data. The multiframe synchronization method according to claim 2. 7. A peculiar existence of a pattern detection unit, a reception multi-frame phase status bit counter, a memory, and a frame phase detection circuit on the receiving side, wherein the pattern detection unit that receives transmission serial data exists in a multi-frame synchronization pattern. The multi-frame temporary synchronization is detected by detecting the part and a temporary synchronization detection signal is output, and the reception multi-frame phase status bit counter loads the status bit at the timing of the temporary synchronization detection signal and makes a transition to receive. The multi-frame phase status bit is output and stored in the memory, and the frame phase detection circuit detects the phase of the reception frame by comparing the transmission serial data with the reception multi-frame phase status bit stored in the memory. 3. The multiframe synchronization method according to claim 2, wherein . 8. A pattern detection section, a reception multi-frame phase status bit counter, a memory, and a sync protection circuit are provided on the receiving side, and the pattern detection section receiving the transmission serial data is a peculiar portion existing in a multi-frame synchronization pattern. By detecting the multi-frame temporary synchronization and outputting a temporary synchronization detection signal, and the reception multi-frame phase status bit counter loads the status bit at the timing of the temporary synchronization detection signal and makes a transition to receive the multi-frame. The frame phase status bit is output and stored in the memory, and the synchronization protection circuit compares the transmission serial data with the received multi-frame phase status bit stored in the memory while reading and writing the synchronization status in the memory. 3. The multi-function system according to claim 2, wherein the synchronization protection process is performed. Lame synchronization method. 9. A transmission multi-frame phase status bit counter and a data selector are provided on the transmission side, and a pattern detection unit, a transmission / reception multi-frame phase difference comparison unit, a phase difference delay unit, a memory, and a synchronization protection circuit are provided on the reception side. On the transmission side, the transmission multi-frame phase status bit counter is expanded into a transmission multi-frame phase status bit and the status bit is output to the data selector. The data selector inserts a status bit into the serial data for each frame. Then, the transmission serial data is generated and transmitted to the outside, and on the receiving side, the pattern detection unit that has received the transmission serial data detects the unique portion existing in the multiframe synchronization pattern to perform the multiframe temporary synchronization. It detects and outputs a temporary synchronization detection signal, The phase difference comparison unit calculates the phase difference between the transmission multiframe and the reception multiframe by comparing the phase of the provisional synchronization detection signal and the phase of the transmission multiframe, and outputs the transmission / reception multiframe phase difference signal. The phase difference delay unit delays the transmission serial data by the transmission / reception multi-frame phase difference signal, outputs the delay serial data and stores it in the memory, and the synchronization protection circuit monitors the delay serial data stored in the memory. The synchronization protection process is performed by
The described multi-frame synchronization method.