JPH09305530A - Dma controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a direct memory access(DMA) controller with which data to be processed by an input/output device designed based on the CPU of difference data arrangement can be properly processed by the other kind of CPU different from that CPU. SOLUTION: A DMA controller 6 has an arrangement change circuit 9 for changing the arrangement of data to be supplied from the input/output device (reader 7 or personal computer 13) designed corresponding to the Motorola system CPU of a system different from an INTEL system CPU 1 of the present system or data to be supplied from a memory to the relevant input/output device when transferring data with the relevant input/output device. The arrangement change circuit 9 exchanges the high-order byte and low-order byte of the relevant data in the case of word transfer. Besides, in the case of byte transfer, data are transferred by exchanging the odd-numbered address and the even-numbered address on the memory for writing or reading the data by designating any address through an EXOR circuit 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA (Direct Memory Access) controller.

[0002]

2. Description of the Related Art A DMA system is known as a system for performing high-speed data transfer between a control unit including a CPU and an input / output device connected thereto. In normal input / output control (so-called program control), data is transferred between the CPU and the input / output device according to an input / output program. Therefore, when inputting / outputting to / from a device capable of transferring a large amount of data at high speed such as a magnetic disk, it takes a long time to transfer the data and the CPU does not finish the transfer process during the data transfer. Therefore, the utilization efficiency of the CPU is poor. In the DMA method, the control by the CPU is performed only at the start and end of input / output, and once the data transfer is started, the data is directly transferred between the memory and the input / output device after that regardless of the CPU.

A DMA controller is used in the DMA system. The DMA controller is a circuit that controls input / output data transfer instead of the CPU. The DMA controller usually has a plurality of channels, and each channel is connected to an input / output device. The DMA controller and the CPU share a bus, and when the DMA controller is activated, the DM is transferred from the control circuit of the input / output device.
When a bus release request for DMA processing is issued via the A controller, the CPU releases the bus at the time when the processing being executed is completed, and gives the DMA controller the right to use the bus. In response, the DMA controller uses the bus to transfer data to and from the I / O device. The data transfer time (hereinafter, referred to as “DMA cycle”) executed by one DMA request is fixed, and the input / output device repeats the DMA processing until the data transfer processing of the target number of bytes is completed. A bus release request for output. When the DMA controller completes the data transfer process of the unit DMA cycle, the DMA controller returns the right to use the bus to the CPU, and the CPU restarts the process by using the bus. When the bus release request for the DMA processing is continuously output at a certain cycle, the DMA processing for them is continuously performed.

[0004]

The data written in the memory by the DMA processing is used by the CPU for processing, processing the data, and the like. In this case, the CPU reads the data in the memory into a register in the CPU, performs a predetermined operation, etc., and outputs the result to the memory again. The data thus obtained is read from the memory and supplied to other components such as the input / output device. Currently, multiple types of 16-bit processors are widely used depending on the manufacturer, but different types of CP
In U, there are differences in data processing operations and the like. For example, on Intel-based processors and Motorola-based processors,
When data is read into the internal register in order to perform an operation on the data stored in the memory, there is a problem that the array of data is different. On a 16-bit processor,
There are cases where data is handled in word (that is, 2 bytes) units and cases where data is handled in bytes, but in the Intel type processor and the Motorola type processor, the upper 1 byte and the lower 1
The byte array is reversed.

This will be described more specifically. For example, assume that a 16-bit signal as shown in FIG. 3 is input to the system. This signal is serial / parallel converted and stored in a memory (RAM) in an array as shown in FIG. In addition, "n address", "n + 2 address", "n + 4 address" ,. . . Indicates the data storage address to be specified on the program when handling data in units of words (16 bits), and normally specifies the address of the lower byte (even address, A0 = 0). The upper byte (odd address,
Data is written or read in word units together with the data of A0 = 1). For example, when a word unit instruction in which "n address" is designated is executed on a program, a total of 16 bits are targeted for "n address (even address)" and "n + 1 address (odd address)". Data writing or reading is simultaneously executed. Therefore, when data writing or reading is continuously performed in word units, two designated addresses are added, such as "n address" and "n + 2 address". Here, for example, when the data in the RAM is processed by the CPU of the Motorola system, the data is taken into the register in the CPU in the same arrangement. But,
When the data in the RAM is calculated by the CPU of the Intel system, the upper byte and the lower byte of the data in the RAM are loaded into the register in the CPU (see FIG. 4B). Therefore, when the data supplied in the array as shown in FIG. 3 is operated by the CPU of the Intel system, the data in which the upper byte and the lower byte are exchanged is operated, and the correct operation cannot be performed.

From this point of view, the system is usually designed to handle data in a data array according to the method of the CPU used. Actually, Motorola CP
When the U is used, the system is designed so that the data is supplied in the RAM in the arrangement as shown in FIG. 4A, and when the Intel CPU is used, the data is shown in FIG.
RA with an array in which the upper and lower bytes are opposite to those in (A)
The system is designed to feed M.

However, in some cases, there is a demand for integrating a plurality of systems designed to use different CPUs so that the functions of both systems can be realized under the control of one CPU. . In such a case, it is time consuming and costly to redesign the other system and rewrite the software so as to match the operation of the CPU of one system. Therefore, it is desired to be able to integrate a plurality of systems without making a fundamental design change of the existing system as much as possible. Specifically, there is a case where a system designed for an Intel CPU and a system designed for a Motorola CPU are integrated, and it is desired to control the whole by one Intel CPU. In this case, if the data to be processed by the system designed for the Motorola CPU is to be directly processed by the Intel CPU, as described above, the CPU
Since the arrangement of the data is different when the data is read in, there is a problem in that the intended calculation and processing cannot be performed.

The present invention has been made in view of the above points, and it is possible to correctly process data processed by a system designed based on CPUs having different data arrays by a CPU of a different type. It is an object to provide a possible DMA controller.

[0009]

In order to solve the above-mentioned problems, the invention according to claim 1 is a DMA controller which transfers data between a control unit including a CPU and a memory and an input / output unit. A transfer circuit that transfers data output from the output unit to the memory and transfers data read from the memory to the input / output unit, wherein the transfer circuit outputs from the input / output unit or the memory It is configured to have an array changing circuit that changes the array of the generated data.

According to the DMA controller configured as described above, the arrangement changing circuit changes the arrangement of the data to be transferred and transfers the data. According to a second aspect of the present invention, in the DMA controller according to the first aspect, the arrangement changing circuit replaces the high-order few bits and the low-order few bits of the data output from the input / output unit or the memory. To configure.

According to the arrangement changing circuit configured as described above, the data outputted from the input / output unit or the memory is transferred by the arrangement changing circuit with the high-order several bits and the low-order several bits exchanged.

According to a third aspect of the present invention, in the DMA controller according to the second aspect, the arrangement change circuit is configured to input data or the input data based on a designation signal output from the CPU. The selection circuit is configured to selectively output either one of the data in which the high-order several bits and the low-order few bits are replaced.

According to the DMA controller configured as described above, the selection circuit swaps the raw data of the data input to the array conversion circuit with the high-order number bits and the low-order number bits based on the designation signal from the CPU. Selectively outputs one of the data.

According to a fourth aspect of the present invention, in the DMA controller according to the first aspect, the arrangement changing circuit is configured to change an address for writing the data in the memory or an address for reading the data from the memory. To do.

According to the DMA controller configured as described above, the address for writing the data in the memory or the address for reading the data from the memory is changed when the data is transferred.

According to a fifth aspect of the present invention, in the DMA controller according to the fourth aspect, the array changing circuit determines the maximum number of address signals supplied to the memory based on a designation signal output from the CPU. It is configured to be a circuit that inverts the lower bits.

According to the DMA controller configured as described above, at the time of data transfer, the least significant bit of the address signal supplied to the memory is inverted based on the designation signal output from the CPU.

The invention according to claim 6 is the DMA controller according to any one of claims 1 to 5,
The CPU is configured so that, when data is fetched from a memory into a register inside the CPU on a word-by-word basis, the upper byte array and the lower byte array are swapped and loaded.

According to the DMA controller configured as described above, when the data is fetched from the memory into the register inside the CPU in word units, even when the arrangement of the upper byte and the lower byte is exchanged,
The data arrangement of the upper byte and the lower byte is changed by the arrangement changing circuit.

[0020]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a configuration of a control unit of a facsimile apparatus to which a DMA controller according to an embodiment of the present invention is applied and a configuration of a relationship with an input / output device thereof. In FIG. 1, the CPU 1 is assumed to be an Intel type processor, and the control system of the recording device 8 is designed corresponding to the data processing method of the Intel type CPU. In addition, the reading device 7
The control system of the personal computer 13 is designed to correspond to the data processing system of the CPU of the Motorola system.

As shown in FIG. 1, the control unit 100 of the facsimile apparatus includes a CPU 1 and a ROM connected to the bus 4.
2, RAM 3, modem 5, and DMA controller 6. When the DMA controller 6 is in the activated state, R
AM3 EXOR including the address counter 14
An address is designated by an address control unit including an (exclusive OR) circuit 15 and a latch circuit 16. The DMA controller 6 is a cycle counter control unit for setting and counting transfer cycles in addition to the address control unit including the address counter 14 or I / O (input / output) when in the DMA activated state. In order to execute the DMA processing based on the data transfer request from the control unit 18,
A timing control unit for issuing a bus release request (BUS REQUEST) to the CPU 1 is provided, and in the present embodiment, the arrangement changing circuit 9 shown in FIG. 2 is provided. The array changing circuit 9 of the DMA controller 6 is connected to the reading device 7 via a register 10 and a serial / parallel converter 11 provided in the I / O control unit 18, and also has a register 12 and a parallel / serial converter 19. It is connected to the personal computer 13 via the register and to the recording device 8 via the register 20. In addition,
The I / O control unit 18 includes registers for other input devices, but the description thereof is omitted here.
The array changing circuit 9 is connected to a latch circuit 17 that latches the array changing instruction data D2 output from the CPU 1. The EXOR circuit 15 and the latch circuit 16 in the address control unit function as an arrangement changing circuit.

The RAM 3 functions as a temporary storage device for data when executing various calculations and controls. R
The OM 2 stores various programs, and the CPU 1 executes various programs by executing these programs. The address counter 14 in the DMA controller 6 counts the address value starting from the start address given by the CPU 1 at the time of starting the DMA, and RAM
The address signals A0-A23 designating the address 3 are output. The CPU 1 sends the DMA activation signal Sd to activate the array change instruction data D1 for byte transfer before the DMA controller 6 is activated.
Supply to The array change instruction data D1 becomes "1" when byte transfer is performed with array change, and is "0" when word transfer is performed or byte transfer without array change is performed. The latch circuit 16 latches the arrangement change instruction data D1 and the EXOR circuit 15
Supply to The EXOR circuit 15 calculates the exclusive OR of the output of the latch circuit 16 and A0 which is the least significant byte of the address signal, and supplies it to the RAM 3 as the address signal A0. The address signals A1-A23 are directly supplied from the address counter 14 to the RAM 3.

The CPU 1 also includes a DMA controller 6
Prior to activating, the array change instruction data D2 for word transfer is supplied to the latch circuit 17. The array change instruction data D2 is "1" when word transfer is performed with array change, and is "0" when byte transfer is performed or word transfer without array change is performed. The latch circuit 17 latches the arrangement change data D2 and supplies it to the arrangement change circuit 9 as a selection signal Ss.

The recording device 8 is a printer unit provided in the facsimile, and receives data received by the modem 20.
Alternatively, the data output from the reading device 7 is received via the DMA controller 6 and the register unit 20 of the I / O control unit 18, and recorded on a recording sheet. The recording device 8 is
Since it is designed for the Intel CPU as described above, it is not necessary to change the data array when performing the DMA transfer.

On the other hand, the reading device 7 is a device for reading a transmission original, and the read data is converted into parallel data by the serial / parallel converter 11 of the I / O control unit 18 and temporarily stored in the register 10. Then, it is input to the array changing circuit 9. The personal computer 13 is also used to store the data received by the modem 20 in the internal memory. Note that the data stored in the personal computer can be read out to perform processing such as printing by the recording device as necessary, but in the present embodiment, only data transfer to the personal computer 13 will be described for convenience of explanation. . Between the personal computer 13 and the array changing circuit 9,
A register 12 for temporarily storing data and a parallel / serial converter 19 are provided. As described above, the input / output control of the reading device 7 and the personal computer 13 are both designed to correspond to the CPU of the Motorola system, and the CPU 1 cannot process the data array as it is. When inputting / outputting data via 9, it is necessary to change the array.

A concrete configuration of the array changing circuit 9 is shown in FIG. As illustrated, the array changing circuit 9 includes a selector 21 connected to the register 10, a selector 22 connected to the registers 12 and 20, and a buffer unit 23 connected to the bus 4. The 16-bit data from the reader 7 is directly input to the input terminals X0-X15 of the selector 21, and the upper 8 bits and the lower 8 bits of the 16-bit data from the reader 7 are input to the input terminals Y0-Y15. Bits are swapped and input. When the selection signal Ss supplied from the latch circuit 17 is "1", the selector 21 outputs the input of the input terminals Y0-Y15, and the selection signal is "0".
In case of, the input of the input terminals X0-X15 is output. Also,
1 from the bus 4 is connected to the input terminals X0-X15 of the selector 22.
6-bit data is input as is, input terminal
Y0-Y15 have the upper 8 bits of 16-bit data from bus 4.
Bits and lower 8 bits are exchanged and input. The selector 22 outputs the input of the input terminals Y0-Y15 when the selection signal Ss is "1", and outputs the input of the input terminals X0-X15 when the selection signal is "0".

Next, a specific operation will be described. First, the I / O controller 18 transfers data to the RAM 3 by DMA transfer as various input / output devices (reading device 7, personal computer 13, recording device 8, etc.) start predetermined operations. Alternatively, on the contrary, when receiving data from the RAM 3, the CPU 1 is requested to start the DMA by outputting an interrupt signal. Then C
PU1 should start DMA transfer by executing a predetermined interrupt process programmed in advance.
The start address (start address) of AM3, the number of transfer cycles, the transfer mode, etc. are sent to the DMA controller 6, and the address counter 14 and the cycle counter are set to predetermined values to perform a preparatory operation for DMA transfer. . After that, the CPU 1 outputs the DMA activation signal Sd to the DMA controller 6. It should be noted that each signal output from the CPU 1 to the DMA controller 6 including the DMA start signal Sd is supplied via the bus 4, but the signal flow can be easily understood in FIG. In order to do so, it is displayed separately from the bus 4.

The DMA controller 6, which has been activated based on the DMA activation signal Sd, then receives a data transfer request from the I / O controller 18 and then the CPU 1
Issue a bus 4 release request (BUS REQUEST) to C
Response signal (BUS ACKNOWLE) indicating that the bus was released from PU1.
DGE), DMA processing is sequentially executed one cycle at a time. Specifically, the data stored in the address portion of the RAM 3 designated by the address counter 14 is transferred to a predetermined register of the I / O control unit 18, or is transferred to a predetermined register of the I / O control unit 18. The stored data is written in the address portion of the RAM 3 designated by the address counter 14. Then, every time one data transfer is completed, the count value of the address counter 14 is advanced and the cycle counter is decremented. Thereafter, the same operation is repeated, and when the value of the cycle counter becomes “0”, the DMA processing is ended.

By the way, as the data transfer by the DMA performed by the control device 100, there are word transfer and byte transfer. Word transfer is a method of transferring target data for each word (2 bytes), and byte transfer is a method of transferring target data for each byte. Control device 10
The operation of 0 differs depending on which transfer method is used.

First, the operation during word transfer will be described. During word transfer with array change, CPU1 DM
Before activating the A controller 6 (sending the activation signal Sd), the array change instruction data D1 is set to "0" and the array change instruction data D2 is set to "1". As a result, the latch circuit 16 latches "0" and the latch circuit 17 latches "1". In this case, the array change instruction data D1 is "0".
Therefore, the EXOR circuit 15 supplies the address signal A0 output from the address counter 14 to the RAM as it is. Therefore, the conversion of the address of RAM3 described later is not performed.

First, in this state, consider a case where the data read by the reading device 7 is transferred to the RAM 3 by DMA. In this case, since the latch circuit 17 latches "1", the latch circuit 17 supplies the selection signal Ss of "1" to the selectors 21 and 22 of the arrangement changing circuit 9. The reading device 7 reads the transmission document with a line image sensor, binarizes it using a predetermined threshold value, and generates and outputs read data as shown in FIG. 3, for example. The serial / parallel converter 11 converts this read data into parallel data in 16-bit units.
The register 10 temporarily stores this and supplies it to the array changing circuit 9 during DMA execution. In the array changing circuit 9, since the selection signal Ss is "1", the selector 21 outputs the input data of the input terminals Y0-Y15. Input terminal Y0-Y1
Since the read data XD0 to XD15 are input to 5 in a form in which the upper byte and the lower byte are exchanged, the array changing circuit 9 transfers the read data in which the upper byte and the lower byte are exchanged to the DMA controller 6. Supply to the bus 4 via. The controller 6 uses the opened bus 4
Is used to transfer the read data to the RAM 3. Since the upper byte and the lower byte of the read data stored in the RAM 3 in this way are exchanged,
In the case of 1, the data can be fetched in the internal register in units of words, and the correct operation can be performed when performing the operation.

Next, the process of transferring the data in the RAM 3 which has been processed by the CPU 1 to the personal computer 13 by DMA will be described. In this case, CPU1
Since it is the data after the processing by, the data array corresponding to the CPU 1 is stored in the RAM 3.
In this case as well, since it is necessary to change the arrangement, the CPU 1 sets the arrangement change instruction data D1 to "0" and the arrangement change instruction data D2 to "1" and outputs the DMA start signal Sd.
Therefore, the selector 21 in the array changing circuit 9 is set to "1".
Will be supplied. The DMA controller 6 reads the data in the RAM 3 by DMA using the released bus 4 and supplies the data to the arrangement changing circuit 9. Selector 22 in array changing circuit 9
Input the selection signal "1", input terminal Y0
The input signal of -Y15, that is, the data in which the upper byte and the lower byte of the output data from the RAM 3 are exchanged, is output to the register 12. The register 12 temporarily holds this data, converts it into serial data by the parallel / serial converter 19 and supplies it to the personal computer. In this case, the data is supplied to the personal computer 13 via the serial interface. In this way, the data in the RAM 3 processed by the CPU 1 is the CPU of the Intel system.
Although it has a data array corresponding to 1, the upper order byte and the lower order byte are exchanged by the array changing circuit before being input to the personal computer 13 in which the control system is designed corresponding to the Motorola CPU. . Therefore, the personal computer 13 receives the data of the array suitable for its own system design, and the correct processing can be performed.

On the other hand, when the data in the RAM 3 is transferred to the recording device 8 by DMA, the CPU 1 sets the arrangement change instruction data D1 and D2 to "0" and outputs the DMA start signal Sd to the DMA controller 6. . Therefore, since the selector 22 in the array changing circuit 9 is supplied with the selection signal Ss of "0", the input signals of the input terminals X0-X15, that is, the output data from the RAM 3 are stored in the register 20 in the same array. It will be stored, and the upper byte and the lower byte of the data are not exchanged. This is because the control system of the recording apparatus is designed to correspond to the same Intel CPU as the CPU 1, as described above.
This is because it is unnecessary to change the data arrangement. Therefore, bus 4
The data transferred by the DMA controller 6 by utilizing the above is supplied to the recording device 8 with the arrangement stored in the RAM 3 as it is. As described above, RA by DMA
Data transfer between the M3 and the reading device 7, the personal computer 13 or the recording device 8 is performed.

Next, the operation during byte transfer will be described.
At the time of byte transfer, of 16-bit (2-byte) data, the data is transferred in units of the upper or lower 1 byte. Therefore, the data of the upper byte and the data of the lower byte are not exchanged by using the arrangement changing circuit 9, but the data of 1 byte is transferred with the bit arrangement as it is, and the write or read address in the RAM 3 is exchanged. Will replace the odd address with the even address. The EXOR circuit 15 exchanges the addresses. That is, at the time of byte transfer accompanied by address array change, the CPU 1 sets the array change instruction data D1 to "1" and the array change instruction data D2 to "0" before activating the DMA controller 6. As a result, the latch circuit 16 latches “1” and the latch circuit 1
7 latches "0". Therefore, the latch circuit 17
Since the selection signal Ss of "0" is supplied to the array changing circuit 9, the array changing circuit 9 outputs the data as it is without exchanging the upper byte and the lower byte of the transfer data.
On the other hand, since the output of the latch circuit 16 is "1", the EXO
The R circuit 15 inverts the address signal A0 output from the address counter 14 and supplies it to the RAM 3. As can be seen from FIG. 4A, when the least significant bit A0 of the address signal is inverted, the addresses designated by the address counter 14 are replaced with odd addresses by even addresses and even addresses by odd addresses. Therefore, RAM
3, the start address of the DMA transfer designated by the address counter 14 is, for example, "address n", "n + 1 address", "n address", "n + 3 address",
Data is written or read in the order of "n + 2 address".

Reader 7 connected to I / O controller 18
The data input from every other reading device is 1 byte.
The data is input to the array changing circuit 9, and the DMA controller 6 uses the released bus 4 to transfer data to the RAM 3. Here, since the address signal A0 is inverted, the data is written by changing the writing order to the odd address and the even address. Therefore, when the CPU 1 fetches the data in word units into the internal register and performs processing such as calculation, correct data processing can be performed based on the data from the input device designed for the Motorola CPU. it can. On the other hand, when the data resulting from the operation of the CPU 1 is DMA-transferred in units of words or bytes to a predetermined output device, the DMA controller 6 RAs in the order in which odd addresses and even addresses are exchanged.
The data is read from M3 and output to a predetermined output device. Therefore, the read data is the Motorola CP
It is compatible with the data array of the control system of the output device designed corresponding to U. In the case of transfer that performs DMA transfer to other output devices designed for Intel CPUs,
Since the CPU 1 sets both the parallel change instruction data D1 and D2 to "0", the EXOR circuit 15 does not exchange the addresses, and the data array written in the RAM 3 by the CPU 1 is transferred to the output device in byte units. . For example, in the example of FIG. 4A, "n address", "n +"
Data is transferred in the order of "1st address", "n + 2th address", and "n + 3th address".

As described above, according to the present invention, D
Since the upper byte and the lower byte of the data can be exchanged by the array changing circuit 9 during the word transfer by the MA, the control system of the input / output device such as the reading device 7 and the personal computer 13 corresponds to the CPU of the type different from the CPU 1. Even if it is designed to handle data in, the CPU 1 can process the data in such an array. Further, in the case of byte transfer by DMA, since the addresses of the RAM 3 can be exchanged by the EXOR circuit 15, the data transfer is performed by exchanging the order of writing or reading 1-byte unit data to the odd address and the even address. As a result, similarly, it becomes possible to process the data of the array corresponding to different CPUs. Therefore, when a new system is configured by partially combining already designed systems, it is not necessary to newly design the entire system or develop software even when using different types of CPUs. . As a result, it becomes possible to efficiently construct a new system using the existing system.

In the above-mentioned embodiment, the DMA transfer is also performed through the arrangement changing circuit 9 for the input / output devices such as the recording device 8 having the same CPU type.
Without being limited to this, for example, a circuit configuration may be adopted in which DMA transfer is performed for the input / output device having the same CPU type without interposing the arrangement changing circuit 9.

[0038]

According to the invention of claim 1, for example,
When the input / output unit is designed to correspond to a CPU different from the CPU of the control unit, the arrangement changing circuit changes the data arrangement. Therefore, a system designed to correspond to a different CPU is integrated into a new one. The system can be easily configured.

According to the second and third aspects of the present invention, the arrangement change circuit only changes the high-order several bits and the low-order few bits of the data, so that the data arrangement can be changed with a simple circuit.

Further, according to the inventions of claims 4 and 5, the arrangement changing circuit only changes the address on the memory where the data is written or read, so that the arrangement is simple and the actual data is changed. The data array can be changed without any processing.

According to the sixth aspect of the present invention, when the data is fetched from the memory into the register inside the CPU in word units, even if the arrangement of the upper byte and the lower byte is interchanged, the higher order bytes are fetched. Since the data arrangement of the byte and the lower byte is changed, it becomes possible to perform a correct operation in the CPU.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a control unit of a facsimile apparatus according to an embodiment of the present invention and a relationship with an input / output device.

FIG. 2 is a diagram showing a circuit configuration of an array changing circuit shown in FIG.

FIG. 3 is a diagram showing an example of data transferred to a RAM.

FIG. 4 is a diagram showing an arrangement of data transferred to a RAM.

[Explanation of symbols]

 1 ... CPU 3 ... RAM 5 ... Modem 6 ... DMA controller 7 ... Reading device 8 ... Recording device 9 ... Array changing circuit 13 ... Personal computer 14 ... Address counter 15 ... EXOR circuit 21, 22 ... Selector

Claims (6)

[Claims] 1. A DMA controller for transferring data between a control unit including a CPU and a memory and an input / output unit, wherein data output from the input / output unit is transferred to the memory and read from the memory. A DMA controller that transfers the selected data to the input / output unit, and the transfer circuit includes an array changing circuit that changes an array of the data output from the input / output unit or the memory. . 2. The DMA controller according to claim 1, wherein the array changing circuit replaces the high-order few bits and the low-order few bits of the data output from the input / output unit or the memory. 3. The array changing circuit, based on a designation signal output from the CPU, either the input data or the data obtained by exchanging the high-order few bits and the low-order few bits of the input data. 3. The DMA controller according to claim 2, which is a selection circuit that selectively outputs. 4. The array changing circuit changes an address for writing the data in a memory or an address for reading the data from the memory.
The DMA controller described. 5. The arrangement changing circuit is a circuit for inverting a least significant bit of an address signal supplied to the memory based on a designation signal output from the CPU. DMA controller. 6. The CPU is of a system in which, when data is fetched from a memory into a register in the CPU in word units, the upper byte array and the lower byte array are interchanged and are fetched. 6. The DMA controller according to any one of 5 to 5.