JPH09305527A - Dma controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a direct memory access(DMA) controller with which the priority of respective channels can be changed as needed corresponding to the operating conditions of a system in the case of multichannel DMA processing. SOLUTION: A channel determination circuit 8 receives DMA processing request signals S1-S7 concerning plural channels, and the DMA processing of any correspondent channel is executed by a DMA processing circuit 9. When the DMA requests of plural channels are overlapped in time, based on the priority predetermined corresponding to the operating mode of the system, the channel determination circuit 8 determines one channel to execute DMA processing. Therefore, the plural DMA requests are executed in order from the high priority but that order is changed corresponding to the mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA (Direct Memory Access) controller.

[0002]

2. Description of the Related Art A DMA system is known as a system for performing high-speed data transfer between a control unit including a CPU and an input / output device connected thereto. In normal input / output control (so-called program control), data is transferred between the CPU and the input / output device according to an input / output program. Therefore, when inputting / outputting to / from a device capable of transferring a large amount of data at high speed such as a magnetic disk, it takes a long time to transfer the data and the CPU does not finish the transfer process during the data transfer. Therefore, the utilization efficiency of the CPU is poor. In the DMA method, the control by the CPU is performed only at the start and end of input / output, and once the data transfer is started, the data is directly transferred between the memory and the input / output device after that regardless of the CPU.

A DMA controller is used in the DMA system. The DMA controller is a circuit that controls input / output data transfer instead of the CPU. The DMA controller usually has a plurality of channels, and each channel is connected to an input / output device. The DMA controller and the CPU share a bus. For example, when performing data transfer by DMA between one of the plurality of input / output devices and the memory, the CPU is a memory that performs DMA transfer to the DMA controller. Send the start address (start address), data of the number of transfer cycles, etc., set the address counters and cycle counters provided for each of the plurality of channels to predetermined values, and then set the corresponding channels to the activated state. . The DMA controller issues a bus release request (BUS REQUEST) to the CPU when a request for DMA processing (DMA request) is output from the corresponding input / output device when the channel is in the activated state. Then, the CPU releases the bus at the end of the process being executed and gives the bus use right to the DMA controller. After that, the DMA controller uses the bus to transfer data to and from the input / output device. In particular,
Response signal from the CPU indicating that the bus has been released (BUS ACKNOWLE
DGE) causes the DMA controller to transfer the memory data specified by the address counter of the corresponding channel to the I / O device that made the DMA request, or to transfer the data input from the I / O device by the address counter. Write to the specified memory address. Then, each time one data transfer is completed, the count value of the address counter is advanced and the cycle counter is decremented. The time of data transfer executed by one DMA request (hereinafter referred to as “DMA cycle”) is fixed, and the input / output device repeatedly outputs the DMA request until the data transfer process of a predetermined number of cycles is completed. . When the DMA controller completes the data transfer process in the unit DMA cycle, the DMA controller passes the right to use the bus to the CPU, and the CPU restarts the process by using the bus. When the DMA requests are continuously output in a certain cycle, the DMA processing for them is continuously performed.

When DMA processing is performed on a plurality of input / output devices, that is, when a plurality of channels are set in the activated state, the timing at which each input / output device issues a DMA request depends on the operating condition of each device. Therefore, DMA requests may be issued from a plurality of input / output devices almost at the same time. In this case, the DMA controller cannot perform the DMA processing for a plurality of channels at the same time, so that one of the channels is given priority to perform the DMA processing. Conventionally, such priorities of a plurality of channels have been fixedly determined in advance according to the importance of the processing performed by each input / output device. That is, in that system,
The more likely the process is to lead to a fatal malfunction, the more DMA
It was set to have a higher priority when a request is made.

This will be described with reference to a specific example of a facsimile machine. In recent facsimile machines,
In addition to the basic operation of sending and receiving data, the function as a copy that prints the contents of the read original,
It is known that a plurality of functions such as temporarily saving read data in a personal computer (hereinafter, referred to as “personal computer”) and using it as data can be realized. In this case, an image reading device that reads a document,
A recording device that outputs data, an interface that transfers data to a personal computer, etc. function as input / output devices, and DMA
Assigned to each channel of the controller. Normal,
Considering the importance of each function as a facsimile device, the priority order of reading by the image reading device at the time of transmission, recording on recording paper at the time of reception, and data transfer with a personal computer is determined. D's function
When the MA requests overlap in time, the DMA processing for one channel determined according to this priority order is performed.

[0006]

However, if the priority order of each channel of the DMA is fixed in this way, it is possible to cope with the case where particularly important processing occurs due to the system condition without any inconvenience. Will be difficult. For example, during the reception of a facsimile, the data corresponding to the recording device of the DMA controller is repeatedly used for the data transfer by the DMA processing to record the received data on the recording paper. When it becomes more important to transfer the data to the personal computer, it is desirable to prioritize the DAM processing of the channel corresponding to the data transfer to the personal computer. However, in the conventional DMA controller, since the priority of each channel is fixed as described above, the DMA processing for transferring to the personal computer can be prioritized over the DMA processing for recording on the recording paper. There wasn't. Therefore, even in a system capable of realizing a plurality of functions, it may not be possible to perform various processing by making the best use of its capabilities.

The present invention has been made in view of the above points, and in multi-channel DMA processing, it is possible to change the priority of each channel as necessary according to the operating status of the system. It is an object to provide a DMA control device.

[0008]

In order to solve the above problems, the invention according to claim 1 is provided in a system which operates in a plurality of operation modes, and which has a plurality of channels.
The A controller receives a DMA processing request signal corresponding to the plurality of channels, selects one of the plurality of channels, and determines a channel for executing the DMA processing, and the channel determination circuit. A DMA processing circuit that executes a DMA processing of the channel determined by the circuit, wherein the channel determination circuit determines one channel based on a priority determined for each operation mode of the system. Configure.

According to the DMA controller configured as described above, the channel determination circuit receives the DMA processing request signals for a plurality of channels, and based on the priority determined in advance according to the operation mode of the system,
One channel to execute the DMA process is determined. D
The MA processing circuit performs DMA for the determined channel.
Execute the process.

The invention according to claim 2 is the DMA controller according to claim 1, wherein the priority order is determined according to the importance of processing of the system corresponding to the channel. .

According to the DMA controller configured as described above, the D of the channel with the high priority is assigned based on the priority determined according to the importance of the processing of the system.
MA processing is given priority.

According to a third aspect of the present invention, in the DMA controller according to the first or second aspect, the channel determination circuit has a logical operation circuit for performing a logical operation according to the priority order. .

According to the DMA controller configured as described above, one channel to execute the DMA process is determined by the logical operation according to the priority order. Further, the invention according to claim 4 is the DMA controller according to claim 1 or 2, wherein the channel determination circuit has a storage device that stores the priority order for each of the operation modes.

According to the DMA controller configured as described above, the channel determination circuit refers to the storage content of the storage device storing the priority order for each operation mode, and executes the DMA.
Determine one channel on which to perform the process.

According to a fifth aspect of the present invention, in the DMA controller according to any one of the first to fourth aspects,
A sampling circuit for sampling the DMA processing request signal at a predetermined cycle and supplying the sampled signal to the channel determination circuit is provided.

According to the DMA controller configured as described above, the DMA processing request signal sampled by the sampling circuit at a predetermined cycle is supplied to the channel determination circuit.

[0017]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a configuration of a control device of a multifunctional facsimile apparatus to which a DMA control circuit according to an embodiment of the present invention is applied and a configuration of a relationship with an input / output device thereof. The document reading mechanism and the recording sheet conveying mechanism of the facsimile apparatus are not directly related to the present invention, and thus the description thereof is omitted.

As shown in FIG. 1, a control unit 100 for performing control processing of a facsimile apparatus, via an I / O port 11, an image reading apparatus 12, a binarization circuit 13, a recording apparatus 1
4, the interface 15, the communication partner device 17 and the operation panel 18 are electrically connected. Control unit 1
00 is a RAM 1, a ROM 2, an EEPROM 3, a transmission / reception control circuit 4, a modem 5, a CPU 6, a DMA processing circuit 9, in addition to an I / O port 11 for connecting to the outside.
An information compression / decompression unit 10 is provided, each of which is a bus 2
Connected to 0. The DMA processing circuit 9 uses the OR
Circuit 7, channel determination circuit 8, sampling circuit 8a
Together with this, it constitutes a DMA controller as a whole.

The RAM 1 is used as a temporary storage device for data when executing various controls. ROM2
Stores various programs, and the CPU 6 executes various processes by executing those programs.
The EEPROM 3 stores threshold data of a binarizing circuit that binarizes the read data of the transmission original read by the image reading device 12. Transmission / reception control circuit 4
When the facsimile device and the partner device 17 are connected to each other, the partner device 17 exchanges transmission related information such as the facsimile number and the resolution of the partner device 17. The modem 5 modulates a digital signal into an analog signal and outputs the analog signal to the outside, and demodulates the analog signal input from the outside into a digital signal.

The OR circuit 7 calculates the logical sum of the DMA request signals S1 to S7 output from the control unit of each input / output device and supplies the bus release request signal to the CPU 6. The sampling circuit 8a is a DMA that supports multiple channels.
The request signals S1 to S7 are input, sampled at a constant cycle, and supplied to the channel determination circuit 8. Note that DMA
The request signal shall be "1" when a request is issued. The channel determination circuit 8 is a circuit that performs a logical operation on a plurality of channels in accordance with a predetermined priority order of DMA processing, and selects one of the seven input signals according to a predetermined priority order, a so-called priority encoder. It has the function as. When only the DMA request signal of one channel is input, the channel determination circuit 8 receives the DMA request and performs the DM processing of the corresponding channel.
Instruct the A processing circuit 9. On the other hand, when the DMA request signals for a plurality of channels are input at the same sampling timing of the sampling circuit 8a, the channel determination circuit 8 gives priority to the DMA request signals for a plurality of channels based on the predetermined priority order. An instruction to select the highest-ranked channel and perform the DMA processing of that channel is output to the DMA processing circuit 9. The DMA processing circuit 9 has a plurality of channels, and the channel determination circuit 8
The DMA processing of the one channel determined by is executed. The information compression / decompression unit 10 compresses read data, transmission data, and the like.

The image reading device 12 reads a transmission original,
The read data is supplied to the binarization circuit 13. The binarization circuit 13 binarizes the read data supplied from the image reading device 12 based on the threshold data stored in the EEPROM 3. The recording device 14 records the data transmitted from the outside on the recording paper. The personal computer 16 is connected to the control unit 100 via the interface 15, inputs the data received by the control unit 100 via the interface 15 and stores the data internally, and also stores the data stored internally as necessary. It is supplied to the control unit 100 via the interface 15. As the interface 15, for example, an interface of Centronics specification is used. The partner device 17 is a facsimile device of a communication partner and is connected via the NCU 30. The operation panel 18 is a panel provided on the front surface of the facsimile apparatus, and the user operates the keys on the operation panel 18 to perform transmission / reception and setting of an operation mode.

FIG. 2 shows processes (input / output devices) assigned to each channel of the DMA processing circuit 9 and their priorities. As shown in FIG. 2, channel 1 (ch1) of the DMA processing circuit 9 is assigned to read the transmission original by the image reading device 12, and channel 2 is assigned to record the received data on the recording paper. PC 1 with Centronics interface for 3
Data input from 6 is assigned, and channel 4 uses a Centronics interface PC 1
Data output to 6 is assigned. Also, data compression control is assigned to channels 5 and 6,
A process corresponding to a key input to the operation panel 18 is assigned to the channel 7. Further, the priority of each channel is the same as that of each channel number in the normal mode, but in the special mode, the data output (channel 4) to the personal computer 16 using the Centronics interface has the second highest priority. .

Next, the operation will be described. In this embodiment, as described above, there are two modes in which the priority of each DMA channel is different, that is, the normal mode and the special mode. The normal mode is a mode in which importance is attached to transmission and reception, which is a basic function of the facsimile apparatus, and the priority of these processes is set high. On the other hand, the special mode is a mode in which the importance of data transfer (output) by the Centronics interface is increased, and the priority of the function (that is, channel 4) is set to the next highest level after image reading. . When data is output to the personal computer 16 using the Centronics interface, the communication method is determined in advance by exchanging data with the personal computer 16 before outputting the data.
When a normal communication method using a method such as handshake is selected, there is no problem even if the DMA transfer is performed in the normal mode. However, when sending data using a high-speed communication method that does not use a method such as handshake, the priority of the function (channel 4) is set high, that is, the special mode is set and DMA transfer is performed. There is a need. Therefore, when such a high speed communication method is selected, the CP
After switching the mode (switching from the normal mode to the special mode) by U6, the corresponding channel 4 is set to the DMA activated state.

First, the operation in the normal mode will be described. Now, if there is a DMA request for channel 2 only, the DMA request signal S2 becomes "1". The sampling circuit 8a samples this and supplies the signal of "1" to the channel determination circuit 8 and the OR circuit 7. OR
The circuit 7 sends a bus release request signal (“1”) to the CPU 6.
Supply. The OR circuit 7 is provided to output a bus release request signal to the CPU 7 when there is a DMA request on at least one channel. CPU6
In response to this, the bus releases the bus and supplies a confirmation signal indicating that the bus has been released to the DMA processing circuit 9. Also,
The channel determination circuit 8 uses the DM corresponding to the channel 2.
It is detected that the A request signal S2 is "1", and the signal line corresponding to channel 2 among the seven signal lines (corresponding to each channel) connected to the DMA processing circuit 9 is set to "1". . In response to this, the DMA processing circuit 9 causes the CPU between the recording device 14 corresponding to the channel 2 and the RAM 1 to operate.
A DMA process is performed to transfer data without going through 6.
When the data transfer is completed, the DMA processing circuit 9 passes the right to use the bus to the CPU 6, and the CPU 6 uses the bus 20 to execute the processing. With this, 1 cycle of DMA
The process ends. It should be noted that, in reality, the amount of data transferred by one cycle of DMA processing is small, so the recording device 1
The DMA request signal S2 of the channel 2 is repeatedly issued until the recording of the required amount by 4 is completed, and a plurality of cycles of DMA processing are performed to complete the recording of one original.

Next, processing in the normal mode when a plurality of channels are in an activated state and DMA requests corresponding to the plurality of channels are simultaneously generated will be described. Now, it is assumed that data transfer by the DMA of channel 3 is being executed and data is being input from the personal computer 16 via the Centronics interface 15. In this case, the channel 3 is in the activated state and the DMA request signal S3 of the channel 3 is repeatedly input to the channel determination circuit at a predetermined timing. Here, when the user sets a document and instructs transmission, channel 1 corresponding to the document reading device 12 is activated, and the DMA request signal S1 of channel 1 is sampled by the sampling circuit 8a It is input to the decision circuit 8. Therefore, the channel determination circuit 8
Two DMA request signals S1 and S3 may be input at the same sampling timing of the sampling circuit 8a. The channel determination circuit 8 outputs a signal indicating the channel with the higher priority to the DMA processing circuit 9 based on a predetermined priority (see FIG. 2).
In this case, the DMA request of channel 1 is accepted and D
A signal designating channel 1 is supplied to the MA processing circuit 9. In response to this, the DMA processing circuit 9 transfers data by DMA between the image reading device 12 and the RAM 1. When the 1-cycle DMA processing of the channel 1 is completed, the DMA processing circuit 9 continuously executes the 1-cycle DMA processing of the channel 3. In this way, a plurality of DMAs are sampled at the same sampling timing of the sampling circuit 8a.
When request signals are input, DMA processing is executed for those requests in descending order of priority.

Until the reading of the document inserted by the user is completed, channel 1 is in the activated state, and the DMA request of channel 1 is repeatedly output. Therefore, during this period, the DMA requests of channel 1 and channel 3 are repeatedly output. Since the timing of issuing the DMA request for channel 1 and the timing of issuing the DMA request for channel 3 are not always the same, when the timings of both DMA request signals are not in the same sampling period, either DMA request is responded to. DMA processing is executed. On the other hand, when the DMA request signals of both channels overlap in the same sampling period, the DMA processing for each request is executed in the order according to the priority as described above.

Next, the operation in the special mode will be described. The special mode described below is a mode that places importance on the data output processing by the Centronics interface, and when the data output processing by the high-speed communication method is selected, the normal mode is switched to the special mode. In the special mode, when the DMA requests for a plurality of channels overlap within the same sampling period, the channel determination circuit 8 determines the priority of the plurality of channels according to the priority of the special mode (see FIG. 2). DMA processing is performed from the higher channel. For example, it is assumed that the recording operation by the recording device 14 is currently being executed. That is, the channel 2 DMA request signal S2 is repeatedly input to the channel determination circuit 8 at a predetermined timing, and the DMA processing circuit 9 causes the recording device 1 to operate.
Data transfer between RAM 4 and RAM 1 is performed by DMA processing. Here, PC 1 corresponding to channel 4
It is assumed that the DMA data transfer to 6 has started. Then, the DMA request signals S2 and S4 of the channels 2 and 4 may be input to the channel determination circuit 8 within the same sampling period. In the special mode, as shown in FIG. 2, since the data output by the Centronics interface has a higher priority than the recording operation, the channel determination circuit 8 first executes the DMA processing of the channel 4 for one cycle according to the priority, and continues. Then, the DMA processing of channel 2 is executed for one cycle.

The reason why the data transfer to the personal computer 16 is prioritized is as follows in more detail.
Usually, data transmission is done by handshake etc.
Generally, it is performed while synchronizing the transmitting side and the receiving side. However, in the case of performing high-speed communication, it is possible to perform a test transmission in advance to determine a transmittable speed, and thereafter perform transmission at the determined speed without handshaking. In such a case, if the data transmission cannot be continued at the determined speed, the data will be interrupted on the way. In such a case, the transmission of data is set to a higher priority than a relatively important operation such as recording. Of course, if it is necessary to increase the priority order for any other reason, the order may be appropriately changed accordingly.

As described above, according to the present invention, when DMA requests of a plurality of channels overlap in time,
The priority for determining one request to be accepted can be changed according to the actual operation mode of the system. Therefore, even when the importance of each operation is different in each set mode, it is possible to perform each process in the priority order that matches the importance in each mode. As a result, it is possible to perform each process without trouble, especially in a system that performs a plurality of processes in parallel in time.

In the above description, the case where the channel determining circuit is constituted by the logic circuit which selects the input signal according to the priority is shown, but instead, the memory storing the priority and the dedicated CPU are used. It is also possible. That is, the priority order is stored in the memory for each mode, and when a plurality of DMA request signals are input at the same sampling timing, the CPU refers to the contents of the memory to determine the execution order of the DMA processing. You may decide.

In the above description, the case where two modes are set has been described, but it is of course possible to adopt more modes and set different priorities for each.

[0032]

According to the first aspect of the present invention, the channel determination circuit determines one channel to be subjected to the DMA processing in accordance with the priority order determined for each operation mode of the system. DMA of multiple channels according to the optimum priority according to the changing operation mode
It is possible to execute processing, and it is possible to maximize the capacity of the system.

According to the second aspect of the present invention, since the priority order is determined according to the importance of the processing of the system,
It is possible to determine the channel for performing the DMA processing based on the optimum priority.

According to the third aspect of the invention, since the channel is determined by the logical operation, it is not necessary to provide a special memory. According to the invention described in claim 4, since the storage device stores the priority order, it is easy to change the priority order.

According to the fifth aspect of the present invention, since the channel determination circuit receives the DMA processing request signal sampled by the sampling circuit, it is easy to detect the DMA processing request signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a control unit of a facsimile apparatus according to an embodiment of the present invention and a relationship with an input / output device.

FIG. 2 is a diagram showing an example of processing of each channel of DMA and setting of its priority order.

[Explanation of symbols]

 1 ... RAM 2 ... ROM 6 ... CPU 8 ... Channel determination circuit 9 ... DMA processing circuit 10 ... Information compression / decoding unit

Claims (5)

[Claims] 1. A DMA controller having a plurality of channels, which is provided in a system operating in a plurality of operation modes, receives a DMA processing request signal corresponding to the plurality of channels, and receives one of the plurality of channels. A channel determination circuit that determines which channel to perform a DMA process on, and a DMA processing circuit that performs a DMA process on the channel determined by the channel determination circuit. A DMA controller characterized by determining one channel based on a priority order determined for each operation mode of the system. 2. The DMA controller according to claim 1, wherein the priority order is determined according to the importance of processing of the system corresponding to the channel. 3. The DMA controller according to claim 1, wherein the channel determination circuit includes a logical operation circuit that performs a logical operation according to the priority order. 4. The DMA controller according to claim 1, wherein the channel determination circuit has a storage device that stores the priority order for each of the operation modes. 5. The DMA controller according to claim 1, further comprising a sampling circuit that samples the DMA processing request signal at a predetermined cycle and supplies the sampled signal to the channel determination circuit.