JPH09305490A - Microprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the performance of an instruction cache by preventing a capacity conflict of a microprocessor system which has the instruction cache. SOLUTION: A counter 5 is provided between a CPU 1 and the instruction cache 2. The CPU 1 generates a cache address information signal S1 each time it accesses the instruction cache 2, and consequently the value of the counter 5 is increased by one. Further, the CPU 1 generates a branch generation information signal S2 each time a subroutine call is generated or branching in a minus direction is established, and consequently the counter 5 is initialized to the number of entries, e.g. 4. Further, when the value of the counter 5 is 0, the counter 5 generates a caching function stop signal S3 to the instruction cache 2 to stop the function of the instruction cache 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor system having an instruction cache.

[0002]

2. Description of the Related Art In recent years, in a microprocessor system, a cache memory is used in order to improve the performance. This cache memory often has a small capacity of 1 Kbyte to 4 Kbyte due to the trade-off between manufacturing cost and performance accompanying the increase in chip area. FIG. 3 is a block circuit diagram showing a conventional microprocessor having a small capacity instruction cache. In FIG. 3, 1
Is a CPU, and 2 is a direct map instruction cache with four entries. The CPU 1 and the instruction cache 2 are connected by the address bus 3 and the data bus 4.

The operation of the microprocessor system shown in FIG. 3 will be described with reference to FIGS. Note that FIG. 4 is an example of a program having a loop, and FIG. 5 is a diagram showing the transition of the contents of the instruction cache 2. When the operation of the CPU 1 enters the loop portion of the program of FIG. 4, instructions A, B, C and D are sequentially fetched from the main memory (not shown), loaded into the instruction cache 2 and executed (step 50).
1, 502, 503, 504). Here, since the instruction cache 2 is a direct map, the entry in which the instruction is placed is determined by the address of the instruction to be fetched.
In the state of step 504, all the entries in the instruction cache 2 will be filled.

Next, the instruction E from the main memory,
F, G and H are sequentially fetched and executed (step 50).
5, 506, 507, 508). In this case, since all the entries in the instruction cache 2 are filled, the instruction cache 2 is replaced, and the instructions A, B, C and D are replaced.
Are sequentially erased from the entries in the instruction cache 2.

Next, after executing the instruction H which is a branch instruction, the instruction A is executed again. In this case, step 5
The instruction A has already been loaded into the instruction cache 2 at 01, but has been replaced by the instruction E at step 505. Therefore, the instruction A is fetched again from the main memory and loaded into the instruction cache 2 (step 50).
9). When the instructions B, C, ... Are subsequently executed, similarly, the instructions B, C, ... Are fetched again from the main memory and loaded into the instruction cache 2 (step 510 and after).

[0006]

As described above, when a program having a loop is executed in a microprocessor system having a small capacity instruction cache, all instructions are fetched from the main memory even though the instruction cache is used. That is, there is a problem that capacity competition occurs and the performance of the instruction cache is canceled. Even when the instruction cache has a set associative structure, there is no change in writing in the first half of the loop after the set is used up, so there is a similar problem. Therefore, it is an object of the present invention to improve the performance of the instruction cache by preventing the capacitive contention of the microprocessor system having the instruction cache.

[0007]

In order to solve the above problems, the present invention provides a CPU, an instruction cache, and a counting means for storing the number of refillable entries in the instruction cache between the instruction cache and the CPU. To provide. The CPU sends a cache access notification signal to the counting means for each access of the instruction cache to decrement the value of the counting means. Further, the CPU sends a branch occurrence notification signal to the counting means to initialize the counting means when a subroutine call or a branch in the negative direction is established. further,
When the value of the counting means is 0, the counting means sends a cache function stop signal to the instruction cache to stop the function of the instruction cache. The counting means may be of an increment type. That is, by limiting the number of times of cache refilling, when a program having a loop is executed, the cache function is invalidated when the instruction cache becomes full to improve the performance.

[0008]

1 is a block diagram showing an embodiment of a microprocessor system according to the present invention, in which a counter 5 is added to the constituent elements of FIG. The counter 5 receives the cache access notification signal S1 and the branch occurrence notification signal S2 from the CPU 1, and also generates a cache function stop signal S3 to the instruction cache 2. Here, the CPU 1 generates the cache access notification signal S1 each time the instruction cache 2 is accessed, and as a result, the value of the counter 5 is decremented by 1. Further, the CPU 1 generates a branch occurrence notification signal S2 each time a subroutine call or a branch in the negative direction is established, and as a result, the counter 5 is initialized and the value of the counter 5 is set to the number of entries, here, 4 It further,
When the value of the counter 5 is 0, the counter 5 issues a cache function stop signal S3 to the instruction cache 2 to stop the function of the instruction cache 2.

The operation of the microprocessor system shown in FIG. 1 will be described with reference to FIGS. 2 is a diagram showing the transition of the contents of the instruction cache 2. The value of the counter 5 is set to the initial value 4. When the operation of the CPU 1 enters the loop portion of the program shown in FIG. 4, instructions A, B, C and D are sequentially fetched from a main memory (not shown), loaded into the instruction cache 2 and executed (step 20).
1, 202, 203, 204). Here, since the instruction cache 2 is a direct map, the entry in which the instruction is placed is determined by the address of the instruction to be fetched.
In each of steps 201, 202, 203, and 204, since the CPU 1 generates the cache access notification signal S1, the value of the counter 5 decreases to 3, 2, 1, 0. As a result, in the state of step 204, all the entries of the instruction cache 2 are filled, and thereafter,
The replacement of the instruction cache 2 does not occur due to the generation of the cache function stop signal S3 of the counter 5.

Next, the instruction E is sent from the main memory.
F, G, H are sequentially fetched and executed (step 20)
5, 206, 207, 208). In this case, the replacement of the cache 2 does not occur, so the instructions A, B, C, D
Remains in the instruction cache 2.

Next, after executing the instruction H which is a branch instruction, the instruction A is executed again. In this case, step 2
Then, the instruction A is already loaded in the instruction cache 2. Therefore, a so-called cache hit occurs (step 509). When the instructions B, C and D are subsequently executed, the instructions B, C and D are executed in steps 202, 203 and 2 respectively.
Since it is loaded in the instruction cache 2 at 04, a cache hit occurs (step 510 and after). afterwards,
When executing the instructions D, E, F, G, H, the instructions D, E, F, G, H must be fetched from the main memory and loaded into the instruction cache 2, but this is the same as the conventional example. .

Although the counter 5 is configured as a decrement counter in the embodiment of the invention described above, it may be configured as an increment counter. In this case, the value of the counter 5 is incremented by 1 each time the cache access notification signal S1 is received, and the counter 5 is received each time the branch occurrence notification signal S2 is received.
Is cleared, and when the value of the counter 5 is a predetermined value, for example, 4, the counter 5 issues a cache function stop signal S3 to the instruction cache 2 to stop the function of the instruction cache 2.

[0013]

As described above, according to the present invention, it is possible to prevent capacitive contention that occurs in a program loop or subroutine call, and thus improve the performance of the instruction cache.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a microprocessor system according to the present invention.

FIG. 2 is a diagram showing the contents of an instruction cache for explaining the operation of the microprocessor system of FIG.

FIG. 3 is a block circuit diagram showing a conventional microprocessor system.

FIG. 4 is a float chart showing an example of a program having a loop.

5 is a diagram showing the contents of an instruction cache for explaining the operation of the microprocessor system of FIG.

[Explanation of symbols]

 1 ... CPU 2 ... Instruction cache 3 ... Address bus 4 ... Data bus 5 ... Counter S1 ... Cache access notification signal S2 ... Branch occurrence notification signal S3 ... Cache function stop signal

Claims (2)

[Claims] 1. A CPU (1), an instruction cache (2) connected to the CPU (1) by a bus (3, 4), and the instruction cache can be refilled between the instruction cache and the CPU. A counting means (5) for storing the number of different entries, and the CPU sends a cache access notification signal (S1) to the counting means for each access of the instruction cache to decrement the value of the counting means. , The CPU sends a branch occurrence notification signal (S2) to the counting means to initialize the counting means when a subroutine call or a branch in the minus direction is established, and when the value of the counting means is 0, The counting system sends a cache function stop signal (S3) to the instruction cache to stop the function of the instruction cache. 2. A CPU (1), an instruction cache (2) connected to the CPU (1) by a bus (3, 4), and an instruction cache filled between the instruction cache and the CPU. Counting means (5) for storing the number of entries, the CPU sends a cache access notification signal (S1) to the counting means for each access of the instruction cache to increment the value of the counting means, The CPU sends a branch occurrence notification signal (S2) to the counting means to clear the counting means when a subroutine call or a branch in the minus direction is established, and when the value of the counting means is a predetermined value, the counting is performed. The means is a cache function stop signal (S
3) A microprocessor system for sending out 3) to the instruction cache to stop the function of the instruction cache.