JPH09298249A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH09298249A JPH09298249A JP10920596A JP10920596A JPH09298249A JP H09298249 A JPH09298249 A JP H09298249A JP 10920596 A JP10920596 A JP 10920596A JP 10920596 A JP10920596 A JP 10920596A JP H09298249 A JPH09298249 A JP H09298249A
- Authority
- JP
- Japan
- Prior art keywords
- cost
- semiconductor device
- resin
- semiconductor chip
- memory cells
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Non-Volatile Memory (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はプラスチックパッケ
ージタイプのＥＰＲＯＭ(消去・書込みタイプのＲＯＭ)
等の紫外線照射窓を有する半導体装置(以下半導体装置
という)に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plastic package type EPROM (erasing / writing type ROM).
And a semiconductor device having an ultraviolet irradiation window (hereinafter referred to as a semiconductor device).
【０００２】[0002]
【従来の技術】以下、従来の半導体装置の一例であるＥ
ＰＲＯＭについて図面を参照しつつ説明する。図４はそ
の構成を示すものであり、セラミックス１とその周囲に
設けたリード２よりなるパッケージベースに半導体チッ
プ３を接着し、更に、この半導体チップ３内の電極パッ
ド３Pとリード２を金等の素材からなる金属細線４によ
り接続した上、低融点ガラス等の接着剤５により蓋体と
なるリッド(またはキャップ)６を接着して密封化したも
のである。なお、半導体チップ３内のメモリセル部３M
と対応する位置の前記リッド６には紫外線を透過する例
えばガラス材よりなる窓部７が設けられている。2. Description of the Related Art The following is an example of a conventional semiconductor device, E.
The PROM will be described with reference to the drawings. FIG. 4 shows the structure thereof. The semiconductor chip 3 is bonded to a package base composed of the ceramics 1 and the leads 2 provided around the ceramics 1, and further, the electrode pads 3 P and the leads 2 in the semiconductor chip 3 are gold-plated. A metal wire 4 made of a material such as the above is used for connection, and a lid (or cap) 6 serving as a lid is adhered and sealed by an adhesive 5 such as low melting glass. The memory cell unit 3 M in the semiconductor chip 3
A window portion 7 made of, for example, a glass material that transmits ultraviolet rays is provided in the lid 6 at a position corresponding to.
【０００３】このような構成により、このＥＰＲＯＭ
は、パッケージ組立て完了後であっても窓部７より半導
体チップ３内のメモリセル部３Mに紫外線を照射させる
ことにより、メモリセル部３Mに書き込まれているメモ
リの内容を消去することができるように構成されてい
る。With this structure, the EPROM
Can erase the contents of the memory written in the memory cell portion 3 M by irradiating the memory cell portion 3 M in the semiconductor chip 3 with ultraviolet rays through the window portion 7 even after the package assembly is completed. It is configured to be able to.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら上記従来
の構成では、その構成部品、例えば、パッケージベース
となるセラミックス材、接着剤である低融点ガラス、ガ
ラス材を含むリッド等いずれも材料コストが高く、ま
た、組立プロセスも複雑で量産性に欠ける等の問題点を
有している。However, in the above conventional structure, the component parts thereof, for example, the ceramic material serving as the package base, the low melting point glass serving as the adhesive, the lid including the glass material, etc., all have a high material cost. Further, there is a problem that the assembly process is complicated and the mass productivity is insufficient.
【０００５】本発明は上記従来の問題点を解決するもの
であり、パッケージ組立て完了後も半導体チップ内のメ
モリーセル部に紫外線を照射できる低コスト、簡易組立
プロセスの半導体装置を提供することを目的とする。The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device having a low cost and a simple assembling process capable of irradiating the memory cell portion in the semiconductor chip with ultraviolet rays even after the completion of the package assembling. And
【０００６】[0006]
【課題を解決するための手段】この目的を達成するため
に本発明の半導体装置は、樹脂封止プラスチックパッケ
ージされた半導体チップと、少なくとも前記半導体チッ
プ表面に形成されたメモリセル部を露出させるよう前記
プラスチックパッケージに設けられた窓部と、前記窓部
に充填された紫外線透過のプラスチック材より構成した
ものである。In order to achieve this object, a semiconductor device of the present invention is configured to expose a semiconductor chip packaged in a resin-sealed plastic package and at least a memory cell portion formed on the surface of the semiconductor chip. A window portion provided in the plastic package and an ultraviolet-transparent plastic material filled in the window portion are included.
【０００７】本発明によれば、低コストである樹脂封止
プラスチックパッケージの使用と、窓部への紫外線透過
性のプラスチック材の充填により低コスト、簡易組立プ
ロセスの半導体装置を提供することが可能となる。According to the present invention, it is possible to provide a low-cost and simple assembly process semiconductor device by using a low-cost resin-sealed plastic package and filling a window portion with an ultraviolet-transparent plastic material. Becomes
【０００８】[0008]
【発明の実施の形態】以下本発明の実施の形態について
図面を参照しながら説明する。なお、前記従来のものと
同一、またはこれと同等の部分については同一符号を用
いるものとする。図１(a)，(b)，(c)，(d)は本発明の実
施の形態における半導体装置の一例であるＤＩＰ(dual
inline package)タイプのプラスチックパッケージに納
められたＥＰＲＯＭの構成とその製造プロセスを示して
いる。図１(a)において、２はリードフレーム、３はリ
ードフレーム２の間のアイランド部８上に接着した半導
体チップで、この半導体チップ３内の電極パッド３Pと
リードフレーム２は金等の素材からなる金属細線４によ
り接続されている。９はプラスチックモールド樹脂で、
リードフレーム２，半導体チップ３，金属細線４を一体
にパッケージングしている。Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the same reference numerals are used for the same parts as those of the above-mentioned conventional device or parts equivalent thereto. 1 (a), (b), (c), and (d) are DIP (dual
The structure of an EPROM housed in an inline package type plastic package and its manufacturing process are shown. In FIG. 1 (a), 2 is a lead frame, 3 is a semiconductor chip adhered on the island portion 8 between the lead frames 2, and the electrode pads 3 P in the semiconductor chip 3 and the lead frame 2 are made of a material such as gold. They are connected by a thin metal wire 4. 9 is a plastic mold resin,
The lead frame 2, the semiconductor chip 3, and the thin metal wire 4 are integrally packaged.
【０００９】このようなプラスチックパッケージは低コ
スト量産に適した構成であり、本発明はこの図１(a)に
示す構成を基本として、メモリセル部３Mに紫外線を照
射できる低コスト、簡易組立プロセスのＥＰＲＯＭを形
成するものである。まず、図１(b)に示すように、プラ
スチックパッケージ上方に配置されたノズル10より硫酸
等のプラスチックモールド樹脂９を溶解する溶融薬品11
を滴下してメモリセル部３Mの上方を覆っているプラス
チックモールド樹脂９を溶解し、図１(c)に示すように
窓部12を形成する。この際、半導体チップ３内の電極パ
ッド３Pにこの溶融薬品11が付着するとその電気特性の
劣化を招くので、電極パッド３Pを覆っている部分のプ
ラスチックモールド樹脂９は絶対に溶融させてはならな
い。次に、図１(d)に示すように、この窓部12に紫外線
透過性のプラスチック材13を充填し、メモリセル部３M
の表面を外部環境あるいは機械的ストレスより保護する
よう構成する。図２は半導体チップ３の表面状態を示し
ており、メモリセル部３Mとメモリコントロール回路３C
を囲むように電極パッド３Pが配置されるインターフェ
イス部３Iが設けられている。Such a plastic package has a structure suitable for low-cost mass production, and the present invention is based on the structure shown in FIG. 1 (a) and is a low-cost, simple assembly capable of irradiating the memory cell portion 3M with ultraviolet rays. It forms the EPROM of the process. First, as shown in FIG. 1 (b), a molten chemical 11 that dissolves a plastic molding resin 9 such as sulfuric acid from a nozzle 10 arranged above the plastic package.
Is dropped to dissolve the plastic mold resin 9 covering the upper portion of the memory cell portion 3 M , and the window portion 12 is formed as shown in FIG. 1 (c). At this time, if the molten chemical 11 adheres to the electrode pad 3 P in the semiconductor chip 3, the electric characteristics of the molten chemical 11 are deteriorated. Therefore, the plastic mold resin 9 covering the electrode pad 3 P should never be melted. I won't. Next, as shown in FIG. 1 (d), the window portion 12 is filled with an ultraviolet-transparent plastic material 13, and the memory cell portion 3 M
The surface of the is configured to protect it from the external environment or mechanical stress. FIG. 2 shows the surface state of the semiconductor chip 3, which includes a memory cell section 3 M and a memory control circuit 3 C.
An interface portion 3 I in which the electrode pad 3 P is arranged is provided so as to surround the.
【００１０】このようにして完成したＥＰＲＯＭは、窓
部への紫外線照射によるメモリセル部３Mのメモリ内容
の消去が可能で、低コスト、簡易組立プロセスという所
期の目的を達成しうるものである。なお、ＤＩＰタイプ
のプラスチックパッケージとして完成した本実施形態に
よるＥＰＲＯＭの外観を図３に斜視図として示すが、本
発明はこのＤＩＰタイプの外、ＱＦＰ(quad flat packa
ge)タイプ，ＳＯＰ(small outline package)タイプ等の
パッケージへの展開も可能である。The EPROM thus completed is capable of erasing the memory contents of the memory cell section 3 M by irradiating the window with ultraviolet rays, and can achieve the intended purpose of low cost and simple assembling process. is there. The perspective view of the EPROM according to the present embodiment completed as a DIP type plastic package is shown in a perspective view in FIG.
ge) type, SOP (small outline package) type and other packages are also possible.
【００１１】[0011]
【発明の効果】本発明によれば、低コストである樹脂封
止プラスチックパッケージの使用と、メモリセル部上に
設けた窓部への紫外線透過性のプラスチック材の充填に
より半導体装置としての低コスト化、組立プロセスの簡
易化を図ることができるという有利な効果が得られる。According to the present invention, the use of a low cost resin-sealed plastic package and the filling of the window provided on the memory cell portion with an ultraviolet-transparent plastic material reduce the cost of the semiconductor device. It is possible to obtain an advantageous effect that the simplification and simplification of the assembling process can be achieved.
【図１】本発明の半導体装置の実施の形態におけるＥＰ
ＲＯＭの構成と、その組立プロセスを示す断面図であ
る。FIG. 1 is an EP in an embodiment of a semiconductor device of the present invention.
It is sectional drawing which shows the structure of ROM, and its assembly process.
【図２】本発明の半導体装置の実施の形態におけるＥＰ
ＲＯＭ内の半導体チップ表面の構成を示す平面図であ
る。FIG. 2 is an EP in an embodiment of a semiconductor device of the present invention.
It is a top view showing composition of the semiconductor chip surface in ROM.
【図３】本発明の半導体装置の実施の形態におけるＥＰ
ＲＯＭの外観斜視図てである。FIG. 3 is an EP in an embodiment of a semiconductor device of the present invention.
FIG. 3 is an external perspective view of a ROM.
【図４】従来のＥＰＲＯＭの構成を示す断面図である。FIG. 4 is a sectional view showing a configuration of a conventional EPROM.
２…リードフレーム、 ３…半導体チップ、 ３M…メ
モリセル部、 ３P…電極パッド、 ３C…メモリコント
ロール回路、 ３I…インターフェイス部、 ４…金属
細線、 ８…アイランド部、 ９…プラスチックモール
ド樹脂、 10…ノズル、 11…溶融薬品、 12…窓部、
13…紫外線透過性のプラスチック材。2 ... Lead frame, 3 ... Semiconductor chip, 3 M ... Memory cell part, 3 P ... Electrode pad, 3 C ... Memory control circuit, 3 I ... Interface part, 4 ... Metal fine wire, 8 ... Island part, 9 ... Plastic mold Resin, 10 ... Nozzle, 11 ... Molten chemical, 12 ... Window,
13 ... UV transparent plastic material.
Claims (1)
半導体チップと、少なくとも前記半導体チップ表面に形
成されたメモリセル部を露出させるよう前記プラスチッ
クパッケージに設けられた窓部と、前記窓部に充填され
た紫外線透過性のプラスチック材を備えたことを特徴と
する半導体装置。1. A semiconductor chip packaged in a resin-sealed plastic package, a window portion provided in the plastic package so as to expose at least a memory cell portion formed on the surface of the semiconductor chip, and the window portion is filled. A semiconductor device comprising an ultraviolet-transparent plastic material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10920596A JP3054929B2 (en) | 1996-04-30 | 1996-04-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10920596A JP3054929B2 (en) | 1996-04-30 | 1996-04-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09298249A true JPH09298249A (en) | 1997-11-18 |
| JP3054929B2 JP3054929B2 (en) | 2000-06-19 |
Family
ID=14504272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10920596A Expired - Fee Related JP3054929B2 (en) | 1996-04-30 | 1996-04-30 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3054929B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002093642A2 (en) * | 2001-05-11 | 2002-11-21 | Melexis Nv | Integrated sensor packaging and methods of making the same |
| US6762077B2 (en) | 2001-05-11 | 2004-07-13 | Melexis Nv | Integrated sensor packages and methods of making the same |
| US7939901B2 (en) | 2007-10-15 | 2011-05-10 | Panasonic Corporation | Optical device for reducing disturbance light and manufacturing method thereof |
-
1996
- 1996-04-30 JP JP10920596A patent/JP3054929B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002093642A2 (en) * | 2001-05-11 | 2002-11-21 | Melexis Nv | Integrated sensor packaging and methods of making the same |
| WO2002093642A3 (en) * | 2001-05-11 | 2003-03-13 | Melexis Nv | Integrated sensor packaging and methods of making the same |
| US6762077B2 (en) | 2001-05-11 | 2004-07-13 | Melexis Nv | Integrated sensor packages and methods of making the same |
| US6917089B2 (en) | 2001-05-11 | 2005-07-12 | Melexis Nv | Integrated sensor packages and methods of making the same |
| US7060216B2 (en) | 2001-05-11 | 2006-06-13 | Melexis, Nv | Tire pressure sensors and methods of making the same |
| US7939901B2 (en) | 2007-10-15 | 2011-05-10 | Panasonic Corporation | Optical device for reducing disturbance light and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3054929B2 (en) | 2000-06-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6353257B1 (en) | Semiconductor package configuration based on lead frame having recessed and shouldered portions for flash prevention | |
| JP3630447B2 (en) | Manufacturing method of solid-state imaging device | |
| US4710797A (en) | Erasable and programable read only memory devices | |
| US4766095A (en) | Method of manufacturing eprom device | |
| US6815808B2 (en) | Hollow airtight semiconductor device package | |
| US6643919B1 (en) | Method of fabricating a semiconductor device package having a core-hollowed portion without causing resin flash on lead frame | |
| JPH09298249A (en) | Semiconductor device | |
| JPH049381B2 (en) | ||
| JPS63133653A (en) | Optically erasable semiconductor storage device | |
| KR920010849B1 (en) | Method of fabricating for erasable programmable rom device | |
| JPS6150352A (en) | Semiconductor device | |
| JPH0312467B2 (en) | ||
| JPS584952A (en) | Semiconductor device | |
| JP2508067Y2 (en) | Package for storing semiconductor devices | |
| JPS63257251A (en) | Semiconductor device | |
| JPS6136957A (en) | Resin sealed type semiconductor integrated circuit | |
| JPH0723961Y2 (en) | Package for storing semiconductor devices | |
| JPH11340480A (en) | Plastic package | |
| JPS6083337A (en) | Manufacture of semiconductor device | |
| JPH0273663A (en) | Hybrid integrated circuit device | |
| JPS61115339A (en) | Eprom device | |
| JPS60171749A (en) | Semiconductor memory device | |
| JPS5759364A (en) | Semiconductor device | |
| JPS60211962A (en) | Semiconductor device | |
| JPH06244314A (en) | Plastic package semiconductor device and production |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080414 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 9 Free format text: PAYMENT UNTIL: 20090414 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 10 Free format text: PAYMENT UNTIL: 20100414 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 11 Free format text: PAYMENT UNTIL: 20110414 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120414 Year of fee payment: 12 |
|
| LAPS | Cancellation because of no payment of annual fees |