JPH09294146A - Automatic gain control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce level fluctuation and an error by comparing a mean value of an input signal with a reference value, a maximum value and a minimum value so as to classify the input signal into five ranks, and adjusting and correcting a gain signal accordingly so as to reduce a gain control time with a small scale circuit. SOLUTION: I, Q components of a phase detection circuit are given to an input signal level arithmetic circuit 1, in which an input signal level of a demodulation section is calculated. Then an averaging circuit 2 is used to obtain a mean value and to eliminate the instantaneous effect of noise included in the reception signal and the result is given to a comparator circuit 3, where the mean value is compared with a reference value, a maximum value and a minimum value to classify the input signal into five ranks. An integration control circuit 4 executes the processing corresponding to them to an integration circuit 6 and provides an output of an automatic gain signal AGC to a variable amplifier. The reception level of five ranks 1-5 classified by the comparator circuit 3 corresponds to the reference value, the maximum value and the minimum value, which are used to apply adjustment and correction to a gain signal. Thus, the gain control time is reduced to reduce level fluctunation and error.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control circuit (hereinafter referred to as an AGC circuit), and more particularly to a demodulation section of a QPSK (Quadrature Phase Shift Keying) receiving device in a digital satellite broadcast receiving system, a digital radio telephone system or the like. It relates to an AGC circuit used.

[0002]

2. Description of the Related Art QPSK is a modulation system capable of taking four phase points and is used for satellite communication, mobile phones and the like. QPSK
Then, two binary digital code bits are grouped together, for example, (00) for the 0 phase, (01) for the π / 2 phase, and (1 for the π phase.
0) Allocate (11) to 3π / 2 phase. Therefore, the amount of information that can be transmitted with a constant bandwidth is BPSK.
It is twice as much as (Binary Phase Shift Keying).

By the way, in QPSK, the phase changes abruptly for each symbol to be transmitted, so that if it is transmitted as it is, the output spectrum will be widened. To prevent this, realize a narrow-band output spectrum, and prevent intersymbol interference on the receiving side, this is a combination of root Nyquist filters in which the transmission / reception total transmission characteristics are equally divided among the transmission / reception filters. So-called roll-off filters are provided on the transmitting side and the receiving side. As a result, frequency utilization efficiency can be made equal to or higher than that of analog transmission.

QPS passing through a roll-off filter on the transmission side
The amplitude of the output waveform of K fluctuates greatly. For this reason,
In the QPSK receiver, it is necessary to accurately receive the QPSK signal as an amplitude-modulated analog signal. However, the transmission quality of high-frequency radio signals and the received electric field strength are often greatly affected by external conditions such as the weather, geographical position, and the effects of interference waves, and it may not always be possible to expect stable reception. Many. Therefore, QPSK
In order to accurately demodulate the modulated data, the input signal must always be input to the demodulation circuit at a constant level so that saturation or lack of dynamic range does not occur for the received signal, A function to maintain a stable level is needed.

Conventionally, an analog gain adjusting circuit has been used as a circuit that performs such a function. However, the conventional analog gain adjusting circuit has a relatively large circuit scale, and there are many inconveniences such as the need for means and adjustment for preventing oscillation and noise.

On the other hand, if the gain is adjusted digitally, the circuit scale can be reduced, but the control step (the width of the variable gain performed at one time) becomes a problem. In digital gain adjustment, normally, when the level of the received signal is higher than the reference value, the gain is reduced by one step, and when the level of the received signal is lower than the reference value, the gain is increased by one step to adjust the gain. It is normal to do. In this way, when the control level is constant and the input level sticks to the maximum or minimum value of the input level, it takes too much time to control the gain if the value of this one step is small. Will end up.

FIG. 4 shows that when the value of one step is small,
FIG. 6 is a diagram showing a transition of a level change from a maximum value or a minimum value of an input level to a reference value by digital gain adjustment. On the other hand, if the value of this 1 step is too large, the time from the maximum value or the minimum value of the input level to reach the reference value becomes short, but the response to the level fluctuation after reaching the reference value becomes extreme, The level becomes unstable when the difference between the reference value and the input level becomes small. FIG. 5 shows the transition of the level change from the maximum value or the minimum value of the input level by digital gain adjustment to the reference value and the transition of the subsequent level change when the value of one step is large. It is the figure shown. From FIGS. 4 and 5, it is understood that it is difficult to set the control step for adjusting the gain in order to shorten the time required to control the gain and maintain the level stably.

[0008]

As described above, in the AGC circuit of the conventional QPSK receiver, if the circuit is configured in an analog manner, the circuit is expensive and tends to be large in scale. In the case of the configuration, there is a drawback that the control step becomes a problem.

The present invention solves this problem and can shorten the time required to control the gain while configuring the AGC circuit by a digital system having a relatively small circuit scale, and reduce the level fluctuation after the gain control is completed. It is an object to realize an AGC circuit for a QPSK receiver that can be used.

[0010]

In order to achieve the above object, the present invention is used in a QPSK receiver, and in an automatic gain control circuit for performing gain control by varying the gain of a variable amplifier circuit, QPSK receiver demodulation. Input signal level calculating means for calculating the input signal level from the demodulated data component of the section, averaging means for averaging the outputs of the input signal level calculating means, and comparison for comparing the output of the averaging means with a reference value, a maximum value and a minimum value. And a variable width of the gain setting value of the variable amplifying circuit according to the comparison result of the comparing means, when the output of the averaging means is equal to the maximum value and equal to or smaller than the minimum value, In other cases, the gain variable width setting means for setting a small value, and the gain setting means for integrating the variable width set by the gain variable width setting means with the previously set gain setting value and outputting the result. And wherein the Rukoto.

As a result, it is possible to provide an AGC circuit which can reduce the time required to control the gain and reduce the level fluctuation after the gain control is completed, while being constructed with a relatively small circuit scale.

[0012]

DETAILED DESCRIPTION OF THE INVENTION An AGC circuit according to the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a block diagram of an AGC circuit of the present invention. In FIG. 1, reference numeral 1 is an input signal level calculation circuit for calculating (I ² + Q ² ) from I (Inphase) component and Q (Quadrature) component of data input to obtain an input signal level, and 2 is an input signal level calculation circuit 1. The average value circuit, which calculates the average value by dividing the output of the average value circuit by adding the output of the average value circuit over a certain period of time, and the average value of the input signal level output from the average value circuit 2 is a reference value (Reference). Comparing circuit 4 for comparing with the integrating circuit 5 for adjusting the integrated value of the integrating circuit 5 at the next stage according to the output of the comparing circuit 3 It is an integrating circuit that integrates and newly holds.

FIG. 2 is a block diagram of an example of a differential detection type QPSK receiving apparatus in which the AGC circuit of the present invention shown in FIG. 1 is used. In FIG. 2, 11 is an antenna, 12 is a tuner circuit, 13 is a variable amplifier, 14 is a 1-symbol delay circuit, 15 and 17 are phase detection circuits, 16 is a π / 2 phase shift circuit, 18 and 19 are identification circuits, and 20. Is a parallel-serial conversion circuit, 2
Reference numeral 1 is an output circuit, 22 is a clock recovery circuit, and 23 is an AGC circuit of the present invention. The QPSK demodulation unit 30 is composed of 14 to 20 circuits.

The operation of this QPSK receiver will be described with reference to FIG. The radio frequency signal received by the antenna 11 is converted into a baseband signal by the tuner circuit 12. The baseband signal output from the tuner circuit 12 is input to the QPSK demodulation unit 30 via the variable amplifier 13. QP
The SK demodulator 30 obtains the phase difference between the received waves for one symbol, estimates the transmission phase difference based on this phase difference, and demodulates it into the transmitted two-bit data. As described above, since the reception wave itself one symbol before is used as the reference signal, the error rate characteristic is deteriorated as compared with the ideal synchronous detection, but it is less susceptible to the phase fluctuation due to fading.

That is, in the QPSK demodulation unit 30, the phase detection circuit 15 detects the current received wave and the received wave one symbol before.
The result of the phase detection in step S2 is taken as the Q component. Further, the result of phase detection by the phase detection circuit 17 from the phase of the current reception wave and the reception wave of one symbol before by π / 2 is taken as the I component. Then, the respective components are identified by the identification circuits 18, 19
Respectively, and discriminates either +1 or -1. Based on these discrimination results, the parallel-serial conversion circuit 20 outputs 2
Bit serial signals are sequentially created and output through the output circuit 21.

In the output circuit 21, when the object is a voice signal, the obtained digital signal is converted into an analog signal,
Output from the speaker. The clock reproduction circuit 22 reproduces the reference frequency signal from the reference signal included in the received wave.
The AGC circuit 23 converts the Q component and the I component from the QPSK demodulation unit 3
The gain of the variable amplifier 13 is adjusted by obtaining the 0 input signal level to stabilize the input signal level of the QPSK demodulation unit 30.

Next, the operation of the AGC circuit 23 will be described with reference to FIG. The I component that is the output of the phase shift detection circuit 17 and the Q component that is the output of the phase shift detection circuit 15 are input to the input signal level calculation circuit 1, and the input signal level calculation circuit 1 corresponds to the input signal level of the demodulation unit. (I ² + Q ² ) is calculated. The output of the input signal level calculation circuit 1 is first integrated by the averaging circuit 2 and then divided by the number of integrations to obtain an average value corresponding to the average level. The number of times of integration in the averaging circuit 2 is normally set to a power of 2. As a result, division can be realized by shifting the binary number of the integrated result by a digit. By such averaging, the influence of instantaneous noise included in the received signal can be removed.

The comparison circuit 3 compares the average value obtained by the averaging circuit 2 with the reference value, the maximum value and the minimum value. Here, it is assumed that the output (I ² + Q ² ) me of the averaging circuit 2 is 8 bits (0 to 255). Based on the comparison with the reference value in the comparison circuit 3, the demodulation unit input signal level is classified into the following five levels. Further, the integration control circuit 4 executes the corresponding processing on the integration circuit 6. Integrating circuit 5
Outputs a gain signal to the external variable amplifier 13. Here, it is assumed that the integrating circuit 6 sends a gain signal of 8 bits (0 to 255) to the variable amplifier 13.

The five stages classified by the comparison circuit 3 and the processing of the integration control circuit 4 corresponding to the five stages are as follows. Case 1 (I ² + Q ² ) me = maximum value (255) Gain signal −16 Case 2 (I ² + Q ² ) me ≦ a certain set minimum value Gain signal +16 Case 3 (I ² + Q ² ) me> reference value Gain signal −1 Case 4 (I ² + Q ² ) me <reference value Gain signal +1 Case 5 (I ² + Q ² ) me = reference value Gain signal ± 0

That is, in case 1, the variable amplifier 13 has a high reception level and is saturated, the input signal level of the demodulation section is also high, and the output (I ² + Q ² ) me of the averaging circuit 2 is 25.
In this case, the integration control circuit 4 subtracts 16 from the previous gain signal held by the integration circuit 5.

In case 2, the demodulator input signal level is low and the output (I ² + Q ² ) me of the averaging circuit 2 shows a certain minimum value, for example, a value smaller than 1 or 2. In this case, the integration control circuit 4 is integrated into the integration circuit 5
16 is added to the previous gain signal held by.

In case 3, the output of the averaging circuit 2 (I ² + Q
² ) When me is larger than the value set as the reference value of the demodulation unit input signal level, in this case, the integration control circuit 4 subtracts 1 from the previous gain signal held by the integration circuit 5.

In case 4, the output of the averaging circuit 2 (I ² + Q
² ) When me is smaller than the value set as the reference value of the demodulation unit input signal level, in this case, the integration control circuit 4 adds 1 to the previous gain signal held by the integration circuit 5.

In case 5, the output of the averaging circuit 2 (I ² + Q
² ) When me is equal to the value set as the reference value of the demodulation unit input signal level, in this case, the integration control circuit 4 holds the previous gain signal held by the integration circuit 5 as it is.

In this way, any processing according to the classification condition of the comparison circuit 3 is added to the previous gain signal to make it the current gain signal.

FIG. 3 is a diagram showing the transition of the level change from the maximum value or the minimum value of the input level to the reference value by the digital gain adjustment according to the present invention. As can be seen from this figure, according to the present invention, the AGC circuit rapidly changes the gain of the variable amplification circuit when the input signal level of the demodulator is stuck to the maximum value or the minimum value. Therefore, the time required to eliminate the stuck state is shortened.

When the demodulator input signal level deviates from the maximum value or the minimum value, the AGC circuit reduces the change width of the gain of the variable amplifier circuit. Therefore, fluctuations in the input signal level of the demodulator are stable within this small change width.

As described above, by changing the variable width of one-time control, that is, the control step, it is possible to shorten the time required to control the gain while configuring the AGC circuit by a digital system having a relatively small circuit scale. In addition, the level fluctuation can be reduced after the gain control is completed.

In the above description, the case where the present invention is applied to the AGC circuit of the differential detection type QPSK receiver has been described, but the application of the present invention is not limited to such an AGC circuit of the QPSK receiver. Instead, it can be used for any device in which gain control is performed digitally. Further, the output of the averaging circuit and the gain signal output from the integrating circuit have been described as 8 bits, but it goes without saying that other gain numbers can be used in the same manner.

[0030]

As described above, according to the present invention, the QPS
In an automatic gain control circuit used in a K receiver,
Input signal level calculating means for calculating the input signal level from the demodulated data component of the PSK receiving device demodulating section, averaging means for averaging the outputs of the input signal level calculating means, and the output of the averaging means for the reference value, the maximum value and the minimum value. Comparing means for comparing with the gain variable width setting means for setting the variable width of the gain setting value of the variable amplifier circuit according to the comparison result of the comparing means, and the gain previously set for the variable width set by the gain variable width setting means. A gain setting means for integrating and outputting the set value is provided. Then, the gain control means makes the variable width large in a state where the variable amplifier circuit is saturated or the output of the variable amplifier circuit is almost 0, and makes the variable width relatively small in other cases. To do so. In addition, the circuit is composed of digital circuits. In this way, by changing the variable width of one-time control, that is, the control step according to the conditions, the time required to control the gain is shortened while configuring the AGC circuit by a digital method with a relatively small circuit scale. In addition, it is possible to reduce the level fluctuation after the gain control is completed, and to realize stable reception with few errors.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an AGC circuit of the present invention.

FIG. 2 is a block diagram of a QPSK receiver in which the AGC circuit of the present invention is used.

FIG. 3 is an explanatory diagram showing a transition of level change due to gain adjustment of the AGC circuit of the present invention.

FIG. 4 is an explanatory diagram showing a transition of a level change due to a gain adjustment of a conventional AGC circuit (when a gain variable width is small).

FIG. 5 is an explanatory diagram showing a transition of a level change due to gain adjustment of a conventional AGC circuit (when the gain variable width is large).

[Explanation of symbols]

1 ... Input signal level calculation circuit, 2 ... Average value circuit, 3
…… Comparison circuit, 4 …… Integration control circuit, 5 …… Integration circuit,
11 ... Antenna, 12 ... Tuner circuit, 13 ... Variable amplifier, 14 ... 1 symbol delay circuit, 15, 17 ...
… Phase detection circuit, 16 …… π / 2 phase shift circuit, 18, 19
...... Identification circuit, 20 ...... parallel serial conversion circuit, 21 ...... output circuit, 22 ...... clock recovery circuit, 23 ...... AGC circuit, 30 ...... QPSK demodulation section.

Claims (3)

[Claims] 1. An automatic gain control circuit used in a QPSK receiver for varying a gain of a variable amplifier circuit to perform gain control, wherein an input signal level for calculating an input signal level from a demodulated data component of a demodulator of a QPSK receiver. Calculating means, averaging means for averaging the outputs of the input signal level calculating means, comparing means for comparing the output of the averaging means with a reference value, a maximum value and a minimum value, and the comparing means according to the comparison result of the comparing means. A gain variable width setting means for setting a variable width of a gain setting value of the variable amplifier circuit; and a gain setting means for integrating the variable width set by the gain variable width setting means with a previously set gain setting value and outputting it. An automatic gain control circuit, comprising: 2. The gain variable width setting means takes a large variable width when the output of the averaging means is equal to the maximum value and equal to or smaller than the minimum value,
The automatic gain control circuit according to claim 1, wherein the variable width is reduced in other cases. 3. The input signal level calculating means, the averaging means, the comparing means, the gain variable width setting means and the gain setting means are constituted by digital circuits. Automatic gain control circuit.