JPH09293047A - Data transfer device of microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To specify a memory address fast by an external device when memory data of the microcomputer are transferred to the external device by an SPI communication. SOLUTION: The microcomputer 11 has a clock synchronous serial communication (SPI communication) with a tool 12 for adaptation through a serial interface 13. A high-order address specification register 24 of the microcomputer 11 specifies the high-order address of data which desires to be read out of a RAM 27. An address generation circuit 25 combines serial data (low-order address) sent from the tool 12 for adaptation with the high-order address specified by the high-order address specification register 24 to generate the address of RAM data to be sent next. Then a transmit data transfer circuit 26 reads the RAM address in the address by direct memory access, and transfers them to a transmit data buffer register 20, so that the data are transmitted to the tool 12 for adaptation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer data transfer device for transferring memory data of a microcomputer to an external device by clock synchronous serial communication.

[0002]

2. Description of the Related Art Conventionally, a microcomputer has been widely used as a computer for controlling various devices, and in the course of development, a microcomputer mounted on a controlled object in order to set a matching constant that matches the characteristics of the controlled object. BACKGROUND ART A matching tool is connected to a computer, and while the control target is controlled by a microcomputer, data that is temporarily stored in a memory (RAM) of the microcomputer is monitored by the matching tool.

Conventionally, a method of connecting a microcomputer and a matching tool to a matching tool by deriving a bus of the microcomputer to the outside has been adopted. However, in recent years, a high operating frequency of the microcomputer has been adopted. Along with this, the connection method in which the bus is led to the outside is susceptible to high-frequency noise, and the reliability of data transfer cannot be ensured.

Therefore, recently, in order to reduce the influence of high frequency noise, a system in which a serial interface is provided in a microcomputer and a communication cable is connected between the microcomputer and a matching tool is being adopted. In this method, in order to reduce the load on the CPU of the microcomputer and enable high-speed data transfer, the data transfer between the memory of the microcomputer and the serial interface is performed directly by hardware without software. A direct memory access (DMA) method of executing is adopted. Conventional DM
In the A method, an address of a memory to be monitored is set in a designated memory area in advance, and the data stored at the address is transferred to the serial interface.

[0005]

However, in the conventional DMA method, since the address of the memory to be monitored is set in a predetermined memory area, a part of the memory in the microcomputer must be used for DMA. As a result, the amount of memory that can be used by the CPU decreases accordingly. Moreover, as the serial communication method between the microcomputer and the adapting tool, the start-stop bit and the stop bit are added to the first and last bits of the serial data for synchronization, and the start-stop synchronization method serial communication (SCI communication) is used. Therefore, the communication baud rate can be secured only up to about 500 Kbps, and the transfer rate of memory data is slow.

In this case, if the communication system is changed to the serial communication (SPI communication) of the clock synchronous system, the communication baud rate can be increased to, for example, about 4 Mbps. Furthermore, by sending the address of the memory to be monitored from the matching tool to the microcomputer, it is not necessary to use part of the memory in the microcomputer for DMA, and the amount of memory available to the CPU is increased accordingly. it can.

However, since a large number of bits are required to specify an enormous memory address, the enormous memory address cannot be specified by the number of bits of serial data sent in one communication. . Therefore,
When the address is designated only by SPI communication, it is necessary to transmit the address data in two steps and combine the serial data twice in the receiving side to create one address data. Therefore, the adapting tool transmits the data of the address twice and receives one memory data for the first time, and the transfer speed of the memory data becomes slower accordingly, which is an advantage of the high speed communication which is the advantage of SPI communication. Not only can the functions be used effectively, but the matching tool requires special processing to synchronize the sent address with the received memory data, which is troublesome.

The present invention has been made in view of the above circumstances, and therefore an object thereof is to use a serial communication (SPI communication) of a clock synchronization system to transmit a serial data in one time. An object of the present invention is to provide a data transfer device for a microcomputer, which can specify an address, can increase the transfer speed of memory data, and can easily synchronize the address with the memory data received by the external device.

[0009]

In order to achieve the above object, a data transfer device for a microcomputer according to claim 1 of the present invention is a receiving part of a serial interface of a clock synchronization system for transmitting data transmitted from an external device. And the received data is used as the lower address of the data to be read from the memory of the microcomputer. The address generating means provided in the microcomputer combines the lower address with the upper address designated by the upper address designating means provided in the microcomputer to generate an address of memory data to be transmitted next. To do. Thereafter, the transmission data transfer means transfers the memory data stored in the address generated by the address generation means to the transmission unit of the serial interface by the direct memory access (DMA) method, and transmits this memory data to the external device. To do.

In this case, by providing the upper address designating means and the address generating means, the address can be designated by one transmission of serial data. Therefore, each time the microcomputer receives the serial data (lower address) transmitted from the external device once, the microcomputer immediately transfers the memory data to the transmission unit of the serial interface by the DMA method, and transfers the memory data to the external unit. It can be transferred to the device, and the transfer speed of the memory data can be increased. Moreover, the external device may process the data received immediately after the end of the data transmission as the memory data of the previously transmitted address, and does not need to perform a special process for synchronizing the address and the memory data.

Further, according to a second aspect, when the receiving unit of the serial interface receives data from the external device, the synchronous clock is not input before the number of input of the synchronous clock reaches the number of bits of the serial data. In this case, the reset means resets the received data. Therefore, even if the synchronous clock is disturbed due to noise or the like, it is possible to restore the subsequent communication to the normal state by stopping the communication for one data.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In the microcomputer 11,
A serial interface 13 for performing serial communication (SPI communication) of a clock synchronization method with the adaptation tool 12 (external device) is provided. The serial interface 13 has a clock terminal 14 to which the synchronization clock CLK is input from the matching tool 12, a reception terminal 15 to which the lower address data RX is input, and a memory data T.
A transmission terminal 16 for transmitting X to the matching tool 12 is provided. The serial interface 13 is provided with, for example, a 16-bit reception shift register 17 and a reception data buffer register 18 that form a reception unit, and a 16-bit transmission shift register 19 and a transmission data buffer register 20 that form a transmission unit. ing. Further, the serial interface 13 is provided with a transmission / reception shift register reset circuit 21 (reset means), and the synchronization clock CLK is generated due to noise or the like during communication.
When the input of is disturbed, the transmission / reception shift register reset circuit 21 outputs a reset signal to the reception shift register 17 and the transmission shift register 19 to reset them.

Further, in the microcomputer 11,
Although not shown, a CPU, ROM, RAM 27 (memory) and the like are provided, and these units are connected by an address bus 22 and a data bus 23. Further, in the microcomputer 11, the high-order address designation register 24
(Upper address designating means) is provided. The upper address designation register 24 is for designating an address (upper address) higher than 16 bits of the address of the data desired to be read from the RAM 27. For example, when the number of bits of the address of the RAM 27 is 24 bits, the upper address is 8-bit data, and the RAM
When the number of bits of the address is 32 bits, the upper address is 16-bit data.

Further, in the microcomputer 11,
An address generation circuit 25 (address generation means) and a transmission data transfer circuit 26 (transmission data transfer means) are provided. The address generation circuit 25 combines the 16-bit lower address data transferred from the reception data buffer register 18 with the 8-bit or 16-bit upper address data transferred from the upper address designating register 24 to obtain 24 bits. Generate a 32-bit or 32-bit address. This address becomes the address of the RAM data to be transmitted next.

On the other hand, the transmission data transfer circuit 26 is mainly composed of a direct memory access (DMA) control circuit. When the address generation circuit 25 finishes generating the address, the transmission data transfer circuit 26 reads the data in the RAM 27 stored at the address by the direct memory access method and transfers the data to the transmission data buffer register 20 of the serial interface 13. It is a thing.

As shown in FIG. 2, an SPI communication cable 31 and an SCI communication cable 32 are connected between the microcomputer 11 and the matching tool 12. SP
The I communication cable 31 uses the synchronous clock CLK,
The SCI communication cable 32 is a cable for transmitting the lower address data RX and the memory data TX, and the SCI communication cable 32 is a cable for transmitting commands and the like by the serial communication system (SCI communication) of the start / stop synchronization system. For example, when changing the upper address specified by the upper address specifying register 24, the SCI communication cable 32 is used to change the matching tool 12
Transmits the data of the higher address to the microcomputer 11. In the example of FIG. 2, the SCI communication cable 32 uses two signal lines of TX and RX, and is a full duplex capable of bidirectional communication at the same time, but the communication direction is one signal line. It is also possible to employ half-duplex, which performs bidirectional communication by alternately changing the two.

The microcomputer 11 communicates with the matching tool 12 via the SPI communication cable 31 to execute the SPI.
Communication is performed as follows. In conformity with the synchronization clock CLK input from the adaptation tool 12, the adaptation tool 1
16-bit lower address data transmitted from 2 is fetched into the reception shift register 17 bit by bit, 1
When the reception of the data of 6 bits is completed, the received data is transferred to the address generation circuit 25 via the reception data buffer register 18. This address generation circuit 2
5, the 16-bit lower address data transferred from the reception data buffer register 18 and the 8-bit or 1-bit transferred from the upper address specification register 24
The 6-bit upper address data is combined to generate the 24-bit or 32-bit address of the RAM data to be transmitted next. Thereafter, the transmission data transfer circuit 26 reads the 16-bit RAM data stored in the address generated by the address generation circuit 25 by the direct memory access method and transfers it to the transmission data buffer register 20 of the serial interface 13. To the transmission shift register 19. Then, the RAM data from the transmission shift register 19 is synchronized with the synchronous clock CLK and 16-bit serial data is used as the adaptation tool 1
2 is sent.

In this case, even if the number of bits of serial data sent in one communication is smaller than the number of bits of address data in the RAM 27, the upper address designation register 24 and the address generation circuit are provided in the microcomputer 11. Since 25 is provided, the address of the RAM 27 can be designated by one transmission of serial data (lower address). Therefore, the microcomputer 11
Every time the serial data (lower address) transmitted from the adapting tool 12 is received, the RAM data can be immediately transferred to the serial interface 13 by the DMA method each time the serial data is transferred. Can be fast Moreover, the adapting tool 12 only needs to process the RAM data received immediately after the data transmission as the RAM data of the address transmitted last time, and it is not necessary to perform special processing for synchronizing the address and the RAM data. It can also contribute to speeding up the processing of the received data of the tool 12 for use.

Further, since the microcomputer 11 can perform a series of processing from reception of serial data (lower address) to transfer of RAM data at high speed,
No data gap between communication data is required on the side of the microcomputer 11. Therefore, the processing speed of the reception data processing unit of the adapting tool 12 is determined by the microcomputer 11
The RAM data can be monitored by the matching tool 12 without a gap between data if the transfer rate of the RAM data from the device can be followed.

Generally, the communication baud rate of SPI communication is 4
It is possible up to about Mbps. In this embodiment, it is assumed that the communication baud rate is 2 Mbps, there is no data gap, and the monitored data is 10 words (1 word = 16).
Bit), the response per data is 10 ×
16/2 = 80 μs.

Further, in this embodiment, the serial interface 13 is provided with a transmission / reception shift register reset circuit 2
1 is provided. The transmission / reception shift register reset circuit 21 counts the number of times the synchronization clock CLK is input while the serial data is being transmitted from the adaptation tool 12, and before the number of inputs of the synchronization clock CLK reaches the number of bits of the serial data. When the synchronous clock CLK is no longer input, a reset signal is output to the reception shift register 17 and the transmission shift register 19 to reset both shift registers 17 and 19. Therefore, even if the synchronous clock CLK is disturbed by noise or the like, the communication can be restored to the normal state by stopping the communication for one data, and the reliability of the communication can be improved.

In this embodiment, the number of bits of serial data is 16 bits, but other numbers of bits such as 8 bits and 32 bits may be used.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a microcomputer according to an embodiment of the present invention.

FIG. 2 is a diagram showing a communication line between a microcomputer and a matching tool.

[Explanation of symbols]

11 ... Microcomputer, 12 ... Adaptation tool (external device), 13 ... Serial interface, 17 ... Reception shift register (reception unit), 18 ... Reception data buffer register (reception unit), 19 ... Transmission shift register (transmission unit) , 20 ... Transmission data buffer register (transmission unit), 21 ... Transmission / reception shift register reset circuit (reset means), 24 ... High-order address designation register (high-order address designation means), 25 ... Address generation circuit (address generation means), 26 ... Transmission data transfer circuit (transmission data transfer means), 27 ... RAM (memory), 31 ... SPI communication cable, 32 ... SCI communication cable.

Claims (2)

[Claims] 1. A data transfer device of a microcomputer for transferring data stored in a memory of a microcomputer to an external device via a serial interface of a clock synchronization system, wherein an upper address of data to be read from the memory is set. The upper address designating unit for designating and the data transmitted from the external device and received by the receiving unit of the serial interface are set as the lower address of the data to be read from the memory, and this is designated by the upper address designating unit. Address generating means for generating an address of memory data to be transmitted next by combining with the upper address, and memory data stored at the address generated by the address generating means are transmitted to the serial interface by the direct memory access method. Transfer to department A data transfer device for a microcomputer, comprising: transmission data transfer means for sending. 2. When receiving the data from the external device in the receiving unit of the serial interface, if the synchronous clock is not input before the number of input of the synchronous clock reaches the number of bits of the serial data, reception is performed. 2. The data transfer device for a microcomputer according to claim 1, further comprising reset means for resetting data.