JPH09289165A - Semiconductor thin film, manufacture thereof, semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor thin film which is equivalent in crystallinity to a single crystal, by a method wherein a semiconductor thin film possessed of a lateral growth region formed of aggregated columnar or needle crystals nearly parallel with a substrate is irradiated with a laser beam. SOLUTION: Nickel element is held coming into contact with a region 205 of a non-crystal silicon film 203 through the intermediary of an oxide film, hydrogen is expelled, and then a heat treatment is carried out to crystallize the non-crystal silicon film 203. At this point, columnar or needle crystals are grown nearly in parallel with a substrate. Then, a silicon oxide 204 which served as a mask when nickel was selectively introduced is removed, and an obtained crystalline silicon film 207 is irradiated with a laser beam or a light beam of high intensity equivalent in energy to a laser beam. By this setup, crystal grain boundaries are not substantially present, so that the lateral growth region itself can be made to serve as a mono-domain region. Furthermore, columnar or needle crystals are markedly improved in crystallinity.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a semiconductor thin film having a region (hereinafter referred to as a monodomain region) formed on a substrate having an insulating surface and which can be regarded as a substantially single crystal, and a semiconductor device having the semiconductor thin film as an active layer. In particular, the present invention relates to a thin film transistor having an active layer made of a crystalline silicon film.

[0002]

2. Description of the Related Art In recent years, a technique for forming a thin film transistor (TFT) by using a thin silicon semiconductor film (having a thickness of several hundreds to several thousands Å) formed on a substrate having an insulating surface has received attention. Thin film transistors have been widely applied to electronic devices such as ICs and liquid crystal display devices.

The important part which should be called the heart of the thin film transistor is a channel forming region and a junction part for joining the channel forming region and the source / drain regions. That is, it can be said that the active layer most affects the performance of the thin film transistor.

As a semiconductor thin film forming an active layer of a thin film transistor, an amorphous silicon film (amorphous silicon film) formed by a plasma CVD method or a low pressure thermal CVD method is generally used.

At present, a thin film transistor using an amorphous silicon film has been put into practical use, but a silicon thin film having crystallinity (referred to as a crystalline silicon film) is used when higher speed operation is required. A thin film transistor utilized is needed.

As a method for forming a crystalline silicon film on a substrate, the applicant of the present invention has disclosed Japanese Patent Laid-Open Nos. 6-232059 and 6-
The technique described in Japanese Patent No. 244103 is known. The technique described in this publication forms a crystalline silicon film having excellent crystallinity by heat treatment at 550 ° C. for about 4 hours by utilizing a metal element that promotes crystallization of silicon. .

Further, the technique described in Japanese Patent Application Laid-Open No. 7-321339 applies the above technique to perform crystal growth substantially parallel to the substrate, and the inventors of the present invention particularly laterally grow the formed crystallization region. It is called the area (or lateral growth area).

The lateral growth region formed by such a technique is
It is a region in which columnar or needle-shaped crystals are gathered in a state in which the traveling directions are aligned, and has a characteristic of excellent crystallinity. Therefore, it is known that a thin film transistor having an active layer formed by utilizing this region has high performance.

However, even with the above technique, there is a feeling that the thin film transistor for forming various arithmetic circuits, memory circuits, etc. is insufficient in its function. This is because the crystallinity is still insufficient and the required properties cannot be obtained.

For example, a peripheral circuit of an active matrix type liquid crystal display device or a passive type liquid crystal display device, a driving circuit for driving a pixel TFT arranged in a pixel region, a circuit for handling and controlling a video signal, A memory circuit or the like for storing various kinds of information is required.

Among these circuits, a circuit for handling and controlling a video signal and a memory circuit for storing various information are
It is required to have performance comparable to that of an integrated circuit using a known single crystal wafer. Therefore, in order to integrate these circuits using a thin film semiconductor formed on a substrate, it is necessary to form a crystalline silicon film having crystallinity comparable to a single crystal on the substrate.

[0012]

SUMMARY OF THE INVENTION An object of the invention disclosed in the present specification is to form a monodomain region having crystallinity comparable to a single crystal on a substrate having an insulating surface. Then, it is an object to obtain a semiconductor device in which an active layer is formed by the monodomain region.

[0013]

The structure of the invention disclosed in the present specification is a semiconductor thin film formed on a substrate having an insulating surface, wherein the semiconductor thin film is laser light or energy equivalent to the laser light. Having a monodomain region whose crystallinity is improved by irradiation with strong light, wherein the monodomain region is formed by assembling a plurality of columnar or acicular crystals substantially parallel to the substrate. .

A semiconductor device having a structure of another invention uses only the monodomain region as an active layer. The inside of this monodomain region is characterized in that there is substantially no grain boundary.

According to another aspect of the invention, there is provided a step of forming an amorphous silicon film on a substrate having an insulating surface by a low pressure thermal CVD method, and a silicon oxide film is selectively formed on the amorphous silicon film. A step of forming, a step of holding a metal element that promotes crystallization in the amorphous silicon film, and a step of transforming at least a part of the amorphous silicon film into a crystalline silicon film by heat treatment. At least, a step of removing the silicon oxide film, and a step of irradiating the amorphous silicon film and / or the crystalline silicon film with laser light or strong light having energy equivalent to the laser light. It is characterized in that the crystalline silicon film is transformed into a monodomain region by a step of irradiating with the laser beam or intense light having the same energy as the laser beam. Further, it is characterized in that the active layer is constituted by a mono domain region formed through these steps.

The present inventors defined the lateral growth region obtained by the present invention as a region which can be regarded as a substantially single crystal, and defined that region as a monodomain region. The feature of the monodomain region is that there is substantially no grain boundary in the region,
That is, there are almost no crystal defects caused by dislocations, stacking faults, and the like.

The phrase "substantially free of crystal grain boundaries" means that the crystal grain boundaries are electrically inactive even if they exist. Such electrically inactive grain boundaries include {111} twin grain boundaries, {111} stacking faults,
{221} twin grain boundaries and {221} Twist twin grain boundaries have been reported (R.Simokawa and Y.Hayashi: Jpn.J.App.
l.Phys. 27 (1987) pp.751 to 758).

The present inventors presume that the crystal grain boundaries included in the monodomain region are highly likely to be these electrically inactive crystal grain boundaries. That is, it is considered to be an inactive region that does not electrically hinder the movement of carriers even if it appears as grain boundaries.

The monodomain region, which is the most important concept in the present invention, is formed in the following process.

First, as shown in FIG. 1A, crystal growth proceeds around a region 101 into which a metal element is selectively introduced. At this time, the columnar or acicular crystals that grow crystals grow in a direction substantially parallel to the substrate.

The metal elements that promote crystallization are Fe, Co, Ni, Ru, Rh, Pd, Os, Ir and P.
One or a plurality of types selected from t, Cu, and Au are used, but here Ni (nickel) is taken as an example.

In this way, a lateral growth region 102 is formed. For example, when formed by heat treatment at 600 ° C. for about 6 hours, the lateral growth width (distance X in the figure) is 100.
It becomes about 200 μm.

The formed lateral growth region 102 is shown in FIG.
It is divided into eight parts A to H as shown in FIG. This time,
Each of A to H looks like one crystal grain. This is because a defect such as slip occurs in a region where A to H collide with each other and becomes a crystal grain boundary.

FIG. 1B shows a simplified diagram in which a part of the regions A to H is enlarged. As shown in FIG. 1 (B), when viewed microscopically, the lateral growth region is formed by a plurality of columnar or needle-like crystals aggregated, and because these are densely packed, macroscopically FIG. ), It looks like a single crystal grain.

Each of these columnar or needle-shaped crystals is a region which does not include a grain boundary and can be regarded as a substantially single crystal.
That is, it is a mono-domain area.

Further, since each crystal grows while excluding the impurity element such as nickel from the inside thereof, metal silicide is formed on the crystal surface, and 10 in FIG. 1 (B) is formed.
The metal element is segregated in the crystal grain boundaries as shown by 3.

Therefore, in the state shown in FIG. 1B, a plurality of monodomain regions are simply aggregated and the crystallinity is relatively good, but the lateral growth region itself is not a monodomain region.

To realize the present invention, this lateral growth region 10 is used.
The step of improving the crystallinity of No. 2 is required. In this specification, this step is particularly referred to as a single crystallization step.

The single crystallization step in the present invention is specifically irradiating the obtained crystalline silicon film with laser light or intense light having energy equivalent to that of laser light.

First, it is desirable to use an excimer laser in the ultraviolet region as the laser light used. Specifically, KrF excimer laser (wavelength 248 nm) and X
An eCl excimer laser (wavelength 308 nm) or the like can be used. Further, the same effect can be obtained by irradiating not the laser light but the strong light using the ultraviolet lamp.

The irradiated surface of the crystalline silicon film irradiated with the laser beam is locally heated to a high temperature, and the silicon film is in an instantaneous molten state. However, actually, the metal silicide segregated in the grain boundary portion 103 of the columnar or needle crystal as shown in FIG. 1B is preferentially melted, and the columnar or needle crystal is not easily melted.

That is, when laser light is irradiated to the lateral growth region having the structure shown in FIG.
Although it is instantaneous, it preferentially melts and recrystallizes. Note that the broken line denoted by 104 in FIG.
This is a bonding interface in which the crystal grain boundary 103 in (B) is temporarily dissociated and then recombined.

At that time, the silicon lattice in the vicinity of the crystal grain boundary 103 is rearranged and silicon is recombined with good matching.
Therefore, as shown in FIG. 1 (B), the individual regions shown by A to H, which were formed by assembling a plurality of columnar or acicular crystals, are substantially crystalline as shown in FIG. 1 (C). There are no grain boundaries.

Furthermore, since crystal defects such as dislocations and stacking faults that are internal to the needle-shaped or columnar crystal are almost eliminated, the crystallinity of the originally columnar or needle-shaped crystal is remarkably improved. Will be things.

At this time, volume expansion occurs in the individual regions A to H due to rearrangement of the silicon lattice. As a result, a ridge of the silicon film is observed at a crystal grain boundary (that is, an outer edge portion of the monodomain region) where the regions A to H collide with each other in FIG. This bulge of the silicon film is one of the features that can be seen when the above laser irradiation process is performed.

It has been empirically known that the crystallinity in the crystal grains is good when such a protrusion of the silicon film occurs at the crystal grain boundaries. The reason is as follows. Currently uncertain.

Further, it is known from SEM observation that the ridge of the silicon film has a height of about 500 Å when the film thickness of the amorphous silicon film is 500 Å, for example.

The crystalline silicon film formed through the above process has a remarkably improved crystallinity, and is a monodomain region having a crystallinity comparable to that of a single crystal.

One of the structures of the present invention is to form an active layer of a semiconductor device represented by a thin film transistor by utilizing only the above-mentioned monodomain region.

FIG. 4 shows active layers arranged in a matrix on a substrate 401 having an insulating surface for manufacturing an active matrix type liquid crystal display device.

The region indicated by the broken line 402 is the place where the region for selectively introducing nickel exists. Further, 403 is a place where a crystal grain boundary formed by the lateral growth regions hitting each other exists. Since it cannot be confirmed after forming the active layer, it is shown by a dotted line.

As shown in FIG. 4, the active layer 404 of the thin film transistor is formed in a matrix so as not to include a nickel introduction region and a crystal grain boundary.

FIG. 4 is a view seen locally, but the substrate 40
The same is true for all active layers formed on 1. That is, the active layers of millions of thin film transistors are formed by using only the monodomain regions that do not include grain boundaries.

The structure of the present invention as described above will be described in detail with reference to the following embodiments.

[0045]

【Example】

[Embodiment 1] In this embodiment, a crystalline silicon film is taken as an example of a semiconductor thin film formed on a substrate having an insulating surface, and a means for further enhancing the crystallinity of a lateral growth region composed of the crystalline silicon film is provided. The means for applying the mono domain region will be described. FIG. 2 is used to explain this process.

The crystallization means used in this embodiment selectively introduces nickel, which is a metal element that promotes crystallization, into the amorphous silicon film to grow crystals in a direction substantially parallel to the substrate. To obtain a crystalline silicon film. This technique is described in JP-A-7-321339, as mentioned above.

First, a substrate 201 having an insulating surface is prepared. In this embodiment, a silicon oxide film 202 is formed as a base film on a glass substrate (which may be a quartz substrate or a silicon substrate) to a thickness of 3000 Å. This silicon oxide film 202 is formed by a sputtering method using an artificial quartz target (for reference, the composition table of the artificial quartz target is shown in FIG. 12).
Shown).

When the amorphous silicon film is crystallized later,
The present inventors have found that the denser the base film, the better the crystallinity of the obtained crystalline silicon film. Therefore, in this embodiment, the silicon oxide film 202 is formed by the sputtering method using the artificial quartz target.

The surface of the silicon oxide film 202 is extremely flat and smooth. For example, the height of the unevenness is 30 Å or less, the width of the unevenness is 100 Å or more, and the AF
Even when observed with M (Atomic Force Microscopy), the level is difficult to recognize as unevenness.

Next, the amorphous silicon film 203 is coated with 100 to 750 Å.
Plasma CVD to a thickness (preferably 150 to 450 Å)
Method, sputtering method or low pressure thermal CVD method. When the low pressure thermal CVD method is used, disilane (Si ₂ H ₆ ), trisilane (Si ₃ H ₈ ) or the like may be used as the film forming gas.

By setting the film thickness of the amorphous silicon film 203 to the above-mentioned film thickness, not only the subsequent single crystallization step by laser light irradiation is effectively performed, but also the crystalline silicon film obtained by crystallization is formed. When it is used as an active layer of a semiconductor device, a semiconductor device with low off current can be manufactured.

The amorphous silicon film formed by the low pressure thermal CVD method has a small natural nucleus generation rate during the subsequent crystallization. This is desirable in order to increase the lateral growth width, since the rate at which individual crystals interfere with each other (collision stops growth) is reduced.

After forming the amorphous silicon film 203, UV light is irradiated in an oxygen atmosphere to form an extremely thin oxide film (not shown) on the surface of the amorphous silicon film 203. This oxide film is for improving the wettability of the solution in the solution applying step when nickel is introduced later. (Fig. 2 (A))

Then, a silicon oxide film 204 having a thickness of 500 to 1200 Å is formed by a sputtering method using a quartz target, and only the region into which nickel is introduced is selectively removed by etching. That is, the silicon oxide film 204 functions as a mask for selectively introducing nickel into the amorphous silicon film 203.

The region 205 exposed by the silicon oxide film 204 is formed in a slit shape having a longitudinal direction perpendicular to the paper surface. (FIG. 2 (B))

Next, a nickel acetate solution containing nickel at a predetermined concentration is dropped to form a water film 206.
(Fig. 2 (C))

Considering residual impurities in the subsequent heating step, it is preferable to use a nickel nitrate salt solution as the nickel salt solution. This is because the nickel acetate salt solution can be used, but the nickel acetate salt solution contains carbon, which may cause carbonization in the subsequent heating step and remain in the film.

In the state shown in FIG. 2C, spin coating is performed using a spinner, and a nickel element is held in contact with the region 205 on the amorphous silicon film 203 via an oxide film (not shown). To do.

Then, at 450 ° C. in an inert atmosphere,
After dehydrogenating for about 1 hour, 500 ~ 700 ℃,
Typically, heat treatment is performed at a temperature of 550 to 600 ° C. for 4 to 8 hours to crystallize the amorphous silicon film 203. However, when it is formed on a glass substrate, it is desirable to set the temperature to 650 ° C. or lower in consideration of the heat resistance of the glass. Thus, the crystalline silicon film 207 is obtained. (Fig. 2 (D))

In a region indicated by 205, nickel diffuses into the amorphous silicon film 203 from a state in which it is held in contact with the amorphous silicon film 203 via an oxide film not shown, through an oxide film not shown, It functions as a catalyst for promoting crystallization. Specifically, nickel and silicon react with each other to form a silicide, which serves as a nucleus to promote crystallization.

At this time, in the crystal growth, columnar or acicular crystals proceed in a direction substantially parallel to the substrate. In the case of the present embodiment, the region indicated by 205 has a slit shape having a longitudinal direction from the front direction to the back direction in the drawing, so that the crystal growth proceeds substantially along one direction as indicated by an arrow 208. To do. At this time, the crystal growth can be performed over several hundred μm.

At this time, if natural nucleation occurs due to the heat treatment, the columnar or needle-shaped crystals that have grown crystals interfere with each other and interfere with each other's growth. That is, the growth width of the lateral growth region becomes short, which is not preferable. Therefore,
It is desirable to set the conditions such that the spontaneous nucleation is small and only the introduced nickel becomes the nuclei.

The concentration of nickel introduced at this time can be easily controlled by adjusting the concentration of the nickel salt solution in the solution coating step.

The lateral growth region as described above is not affected by other crystals so much because the crystal growth directions are aligned.
Therefore, this lateral growth region appears macroscopically as large crystal grains (grains) of several hundred μm or more.

However, microscopically, the columnar or needle-like crystals are only densely packed, and although the individual crystals are monodomains, the regions having relatively excellent crystallinity are generally present. It's just forming. That is, it cannot be regarded as a monodomain region.

Next, after the heat treatment for crystallization is completed, the silicon oxide film 204 which serves as a mask for selectively introducing nickel is removed. This step is easily performed with buffered hydrofluoric acid or the like.

In this state, the crystalline silicon film 20
Surface irregularity of 7 is less than ± 30Å (preferably less than ± 20Å)
It has become. It is considered that this is because the surface of the silicon film is suppressed by the silicon oxide film 204 during crystal growth.

Next, the crystalline silicon film 207 obtained in the above step is irradiated with laser light or intense light having energy equivalent to that. In this embodiment, a KrF excimer laser (wavelength 248 nm) is used as the laser light, but a XeCl excimer laser (wavelength 308n) is used.
m) may be used.

In this step, the columnar or needle-shaped crystals forming the lateral growth region are locally heated to a high temperature by the irradiation of laser light. At this time, a metal silicide (nickel silicide in this embodiment) segregated at the crystal grain boundaries (shown by 103 in FIG. 1B) of columnar or needle crystals.
Melts preferentially.

Then, the silicon lattice is rearranged at the crystal grain boundaries which are instantaneously melted, and the silicon atoms are recombined with good matching. Therefore, the crystal grain boundaries do not substantially exist, and the lateral growth region itself can be used as the monodomain region.

Furthermore, since crystal defects such as dislocations and stacking faults that are internal to the needle-shaped or columnar crystal are almost eliminated, the crystallinity of the originally columnar or needle-shaped crystal is remarkably improved. Becomes

The crystalline silicon film 208 thus obtained is composed of a monodomain region in which crystal grain boundaries do not substantially exist, and has crystallinity comparable to that of a single crystal in the monodomain region.

[Embodiment 2] This embodiment is an example in which the irradiation of the laser light of Embodiment 1 is performed with strong light having the same energy. RTA (Rapid Thermal Annealing) is known as this technique.

RTA is a method of irradiating an object to be processed with intense light such as infrared light and ultraviolet light by a lamp or the like. This feature is that the heating rate and the cooling rate are fast, and the processing time is short at several seconds to several tens of seconds, so that only the thin film on the outermost surface can be heated substantially. That is, for example, only a thin film on a glass substrate can be annealed at an extremely high temperature of about 1000 ° C.

Further, the fact that the processing time is short means that the throughput is greatly improved in the manufacturing process, and it can be said that this is a very effective means from the viewpoint of productivity.

[Embodiment 3] This embodiment shows an example in which an active layer of a thin film transistor is formed by using the monodomain region obtained in the step shown in Embodiment 1. In this embodiment, the top gate type is taken as an example, but it can be easily applied to the bottom gate type.

First, as shown in FIG. 3A, a semiconductor thin film including a monodomain region is formed according to the process shown in the first embodiment, and an active layer 303 including only the monodomain region is formed by patterning. . Incidentally, 301 is a quartz substrate as described in the first embodiment, and 302 is a silicon oxide film.

Next, a silicon oxide film 304 functioning as a gate insulating film is formed to a thickness of 1500Å by the plasma CVD method. It may be a silicon oxynitride film or a silicon nitride film.

Next, an aluminum film 305 for forming a gate electrode is formed to a thickness of 5000Å by a sputtering method. 0.2% scandium is contained in this aluminum film.
% By weight. In addition to aluminum, other metals such as tantalum and molybdenum may be used. Thus, the state shown in FIG. 3A is obtained.

After forming the aluminum film 305, an extremely thin anodic oxide film (not shown) is formed on the surface thereof. For this anodic oxide film, an ethylene glycol solution containing 3% tartaric acid neutralized with aqueous ammonia is used as an electrolytic solution. That is, in this electrolytic solution, the aluminum film 3
Anodization is performed using 05 as an anode and platinum as a cathode.

The anodic oxide film formed in this step has a dense film quality and functions to improve the adhesion to the resist mask formed later. The thickness of the anodic oxide film (not shown) is about 100Å. The film thickness can be controlled by the applied voltage.

Next, the aluminum film 305 is patterned to form an island-shaped aluminum film pattern 306 which will be the base of the gate electrode. The resist mask (not shown) used at this time is left as it is. (Fig. 3
(B))

After obtaining the state shown in FIG. 3B, anodic oxidation is performed again using the aluminum film pattern 306 as an anode. Here, a 3% oxalic acid aqueous solution is used as the electrolytic solution. In this anodizing step, anodization proceeds only on the side surface of the aluminum pattern 306 due to the presence of a resist mask (not shown). Therefore,
An anodic oxide film is formed as indicated by 307 in FIG.

Further, the anodic oxide film 30 formed in this step
No. 7 has a porous shape, and its growth distance can be increased up to several μm.

The thickness of the porous anodic oxide film 307 is set to 7,000 Å. The film thickness of the anodic oxide film 307 can be controlled by the anodic oxidation time.

Porous anodic oxide film 3 shown in FIG. 3 (C)
After forming 07, the resist mask not shown is removed. Then, by performing anodic oxidation again, a dense anodic oxide film 308 is formed. This anodic oxidation process is performed under the same conditions as those for forming the dense anodic oxide film described above.

However, the film thickness to be formed is 800 Å.
In this step, since the electrolytic solution enters the inside of the porous anodic oxide film 307, the anodic oxide film 308 is formed as shown in FIG.

When the thickness of this anodic oxide film is increased to 1500 Å or more, the offset gate region can be formed in the subsequent impurity ion implantation step.

The dense anodic oxide film 308 functions to suppress the generation of hillocks on the surface of the gate electrode 309 in a later step.

After forming the dense anodic oxide film 308,
In this state, impurity ions are implanted to form the source / drain regions. Here, P ions are implanted in order to manufacture an N-channel thin film transistor.

In this step, the source region 310 and the drain region 311 to which impurities are added at a high concentration are formed. (FIG. 3 (C))

Next, using a mixed acid obtained by mixing acetic acid, phosphoric acid, and nitric acid, the porous anodic oxide film 307 is selectively removed, and then P ions are implanted again. This ion implantation is performed with a lower dose amount than when forming the source / drain regions.

As a result, low-concentration impurity regions 312 and 313 having a lower impurity concentration than the source region 310 and the drain region 311 are formed. Then, the region 314 is formed as a channel forming region in a self-aligning manner. (Fig. 3
(D))

After the step of implanting the impurity ions, laser light, infrared light, or ultraviolet light is irradiated to anneal the region where the ions are implanted.

Thus, the source region 310, the low concentration impurity region 312, the channel forming region 314, the low concentration impurity region 313, and the drain region 311 are formed. Here, the low-concentration impurity region 313 is a region usually called LDD (lightly doped drain region).

Here, the plasma hydrogenation treatment is performed in the range of 300 to 35.
It is effective to perform the treatment in the temperature range of 0 ° C. for 0.5 to 1 hour.
By this step, 5 atomic% or less (1 ×
10 ²¹ atoms / cm ³ or less), preferably 1 × 10 ¹⁵ to 1 ×
Hydrogen of 10 ²¹ atoms / cm ³ or less is added.

Since this hydrogen is active, it can be removed by neutralizing the dangling bonds of silicon in the active layer 303 or the level at the interface of the active layer / gate insulating film.

When the state shown in FIG. 3D is obtained in this way, an interlayer insulating film 315 is next formed. Interlayer insulating film 315
Is formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a resin film, or a stacked film of these films. It is preferable to use a silicon nitride film because hydrogen added in the previous step can be prevented from being released again to the outside of the device.

Then, contact holes are formed to form a source electrode 316 and a drain electrode 317. Pixel TFT in active matrix type liquid crystal display device
However, in the case of the circuit TFT used in the peripheral drive circuit, the extraction electrode from the gate electrode 309 also needs to be formed at the same time.

Further, heat treatment is performed in a hydrogen atmosphere at 350 ° C. to hydrogenate the entire element, thereby completing the thin film transistor shown in FIG.

Since the thin film transistor formed in this manner has an active layer composed of a monodomain region, it exhibits a good field-effect mobility that is compatible with high-speed operation. In addition, since there is no segregation of crystal grain boundaries and nickel compounds in the channel region and the drain junction, a thin film transistor with excellent reliability can be manufactured.

[Embodiment 4] This embodiment is an example of forming a CMOS structure with the TFT shown in the third embodiment. FIG.
~ Fig. 7 shows a manufacturing process of this embodiment. Note that the crystalline silicon film formed according to the present invention has a wide range of applications, and the CMOS
The method of forming the structure is not limited to this embodiment.

First, according to the structure shown in Example 1, a silicon oxide film 502 is formed on a glass substrate 501, and a crystalline silicon film having a monodomain region is obtained thereon. Then, by patterning it, an active layer 503 of the N-channel type TFT and an active layer 504 of the P-channel type TFT which are composed of only the mono domain region are obtained.

After forming the active layers 503 and 504, the silicon oxide film 505 functioning as a gate insulating film is plasma C
The film is formed by the VD method. The thickness is 500 to 2000Å, typically 1000 to 1500Å. Further, as the gate insulating film, another insulating film such as a silicon oxynitride film or a silicon nitride film may be used.

Thus, the state shown in FIG. 5A is obtained. Here, an example in which a pair of N-channel thin film transistors and P-channel thin film transistors is formed is shown for simplicity of description. Generally, an N-channel type thin film transistor and a P-channel type thin film transistor are formed in units of several hundreds or more on the same glass substrate.

After obtaining the state shown in FIG.
As shown in (B), an aluminum film 506 which will later form a gate electrode is formed.

This aluminum film contains scandium in an amount of 0.2 wt% in order to suppress the generation of hillocks and whiskers. The aluminum film is formed by a sputtering method or an electron beam evaporation method.

Hillocks and whiskers are spine-like or needle-like protrusions caused by abnormal growth of aluminum. The presence of hillocks or whiskers causes short circuits or crosstalk between adjacent wirings or between wirings separated by an upper limit.

As a material other than the aluminum film, anodizable metal such as tantalum can be used.

After forming the aluminum film 506, anodization is performed in the electrolytic solution using the aluminum film 506 as an anode to form a thin and dense anodic oxide film 507.

Here, an ethylene glycol solution containing 3% tartaric acid neutralized with ammonia is used as an electrolytic solution. By using this anodizing method, an anodized film having a dense film quality can be obtained. The film thickness can be controlled by the applied voltage.

Here, the thickness of the anodic oxide film 507 is set to 100.
Å The anodic oxide film 507 has a role of improving the adhesion with a resist mask formed later. Thus, the state shown in FIG. 5B is obtained.

Next, resist masks 508 and 509 are formed. Then, using the resist masks 508 and 509, the aluminum film 506 and the anodic oxide film 50 on its surface are formed.
7 is patterned. Thus, the state shown in FIG. 5C is obtained.

Next, using 3% oxalic acid aqueous solution as an electrolytic solution, anodic oxidation is performed with the patterns 510 and 511 made of the aluminum film remaining in this solution as anodes.

In this anodizing step, the anodizing selectively proceeds on the side surfaces of the aluminum films 510 and 511 where the anodization remains. This is the aluminum film 510 and 5
11, a dense anodic oxide film and a resist mask 508
And 509 remain.

In this anodic oxidation, the anodic oxide films 512 and 51 having a porous (porous) film quality.
3 is formed. Also, this porous anodic oxide film 51
2, 513 can be grown to about several μm.

In the present embodiment, this anodic oxidation progress distance,
That is, the film thickness is 7,000 Å. The length of the low-concentration impurity region will be determined later by the progress distance of this anodic oxidation. Empirically, the growth distance of this porous anodic oxide film is 6000Å
It is desirable to set it to ~ 8000Å. FIG.
The state shown in (D) is obtained.

In this state, the gate electrodes 51 and 52 are defined. After obtaining the state shown in FIG. 5D, the resist masks 508 and 509 are removed.

Next, anodic oxidation is performed again using an ethylene glycol solution containing 3% tartaric acid neutralized with ammonia as an electrolytic solution. In this step, the electrolytic solution penetrates into the porous anodic oxide films 512 and 513. As a result, dense anodic oxide films 514 and 515 in FIG. 5E are formed.

The thickness of the dense anodic oxide films 514 and 515 is set to 500 to 4000 Å. The film thickness is controlled by the voltage application time. The remaining portion of the dense anodic oxide film 507 formed previously is integrated with the anodic oxide films 514 and 515.

Next, in the state shown in FIG. 5E, the entire surface is doped with P (phosphorus) ions as an impurity imparting N-type conductivity.

This doping is 0.2-5 × 10 ¹⁵ / c
The dose is as high as m ² , preferably 1 to 2 × 10 ¹⁵ / cm ² . A plasma doping method or an ion doping method is used as the doping method.

As a result of the step shown in FIG. 5 (E), regions 516, 517, 518 where P ions are implanted at a high concentration,
519 is formed.

Next, the porous anodic oxide films 512 and 513 are removed using aluminum mixed acid. At this time, the anodic oxide film 5
The active layer regions located directly under 12, 513 are substantially intrinsic because they are not ion-implanted.

Next, the resist mask 5 is formed so as to cover the element forming the right P-channel type thin film transistor.
Form 20. Thus, the state shown in FIG. 6A is obtained.

After obtaining the state shown in FIG.
As shown in (B), P ions are implanted again. This P
The dose of ion implantation is 0.1 to 5 × 10 ¹⁴ / cm 3.
² , preferably a low value of 0.3 to 1 × 10 ¹⁴ / cm ² .

That is, P performed in the step shown in FIG.
The dose of the ion implantation is lower than the dose performed in the step shown in FIG.

As a result of this step, the regions 522 and 524 become lightly doped low concentration impurity regions. Also, 5
The regions 21 and 525 are high-concentration impurity regions in which P ions are implanted at a higher concentration.

In this step, the region 521 becomes the source region of the N-channel type thin film transistor. And 522 and 524 become a low concentration impurity region, and 525 becomes a drain region. Further, the region indicated by 523 becomes a substantially intrinsic channel forming region. The region indicated by 524 is a region generally called an LDD (lightly doped drain) region.

Although not shown in particular, the anodic oxide film 514 is not shown.
The region blocked by the ion implantation is the channel forming region 523.
And the low-concentration impurity regions 522 and 524.
This region is called an offset gate region and has a distance corresponding to the film thickness of the anodic oxide film 514.

Although the offset gate region is substantially intrinsic without being ion-implanted, it does not form a channel because a gate voltage is not applied, functions as a resistance component that relaxes the electric field strength and suppresses deterioration.

However, the distance (offset gate width)
Is short, it does not function as an effective offset gate region. Also, there is no clear boundary as to how far away it will work effectively.

Next, the resist mask 820 is removed,
As shown in FIG. 6C, a resist mask 526 which covers the left N-channel thin film transistor is formed.

Next, in the state shown in FIG. 6C, B (boron) ions are implanted as impurities imparting P-type. Here, the dose amount of B ions is 0.2 to 10 × 10.
¹⁵ / cm ² , preferably about 1 to 2 × 10 ¹⁵ / cm ² . This dose amount can be approximately the same as the dose amount in the step shown in FIG.

527 and 531 formed by this process
The region indicated by contains an impurity imparting N-type and P-type, but substantially has only a function as a pad (hereinafter, referred to as a contact pad) for making contact with the extraction electrode. That is, unlike the N-channel thin film transistor on the left side, the regions 527 and 531 are clearly distinguished from the source / drain regions.

The present inventors defined the source region as a region indicated by 528 and the drain region as a region indicated by 530 in the P-channel type thin film transistor.

These regions 528 and 530 are formed by implanting only B ions into the substantially intrinsic region. Therefore, since other ions do not coexist, the impurity concentration can be easily controlled, and a PI junction with good compatibility can be realized. Further, the disorder of crystallinity due to ion implantation can be relatively small.

Although the offset gate region can be formed using the anodic oxide film 515, empirically, the P-channel type thin film transistor hardly deteriorates. Therefore, it is not necessary to particularly provide the offset gate region.

Thus, the source region 528 and the drain region 530 of the P-channel type thin film transistor are formed. Further, the region 529 is a channel forming region without any particular impurity implantation. And, as mentioned above, 527, 5
31 is a source region 528 and a drain region 530, respectively.
It becomes a contact pad for taking out a current from.

After the step shown in FIG. 6C is completed, the resist mask 526 is removed to obtain the state shown in FIG. 6D. In this state, laser light irradiation is performed to activate the implanted impurities and anneal the regions where the impurity ions are implanted.

At this time, a region shown by a pair of source / drain regions 521 and 525 of the N-channel type thin film transistor and a region shown by a set of source / drain regions 528 and 530 of the P-channel type thin film transistor. Irradiation with laser light can be performed in a state in which the difference in crystallinity between and is not so large.

The difference in crystallinity is not so large because the source / drain regions 528 and 530 of the P-channel type thin film transistor are not significantly damaged during ion implantation in the step shown in FIG. 6C. Is.

Therefore, when laser light irradiation is performed in the state shown in FIG. 6D to anneal the source / drain regions of the two thin film transistors, the difference in annealing effect can be corrected. That is, it is possible to correct the difference in the characteristics of the obtained N-type and P-channel type thin film transistors.

After obtaining the state shown in FIG.
As shown in (A), an interlayer insulating film 532 is formed to a thickness of 4000Å. The interlayer insulating film 532 may be any of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film, and may have a multi-layer structure. These silicide films are formed by plasma CVD.
Method or thermal CVD method may be used.

Next, contact holes are formed to form a source electrode 533 and a drain electrode 534 of an N-channel type thin film transistor (NTFT). At the same time, the source electrode 5 of the P-channel type thin film transistor (PTFT)
35 and the drain electrode 536 are formed. (Fig. 7 (B))

Here, patterning is performed so as to connect the drain electrode 534 of the N-channel type thin film transistor and the drain electrode 536 of the P-channel type thin film transistor, and the gate electrodes of the two TFTs are connected to each other to realize a CMOS structure. To be done.

For example, the CMOS type thin film circuit as shown in this embodiment can be used for an active matrix type liquid crystal display device or an active matrix type EL display device.

Note that FIG. 5 (E), FIG. 6 (B), and FIG.
In the step of implanting impurity ions shown in (C), it is important that the active layer is covered with the silicon oxide film 505 forming the gate insulating film.

By implanting impurity ions in such a state, it is possible to suppress the surface of the active layer from being roughened or contaminated. This greatly contributes to improving the yield and the reliability of the obtained device.

[Embodiment 5] This embodiment shows an example in which the crystalline silicon film shown in Embodiment 1 is formed on a silicon wafer. In this case, it is necessary to provide an insulating layer on the surface of the silicon wafer, but usually a thermal oxide film is often used.

The temperature range of the heat treatment is generally 700 to 1300 ° C., and the treatment time varies depending on the desired oxide film thickness.

Further, thermal oxidation of a silicon wafer is usually O
₂ , O ₂ -H ₂ O, H ₂ O, O ₂ -H ₂ combustion or the like. Further, oxidation in an atmosphere to which a halogen element such as HCl or Cl ₂ is added is also widely used.

A silicon wafer is one of the essential substrates for semiconductor devices such as ICs, and techniques for forming various semiconductor elements on the wafer have been created.

According to this embodiment, a crystalline silicon film having crystallinity comparable to that of a single crystal can be combined with a conventional technique using a silicon wafer to further expand the range of application of the crystalline silicon film. .

[Embodiment 6] This embodiment shows an example of Embodiment 5 in which a TFT using a crystalline silicon film according to the present invention is formed on an IC formed on a silicon wafer. The outline of the manufacturing process will be described with reference to FIG.

FIG. 8A shows a MOS-FET formed on a silicon wafer by a normal process. Reference numeral 801 denotes a silicon substrate, 802, 80
Reference numeral 3 is an insulating film for separating the elements from each other, and a thermal oxide film is generally used.

Reference numeral 804 denotes a source region and 805 denotes a drain region, which are formed through a diffusion process after implanting impurity ions imparting one conductivity type into the silicon substrate 801. If the silicon substrate 801 is P-type, an impurity (phosphorus) that imparts N-type is implanted, and if the silicon substrate 801 is N-type, an impurity (boron) that imparts P-type is implanted.

The region indicated by 806 is a channel forming region. A part of the thermal oxide film formed in the diffusion process after ion implantation is left on the silicon surface in this region by controlling the film thickness, and functions as a gate insulating film. 807
Is a gate electrode made of a polycrystalline silicon film having one conductivity type.

The gate electrode 807 is covered with an insulating film 808 such as a silicon oxide film, and the source electrode 809 and the drain electrode 81 are formed.
It is configured so as not to be electrically short-circuited with 0. (FIG. 8
(A))

After the state of FIG. 8A is obtained, an interlayer insulating film 811 is formed. A silicon oxide film, a silicon nitride film, or the like is used as this interlayer insulating film. After forming the interlayer insulating film 811, a contact hole is formed and a lead wire 812 from the drain electrode is formed. (Fig. 8 (B))

After obtaining the state of FIG. 8B, the exposed surface is flattened by polishing by CMP (chemical mechanical polishing) technique or the like. By this process,
The interlayer insulating film 811 is flattened, and the protruding portion of the extraction wiring 812 disappears.

In FIG. 8C, 813 is a flattened interlayer insulating film, and 814 is its flat surface. Also, 815
Is a lead-out wiring without a convex portion, and a lead-out wiring 816 is formed in connection with it.

Next, an interlayer insulating film 817 is formed. The present invention can be applied to this interlayer insulating film 817. That is, a thin film transistor having an active layer formed using a monodomain region is formed over the interlayer insulating film 817.

First, according to the first embodiment, the active layer 818 composed of the mono domain region is formed. Then, a gate insulating film 819 is formed, and then a gate electrode 820 is formed. Then, an impurity imparting one conductivity type is injected into the active layer.

After the impurity implantation is completed, a sidewall 31 for forming a low concentration impurity region is formed later.
The sidewall 821 is formed by the following steps.

First, an insulating film (not shown) made of a silicon oxide film or the like is formed so as to cover the gate electrode 820 and have a thickness equal to or larger than that of the gate electrode 820. Next, anisotropic etching by dry etching is performed to remove the formed insulating film,
The insulating film remains only on the side surface of the gate electrode 82.

Impurity implantation is performed again in this state. Then, the region into which the impurities are implanted for the second time becomes a source region and a drain region, and the region shielded by the sidewall 821 becomes an impurity region having a lower concentration than the source region and the drain region. After implanting the impurities, the impurities are activated by heat treatment, laser light irradiation, or the like.

After the active layer is formed as described above, a silicon oxide film or a silicon nitride film is formed as an interlayer insulating film 822, contact holes are formed, and a source electrode 823 and a drain electrode 824 are formed.

As described above, by applying the present invention on an IC as shown in this embodiment, an integrated circuit having a three-dimensional structure as shown in FIG. 8D can be formed. According to the present invention, since the TFT formed above the IC has a performance comparable to that of the TFT formed on the single crystal, it is possible to realize a higher density integrated circuit than before without impairing the original performance of the IC. You can [Embodiment 7] In this embodiment, an example in which a TFT manufactured by applying the present invention is applied to a DRAM (Dynamic Rondom Access Memory) will be described. FIG. 9 will be used for the description.

The DRAM is a type of memory in which information to be stored is stored in a capacitor as an electric charge. The transfer of charge as information to and from the capacitor is controlled by a TFT connected in series to the capacitor. FIG. 9 shows a circuit of a TFT and a capacitor which constitutes one memory cell of DRAM.
It shows in (A).

When a gate signal is applied by the word line 901, the TFT indicated by 903 becomes conductive.
In this state, the capacitor 904 is charged with electric charges from the bit line 902 side to read information, or the electric charges are taken out from the charged capacitor to read information.

A sectional structure of the DRAM is shown in FIG.
Reference numeral 905 denotes a substrate made of a quartz substrate or a silicon substrate. If it is a silicon substrate, so-called SOI
The structure can be configured.

A silicon oxide film 906 is formed as a base film on the substrate 905, and a T film to which the present invention is applied is formed on the silicon oxide film 906.
An FT is created. If the base 905 is a silicon substrate, a thermal oxide film can be used as the base film 906. Reference numeral 907 denotes an active layer formed of the mono domain region formed according to the first embodiment.

The active layer 907 is covered with the gate insulating film 908, and the gate electrode 909 is formed thereon. Then, after the interlayer insulating film 910 is laminated thereon, the source electrode 911 is formed. Simultaneously with the formation of the source electrode 911, the electrodes indicated by the bit lines 902 and 912 are formed. Reference numeral 913 is a protective film made of an insulating film.

This electrode 912 keeps a fixed potential, and a capacitor 904 is formed between the electrode 912 and the drain region of the active layer located therebelow. That is, the electric charge accumulated in this capacitor is written into or read from the TFT to have a function as a memory element.

The feature of the DRAM is that the number of elements constituting one memory is very small with only the TFT and the capacitor.
It is suitable for constructing large-scale memory with high integration density.
In addition, the price is kept low, so it is currently used in the largest amount.

For example, when an SOI structure to which the present invention is applied is formed on a silicon substrate, the junction area is small, so T
The leak current of the FT can be suppressed to a small value. This greatly contributes to the data retention time.

Further, as a feature of the DRAM cell formed on the SOI substrate, since the storage capacitance can be set small, it is possible to operate at a low voltage.

[Embodiment 8] In this embodiment, a TFT manufactured by applying the present invention is used as an SRAM (Static Rondom Access).
Memory) will be described. FIG. 10 will be used for the description.

The SRAM is a memory that uses a bistable circuit such as a flip-flop as a storage element, and is an O of the bistable circuit.
The binary information value (0 or 1) is stored corresponding to the two stable states of N-OFF or OFF-ON. This is advantageous in that memory is retained as long as power is supplied.

The memory circuit is composed of N-MOS and C-MOS. The SRAM circuit shown in FIG. 10A is a circuit using a high resistance as a passive load element.

Reference numeral 11 is a word line, and 12
Is a bit line. Reference numeral 13 is a load element composed of a high resistance, and an SRAM is composed of two sets of driver transistors as shown by 14 and two sets of access transistors as shown by 15.

A sectional structure of the TFT is shown in FIG.
A silicon oxide film 17 is formed as a base film on a substrate 16 made of a quartz substrate or a silicon substrate, and a TFT to which the present invention is applied can be manufactured on the silicon oxide film 17. 18 is Example 1
Is an active layer composed of a monodomain region formed according to the above.

The active layer 228 is covered with the gate insulating film 19, and the gate electrode 20 is formed thereon. And
After the interlayer insulating film 21 is laminated thereon, the source electrode 2
2 is formed. At the same time when the source electrode 22 is formed, the bit line 12 and the drain electrode 23 are formed.

An interlayer insulating film 24 is laminated again thereon, and then a polysilicon film 25 is formed as a high resistance load. Reference numeral 26 is a protective film made of an insulating film.

The characteristics of the SRAM having the above-mentioned structure are that it can operate at high speed, has high reliability, and can be easily incorporated into a system.

[Ninth Embodiment] The research on the SOI structure as mentioned in the seventh and eighth embodiments has been remarkable in recent years as a breakthrough of low power consumption. In this embodiment, the problem left on the SOI substrate is compared with the present invention.

The above problems are summarized in FIG. As shown in FIG. 11, there are things related to crystallinity such as interface states and fixed charges in the silicon film, and external things such as metal contamination and boron concentration.

In the present invention, the crystalline silicon film is irradiated with laser light or intense light having an energy equivalent to that of laser light to improve the crystallinity and recombine crystals (single crystallization).

As the effect of this laser annealing, factors that adversely affect the crystallinity such as pipe density, interface state, fixed charge, and threading transition can be removed or sufficiently reduced.

Furthermore, if the precipitate in FIG. 11 is a silicide-based substance, it is easily melted and disappears when irradiated with laser light. Further, in the case of an oxide-based substance, it can be expected that oxygen will be desorbed and diffused again due to a local temperature increase due to laser irradiation, and the oxide will disappear.

[Embodiment 10] In this embodiment, the semiconductor device of Embodiment 3 and the CMOS structure of Embodiment 4 are used to integrate an active matrix region and a peripheral drive circuit for driving this active matrix region on the same substrate. An example is shown below.

One of the bases constituting the integrated active matrix type liquid crystal display device has the following constitution. That is, in the active matrix area, at least one thin film transistor for switching is arranged in each of the pixels arranged in a matrix, and peripheral circuits for driving the active matrix area are arranged around the active matrix area. There is. All these circuits are integrated on one glass substrate (or quartz substrate or silicon substrate).

When the invention disclosed in this specification is applied to such a structure, the active matrix region and the peripheral circuit can be composed of thin film transistors having performance comparable to that of a MOS-FET formed on a single crystal. .

That is, the thin film transistor shown in FIG. 3 constitutes the pixel TFT in the active matrix region, and the CMOS circuit shown in FIGS. 5 to 7 constitutes the peripheral circuit.

Since it is necessary for the thin film transistor arranged in the active matrix region to maintain the electric charge held in the pixel electrode for a predetermined time, it is desirable to make the off current value as small as possible.

Since the active layer of the thin film transistor according to the present invention is formed in the monodomain region, there is substantially no crystal grain boundary that can serve as a path (current path) through which the off current preferentially flows. Therefore, a thin film transistor with a small off-state current can be provided.

On the other hand, a CMOS circuit is often used as the peripheral drive circuit. And in order to improve its characteristics, C
It is necessary to make the characteristics of the N-channel type thin film transistor and the P-channel type thin film transistor forming the MOS circuit uniform as much as possible.

For such a purpose, the CMOS structure as shown in Embodiment 4 (see FIGS. 5 to 7) is optimum.

In this way, it is possible to obtain an integrated active matrix type liquid crystal display device having a structure having preferable characteristics for each circuit.

[Embodiment 11] In this embodiment, an example in which the step of forming the gate insulating film is different from that in Embodiment 3 will be described.

First, a semiconductor thin film including a monodomain region is formed through the same steps as in Example 1, and then only the monodomain region is selectively utilized to form an active layer of a semiconductor device.

Next, 200 to 1500 Å so as to cover the active layer.
An insulating film (silicon oxide film in this embodiment) having a thickness of (800 Å in this embodiment) containing silicon as a main component is formed by CVD or PV.
A film is formed by a vapor phase method typified by method D. At this time, the thickness of the silicon oxide film may be determined in consideration of the final withstand voltage. Further, a silicon oxynitride film or a silicon nitride film can be used instead of the silicon oxide film.

After forming the silicon oxide film, heat treatment is performed in an atmosphere containing a halogen element. The main purpose of this heat treatment is to remove gettering metal residues such as nickel remaining in the active layer. This heat treatment can be carried out in the temperature range of 600 to 1100 ° C, but it is desirable to carry out at a temperature higher than 700 ° C (preferably 800 to 1000 ° C) in order to obtain a sufficient gettering effect.

When a glass substrate is used as the substrate, it is necessary to perform it at 600 to 650 ° C. in consideration of heat resistance. Further, when a highly heat-resistant material such as a quartz substrate is used as the substrate, the upper limit temperature is 1100 ° C (preferably 1000 ° C).
℃) can be increased.

In this embodiment, a quartz substrate is used as the substrate,
The heat treatment is performed in an atmosphere containing 0.5 to 10% (3% in this embodiment) hydrogen chloride (HCl) with respect to oxygen. If the HCl concentration is higher than the above concentration, the surface of the crystalline silicon film will be roughened. At this time, the processing temperature is 95
The temperature shall be 0 ° C and the treatment time shall be 0.5hr.

To form an atmosphere containing a halogen element, HCl, HF, HBr, Cl are added in an oxygen atmosphere.
_One or more kinds of gas selected from ₂ , NF ₃ , F ₂ and Br ₂ may be added.

As a result of this step, the gettering action of the metal element by the halogen element works, and the nickel contained in the active layer is 1 × 10 ¹⁷ atoms / cm ³ or less (preferably 1 × 10 ^16).
Gettering is removed up to atoms / cm ³ or less, more preferably spin density or less). The above concentration is SIM
It is a measurement value obtained from the measurement result of S (secondary mass analysis).

At the interface between the active layer and the silicon oxide film described above, a thermal oxidation reaction proceeds to form a thermal oxide film of about 200 Å. At that time, the final thickness of the active layer is
Setting it to 200 to 300 Å (typically 250 Å) is effective in reducing the off current. In this embodiment, the heat treatment in the atmosphere containing the halogen element is followed by heat treatment in a nitrogen atmosphere at about 950 ° C. for about 1 hr to improve the film quality of the thermal oxide film and the insulating film containing silicon as a main component. ing.

By the way, it is considered that nickel is segregated in the crystal grain boundaries of the crystalline silicon film forming the active layer, but when it is removed, many dangling bonds are generated in the crystal grain boundaries.
The large number of dangling bonds are recombined with each other by heat treatment at 950 ° C. to form crystal grain boundaries with few trap levels.

Further, as a result of the heat treatment in the atmosphere containing the halogen element, the halogen element remains at a high concentration near the interface between the active layer and the gate insulating film. According to SIMS measurement, it exists at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ atoms / cm ³ .

Further, the thermal oxide film formed at the interface between the active layer and the silicon oxide film forms a gate insulating film together with the silicon oxide film. At this time, when the thermal oxide film is formed, the defect level at the interface of the active layer and the interstitial silicon atoms are reduced, so that the interface state between the active layer and the gate insulating film becomes very excellent.

As described above, the metal element such as nickel can be reduced by performing the heat treatment shown in this embodiment. It is very important to reduce the metal element such as nickel in order to improve the reliability as a semiconductor device. Further, the crystalline state of the active layer can be improved, and a gate insulating film having a good interface state can be formed.

As a result of the above, it is possible to realize a semiconductor device having excellent electrical characteristics and high reliability.

[Embodiment 12] This embodiment is an example in the case where attention is paid to improving the interface state between the active layer and the gate insulating film. In particular, this is a technique that exhibits effects when a glass substrate is used as the substrate.

First, a semiconductor thin film including a monodomain region is formed through the same steps as in Example 1, and then the active layer of the semiconductor device is formed by selectively utilizing only the monodomain region. Then, as in Example 11, a silicon oxide film having a thickness of 200 to 1500Å is formed by the CVD method or the PVD method.

In this state, the temperature is 500 to 700 ° C (typically 640
Heat treatment (~ 650 ℃). This temperature range is a temperature set for forming a thermal oxide film without causing distortion or warpage on the glass substrate. Further, this heat treatment may be performed in an atmosphere containing only oxygen or an atmosphere containing a halogen element. Alternatively, the atmosphere may be a wet atmosphere containing water vapor.

[0218] When heat treatment is performed under the conditions of this embodiment,
If it is processed for about 5 to 2 hours, it will be less than several tens of liters (eg
Å) thermal oxide film is formed. Then, the growth of the thermal oxide film is substantially converged to this thickness.

According to the knowledge of the present inventors, fixed charges and defect levels are formed in the vicinity of the polar interface between the active layer and the gate insulating film (a region of about 10 to 30 Å from the interface toward the active layer side and the gate insulating film side). It is not an exaggeration to say that this region determines the interface state between the active layer and the gate insulating film, since the above concentration occurs.

Therefore, in order to obtain a good interface state between the active layer and the gate insulating film, only 10 to 30 Å of the active layer interface is required.
Area is thermally oxidized (active layer is reduced by 10 to 30Å
It is only necessary to eliminate the fixed charges and defect levels near the pole interface by forming a thermal oxide film of ~ 60Å). In other words, it is sufficient to form a thermal oxide film of less than several tens of liters in order to realize a good interface state.

By incorporating the thermal oxidation step as in this embodiment into the present invention, it is possible to manufacture a semiconductor device having excellent characteristics even on a substrate having weak heat resistance such as a glass substrate. Become.

[Embodiment 13] This embodiment shows an example in which a crystalline silicon film (polysilicon film) is used as a gate electrode. FIG. 13 is used for the description.

In FIG. 13A, 1301 is a glass substrate, 1302 is a base film, 1303 is an active layer made of the monodomain region obtained in the process shown in Example 1, 1304.
Is a gate insulating film, and 1305 is a gate electrode made of a polysilicon film having one conductivity.

Next, in this state, impurity ions for imparting one conductivity type to the active layer 1303 are implanted. Then, the impurity regions 1306, 1 are formed by this ion implantation process.
307 is formed.

After the implantation of impurity ions is completed, a silicon nitride film 1308 is formed to a thickness of 0.5 to 1 μm. The film forming method may be any of a low pressure thermal CVD method, a plasma CVD method and a sputtering method. Further, a silicon oxide film may be used instead of the silicon nitride film.

Thus, the state shown in FIG. 13B is obtained.
After the state of FIG. 13B is obtained, next, the silicon nitride film 13 is formed.
08 is etched by the etch-back method and left only on the side wall of the gate electrode 1305. The silicon nitride film left in this way functions as a sidewall 1309.

At this time, the gate insulating film 1304 is left in a state as shown in FIG. 13C by removing the regions other than the regions where the gate electrode 1305 and the sidewalls 1309 serve as a mask.

Then, impurity ions are implanted again in the state shown in FIG. At this time, the dose amount is set higher than the dose amount for the ion implantation. At the time of this ion implantation, the region 131 immediately below the sidewall 1309.
0 and 1311 are not ion-implanted, so that the impurity ion concentration does not change. However, the exposed area 13
In 12 and 1313, a higher concentration of impurity ions will be implanted.

Through the second ion implantation as described above, low concentration impurity regions (LDD regions) 1310 and 1311 having an impurity concentration lower than that of the source region 1312, the drain region 1313 and the source / drain regions are formed. Immediately below the gate electrode 1305 is an undoped region, which serves as a channel formation region 1314.

When the state of FIG. 13C is obtained through the above steps, a titanium film (not shown) having a thickness of 300 Å is formed, and the titanium film and the silicon film are reacted with each other. Then, after the titanium film is removed, a heat treatment such as lamp annealing is performed, so that the source region 1312 and the drain region 13 are formed.
13. Titanium silicides 1315 to 1317 are formed on the exposed surface of the gate electrode 1305. (Figure 13 (D))

Note that a tantalum film, a tungsten film, a molybdenum film, or the like can be used instead of the titanium film in the above steps.

Next, a silicon oxide film is formed as an interlayer insulating film 1318 to a thickness of 5000Å to form a source wiring 1319, a drain wiring 1320, and a gate wiring 1321. Thus, the TFT having the structure shown in FIG. 13D is completed.

The TFT having the structure shown in this embodiment has wiring and T
Since the connection with the FT is made through the titanium silicides 1315 to 1317, good ohmic contact can be realized.

[Embodiment 14] A semiconductor device in this specification refers to all devices that function by using a semiconductor, and an active matrix electro-optical device having a structure as shown in Embodiment 10. (Liquid crystal display devices, EL display devices, EC display devices, etc.) and applied products incorporating such electro-optical devices are also included in the category.

In this embodiment, the applied product will be described with reference to the drawings. Examples of semiconductor devices utilizing the present invention include TV cameras, head mounted displays, car navigations, projections (front and rear types), video cameras, personal computers and the like. A brief description will be given with reference to FIG.

FIG. 14A shows a mobile computer, which has a main body 2001, a camera section 2002, and an image receiving section 200.
3, an operation switch 2004, and a display device 2005. The present invention is applied to the display device 2005 and an integrated circuit incorporated in the device.

FIG. 14B shows a head mounted display, which is composed of a main body 2101, a display device 2102, and a band portion 2103. Two display devices 2102 having a relatively small size are used.

FIG. 14C shows a car navigation system, which includes a main body 2101, a display device 2102, and operation switches 2.
103 and an antenna 2104. The present invention can be applied to the display device 2102 and an integrated circuit inside the device. The display device 2202 is used as a monitor, but since the main purpose is to display a map, it can be said that the allowable range of resolution is relatively wide.

FIG. 14D shows a mobile phone, which is the main body 23.
01, voice output unit 2302, voice input unit 2303, display device 2304, operation switch 2305, antenna 230
6. The present invention can be applied to the display device 2304 and an integrated circuit inside the device.

FIG. 14E shows a video camera, which includes a main body 2401, a display device 2402, a voice input section 2403, operation switches 2404, a battery 2405, and an image receiving section 24.
06. The present invention can be applied to the display device 2402 and an integrated circuit inside the device.

FIG. 14F shows a front projection, which is composed of a main body 2501, a light source 2502, a reflection type display device 2503, an optical system (including a beam splitter and a polarizer) 2504, and a screen 2505.
Since the screen 2505 is a large screen used for presentations such as conferences and conference presentations, the display device 2503 is required to have high resolution.

In addition to the electro-optical device shown in this embodiment, it can be applied to portable information terminal equipment such as rear projection and handy terminal. As described above, the application range of the present invention is extremely wide, and the present invention can be applied to display media in all fields.

[0243]

As an effect of the present invention, it is possible to realize the formation of a monodomain region which can be regarded as a substantially single crystal on a substrate having an insulating surface. Then, an active layer of a semiconductor device such as a thin film transistor can be formed using a crystalline silicon film having crystallinity comparable to that of a single crystal.

Therefore, it is possible to construct a semiconductor circuit having performance comparable to that of an integrated circuit using a known single crystal wafer.

[Brief description of drawings]

FIG. 1 is a diagram showing characteristics of a lateral growth region.

FIG. 2 is a diagram showing a process for forming a semiconductor thin film having a monodomain region.

3A to 3D are diagrams showing a manufacturing process of a semiconductor device.

FIG. 4 is a diagram showing an active layer formed in a monodomain region.

5A to 5C are diagrams illustrating a manufacturing process of a semiconductor device.

FIG. 6 illustrates a manufacturing process of a semiconductor device.

7A to 7C are diagrams illustrating a manufacturing process of a semiconductor device.

FIG. 8 is a diagram showing a manufacturing process of a semiconductor device.

FIG. 9 is a diagram showing a structure of a DRAM.

FIG. 10 is a diagram showing a configuration of SRAM.

FIG. 11 is a diagram showing a problem of an SOI structure.

FIG. 12 is a diagram showing a composition table of an artificial quartz target.

13A to 13D are diagrams illustrating a manufacturing process of a semiconductor device.

FIG. 14 is a diagram for explaining an example of an applied product.

[Explanation of symbols]

 101 Nickel Introduced Region 102 Lateral Growth Region 103 Crystal Grain Boundary 104 Bonding Interface 201 Glass Substrate 202 Silicon Oxide Film 203 Amorphous Silicon Film 204 Silicon Oxide Film 205 Nickel Introduced Region 206 Water Film Containing Nickel 207 Crystalline Silicon Film 208 Crystal Growth direction 209 crystalline silicon film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 21/336 H01L 29/78 627G 627E (72) Inventor Kenji Fukunaga 398 Hase, Atsugi, Kanagawa Stock Company Semiconductor Energy Research Institute

Claims (26)

[Claims] 1. A semiconductor thin film formed on a substrate having an insulating surface, wherein the semiconductor thin film has a crystallinity improved by irradiation with laser light or strong light having energy equivalent to the laser light. A semiconductor thin film having a region, wherein the monodomain region is formed by collecting a plurality of columnar or acicular crystals substantially parallel to the substrate. 2. The semiconductor thin film according to claim 1, wherein the monodomain region is substantially free of crystal grain boundaries. 3. A semiconductor thin film formed on a substrate having an insulating surface, the semiconductor thin film being substantially improved in crystallinity by irradiation with laser light or intense light having energy equivalent to the laser light. 1. A semiconductor thin film having a monodomain region in which no crystal grain boundary exists, wherein the monodomain region is formed by collecting a plurality of columnar or needle-like crystals substantially parallel to the substrate. 4. A step of forming an amorphous silicon film on a substrate having an insulating surface by a low pressure thermal CVD method, a step of selectively forming a silicon oxide film on the amorphous silicon film, A step of holding a metal element that promotes crystallization in the amorphous silicon film; a step of transforming at least a part of the amorphous silicon film into a crystalline silicon film by heat treatment; And a step of removing the amorphous silicon film and / or the crystalline silicon film with a laser beam or intense light having an energy equivalent to the laser beam to turn the crystalline silicon film into a monodomain region. A semiconductor thin film, which is manufactured through at least the step of transforming. 5. The semiconductor thin film according to claim 1, wherein the monodomain region has a film thickness of 150 to 450 Å. 6. The semiconductor thin film according to claim 1, wherein the outer edge portion of the monodomain region is raised by irradiation with laser light or strong light having energy equivalent to that of the laser light. 7. The semiconductor thin film according to claim 1, wherein a film thickness of an outer edge portion of the monodomain region is larger than a film thickness of the monodomain region. 8. The semiconductor thin film forming the monodomain region according to claim 1, wherein hydrogen is 1 × 10 ^15.
A semiconductor thin film, which is added at a concentration of 1 × 10 ²¹ atoms / cm ³ . 9. A step of forming an amorphous silicon film by a low pressure thermal CVD method on a substrate having an insulating surface, a step of selectively forming a silicon oxide film on the amorphous silicon film, A step of holding a metal element that promotes crystallization in the amorphous silicon film; a step of transforming at least a part of the amorphous silicon film into a crystalline silicon film by heat treatment; And a step of irradiating the amorphous silicon film and / or the crystalline silicon film with laser light or strong light having an energy equivalent to the laser light. Alternatively, a method for manufacturing a semiconductor thin film is characterized in that the crystalline silicon film is transformed into a monodomain region by a step of irradiating strong light having an energy equivalent to that of the laser light. 10. The method for producing a semiconductor thin film according to claim 9, wherein the crystalline silicon film is formed by assembling a plurality of columnar or acicular crystals substantially parallel to the substrate. 11. The quartz substrate according to claim 9, wherein the substrate is a quartz substrate having a silicon oxide film formed by a sputtering method using an artificial quartz target or a silicon substrate having a thermal oxide film formed on the surface thereof. Method for manufacturing semiconductor thin film. 12. The metal element for promoting crystallization according to claim 9, wherein Fe, Co, Ni, Ru, Rh, Pd,
A method of manufacturing a semiconductor thin film, wherein one or more kinds selected from Os, Ir, Pt, Cu, and Au are used. 13. A semiconductor device having an active layer formed of a semiconductor thin film formed on a substrate having an insulating surface, wherein the semiconductor thin film is irradiated with laser light or intense light having energy equivalent to the laser light. A monodomain region having improved crystallinity, wherein the monodomain region is formed by assembling a plurality of columnar or acicular crystals substantially parallel to the substrate, and the active layer is composed of only the monodomain region. A semiconductor device characterized by the above. 14. The semiconductor device according to claim 13, wherein the active layer has substantially no crystal grain boundaries. 15. A semiconductor device having an active layer made of a semiconductor thin film formed on a substrate having an insulating surface, wherein the semiconductor thin film is irradiated with laser light or intense light having energy equivalent to the laser light. A monodomain region having improved crystallinity, wherein the monodomain region is formed by collecting a plurality of columnar or needle-like crystals substantially parallel to the substrate, and the active layer is composed of only the monodomain region. Is a semiconductor device characterized by having substantially no crystal grain boundaries. 16. Low pressure thermal CVD on a substrate having an insulating surface.
A step of forming an amorphous silicon film by a method, a step of selectively forming a silicon oxide film on the amorphous silicon film, and a metal element that promotes crystallization of the amorphous silicon film. A step of holding the amorphous silicon film, a step of transforming at least a part of the amorphous silicon film into a crystalline silicon film by heat treatment, a step of removing the silicon oxide film, and a step of removing the amorphous silicon film and / or the amorphous silicon film. A step of irradiating the crystalline silicon film with a laser beam or strong light having an energy equivalent to that of the laser beam to transform the crystalline silicon film into a monodomain region. A semiconductor device characterized in that an active layer is formed of. 17. Low pressure thermal CVD on a substrate having an insulating surface.
A step of forming an amorphous silicon film by a method, a step of selectively forming a silicon oxide film on the amorphous silicon film, and a metal element that promotes crystallization of the amorphous silicon film. A step of holding the amorphous silicon film, a step of transforming at least a part of the amorphous silicon film into a crystalline silicon film by heat treatment, a step of removing the silicon oxide film, and a step of removing the amorphous silicon film and / or the amorphous silicon film. A step of irradiating the crystalline silicon film with a laser beam or strong light having an energy equivalent to the laser beam to transform the crystalline silicon film into a monodomain region, and forming an active layer using only the monodomain region. A step of forming, an step of forming an insulating film containing silicon as a main component so as to cover the active layer by a vapor phase method, and a heat treatment in an atmosphere containing a halogen element to promote the crystallization in the active layer. A step of forming a thermal oxide film on an interface between the active layer and the insulating film containing silicon as a main component while gettering and removing the group element; and the silicon including the thermal oxide film by heat treatment in a nitrogen atmosphere. And a step of improving the film quality of an insulating film containing as a main component. 18. The stacked film according to claim 17, wherein the laminated film including an insulating film containing silicon as a main component and a thermal oxide film functions as a gate insulating film, and a halogen is provided near an interface between the active layer and the gate insulating film. A semiconductor device characterized in that the element is present in a high concentration. 19. The semiconductor device according to claim 13, wherein the thickness of the active layer is 150 to 450 Å. 20. In any one of claims 13 to 17, hydrogen is contained in the active layer in an amount of 1 × 10 ¹⁵ to 1 × 10 ²¹ atoms / cm 3.
A semiconductor device characterized by being added at a concentration of ³ . 21. A semiconductor device having an active layer made of a semiconductor thin film formed above an IC integrated on a silicon substrate, wherein the semiconductor thin film has a laser beam or energy equivalent to the laser beam. It has a mono-domain region whose crystallinity is improved by irradiation of strong light, and the mono-domain region is formed by collecting a plurality of columnar or needle-like crystals substantially parallel to the substrate, and is composed of only the mono-domain region A semiconductor device characterized in that the active layer has substantially no crystal grain boundaries. 22. In manufacturing a semiconductor device having an active layer made of a semiconductor thin film, a step of forming an amorphous silicon film on a substrate having an insulating surface by a low pressure thermal CVD method, and the amorphous silicon film. A step of selectively forming a silicon oxide film thereon, a step of holding a metal element that promotes crystallization in the amorphous silicon film, and a step of heating at least part of the amorphous silicon film. A step of transforming into a crystalline silicon film, a step of removing the silicon oxide film, and a laser beam or strong light having an energy equivalent to the laser beam with respect to the amorphous silicon film and / or the crystalline silicon film. And a step of irradiating the crystalline silicon film into a monodomain region by the step of irradiating the laser beam or intense light having an energy equivalent to the laser beam, The method for manufacturing a semiconductor device characterized by forming the active layer by using only the serial monodomain region. 23. In manufacturing a semiconductor device having an active layer made of a semiconductor thin film, a step of forming an amorphous silicon film on a substrate having an insulating surface by a low pressure thermal CVD method, and the amorphous silicon film. A step of selectively forming a silicon oxide film thereon, a step of holding a metal element that promotes crystallization in the amorphous silicon film, and a step of heating at least part of the amorphous silicon film. A step of transforming into a crystalline silicon film, a step of removing the silicon oxide film, and a laser beam or strong light having an energy equivalent to the laser beam with respect to the amorphous silicon film and / or the crystalline silicon film. Irradiation to transform the crystalline silicon film into a monodomain region, a step of forming an active layer using only the monodomain region, and an insulating layer containing silicon as a main component to cover the active layer. By a vapor phase method, and by heat treatment in an atmosphere containing a halogen element to gettering and removing the metal element that promotes the crystallization in the active layer, and the active layer and the silicon as a main component. A step of forming a thermal oxide film at the interface with the insulating film; and a step of improving the film quality of the silicon-based insulating film including the thermal oxide film by heat treatment in a nitrogen atmosphere. A method for manufacturing a characteristic semiconductor device. 24. In Claim 22 or Claim 23,
A method for manufacturing a semiconductor device, wherein the crystalline silicon film is formed by collecting a plurality of columnar or needle-like crystals that are substantially parallel to the substrate. 25. In Claim 22 or Claim 23,
A method for manufacturing a semiconductor device, wherein a quartz substrate having a silicon oxide film formed on a surface thereof by a sputtering method using an artificial quartz target or a silicon substrate having a thermal oxide film formed on a surface thereof is used as a substrate. 26. In Claim 22 or Claim 23,
Metal elements that promote crystallization include Fe, Co, Ni,
A method for manufacturing a semiconductor device, wherein one or more kinds selected from Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au are used.