JPH09282426A - Card and its communicating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IC card which can communicate with an external equipment irrelevantly to a use style, etc., according to proper communication conditions and is inexpensive. SOLUTION: This IC card 10 is equipped with a CPU 18, a rewritable nonvolatile memory 16, and a read-only memory 12 which stores a program that the CPU 18 can execute, and the read-only memory 12 has a communication control program prescribing the operation of the CPU 18 when a communication with the outside is made; and the nonvolatile memory 16 has communication condition information prescribing the conditions of the communication carried out according to the communication control program and the CPU 18 executes the communication program by using the communication condition information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC card for communicating with the outside and a communication method therefor.

[0002]

2. Description of the Related Art In recent years, an IC card has attracted attention as a new information storage medium replacing a magnetic card. Especially,
Since an IC card with a built-in CPU can realize high security, it is expected to be used in various fields of the advanced information society.

In general, IC cards are ROM, RAM, E
It has three types of memories of the EPROM and a CPU for accessing these memories. The EEPROM is a rewritable non-volatile memory and stores data such as personal information relating to the IC card user. RAM is CPU
Is a volatile memory used as a work area when executing a program. The ROM is a read-only memory and stores a program to be executed by the CPU.

One of the programs stored in the ROM is related to communication between the IC card and external equipment (hereinafter referred to as "communication program"). Communication between the IC card and the external device is performed according to a predetermined agreement by the CPU executing the communication program. Here, the predetermined agreement means so-called communication conditions such as positive logic / negative logic of a communication signal, length of response interval time in data transmission, and the like. Communication conditions are generally I
The most suitable one is determined for each usage mode of the C card.

[0005]

By the way, the ROM in which the communication program is stored is a read-only memory as described above, and a new program cannot be additionally written to this ROM later. Therefore, the conventional IC card can only perform communication according to the only condition specified by the communication program stored in the ROM. Therefore, when the same IC card is used for various applications, there is a problem that appropriate communication may not always be performed between the IC card and an external device depending on the application.

[0006] Further, an IC card that operates according to the new communication condition may be required due to a change in the usage mode of the IC card or a change in the communication condition in the system using the IC card. Conventionally, in such a case, it has been necessary to newly produce a ROM that stores a communication program according to the new communication condition. However, ROM requires enormous cost and time for its development. Therefore, if the ROM is redesigned and remanufactured each time the usage of the IC card is changed, the IC card development / production cost and development time increase, and the IC card price increases. There was also a problem.

[0007] Therefore, an object of the present invention is to provide an inexpensive IC card which can always communicate with an external device according to appropriate communication conditions irrespective of the usage mode and the like.

[0008]

In order to solve the above problems, the invention according to claim 1 provides a CPU (18), a rewritable nonvolatile memory (16), and a program executable by the CPU. Read-only memory to store (1
2), wherein the read-only memory has a communication control program that defines the operation of the CPU when communicating with the outside, and the non-volatile memory follows the communication control program. The CPU having communication condition information that defines the condition of communication to be executed.
Executes the communication program using the communication condition information.

According to a second aspect of the present invention, in the IC card according to the first aspect, the communication condition information contained in the nonvolatile memory can be rewritten by an external command. The invention according to claim 3 is a CPU
(18) and a rewritable nonvolatile memory (16)
And a read-only memory (12) for storing a program executable by the CPU, wherein the communication-related program stored in the non-volatile memory is stored in the non-volatile memory. It is characterized in that it communicates with the outside by executing it using information about the condition.

[0010]

Hereinafter, an embodiment of the present invention will be described in more detail with reference to the drawings. FIG. 1 is a diagram showing a configuration of an IC card according to the present invention.
As shown in FIG. 1, an IC card 10 includes a ROM 12 that is a read-only memory and a RAM that is a volatile memory.
14, EEPR, a non-volatile memory that can be rewritten at any time
It has an OM 16 and a CPU 18 for accessing these memories.

The IC card 10 has a plurality of contacts (Vcc to GND) for exchanging electric signals and the like with a reader / writer (not shown). When the IC card is inserted into the reader / writer, the contacts of the reader / writer
It is connected to the contacts of the C card, and exchanges electrical signals. Different electrical signals are assigned to the respective contacts. For example, Vcc is a contact for receiving the supply of power supply voltage required for the IC to operate, and I / O
Is a contact (serial port) for the CPU to communicate with the reader / writer. The CPU 18 is given a command from the reader / writer via the contact, executes the program stored in the ROM 12 or the EEPROM 16 in accordance with the command, and as a result, the EEPROM
Access 16 etc.

FIG. 2 is a diagram showing an example of addresses allocated to each memory of the present embodiment. In this embodiment, for example, the ROM 12 has H'0000 to H'1FF.
F, H'2000 to H'21FF, EEP in RAM14
Addresses H'3000 to H'3FFF are assigned to the ROM 16. Note that, in this specification, “H ′” added before a numerical value means that the numerical value is represented based on a hexadecimal number.

The ROM 12 stores a program for the CPU 18 to interpret and execute. Specifically, a communication control program, an Answer to Reset processing program, and a command & response processing program are stored. Command and response processing program is CPU1
8 has various subprograms that execute according to commands sent from the outside. Upon receiving the command from the reader / writer, the CPU 18 reads a code (hereinafter referred to as “INS”) indicating the type of the command recorded in the first 1 byte of the command, and selects a subprogram corresponding to the INS, Run. In the subprogram, the parameter following the INS of the command is referred to and the process corresponding to the command is performed. Also, response data indicating the processing result is generated.

The Answer to Reset processing program is a program for editing the data for making a so-called initial response in a predetermined address of the RAM 14. This program is executed after the IC card 10 and the reader / writer are connected and a reset command is transmitted from the reader / writer.

The communication control program is a program that defines the operation of the CPU 18 when the IC card 10 receives a command from the reader / writer or sends a response. For example, as a result of executing the Answer to Reset processing program, or a result of executing the command and response processing program, the initial response data or response data edited in the RAM 14 is read by executing the communication control program. -Sent to the writer.

The communication control program has four parameters for setting communication conditions, namely "FST" and "C".
It has “NV”, “ICT” and “TCT”. FS
T is a parameter indicating whether the 1-byte data to be transmitted is transmitted from the most significant bit (MSB First) or the least significant bit (LSB First). CNV is a parameter indicating whether the communication is performed based on positive logic / negative logic. The ICT and TCT shall each send the first 1-byte data of the response after the time interval (response interval time) between each byte to be sent and the last 1-byte data of the command have been sent. Is a parameter that represents the minimum time (command-response switching minimum waiting time) until is allowed.

In the present embodiment, the communication control program itself does not have regular data to be substituted into the above four parameters. Regular data of these parameters is stored as communication condition data at a predetermined address of the EEPROM 16. FIG. 3 is a diagram showing a memory map of the EEPROM 16. As illustrated, the communication condition data is stored in the first 4 bytes of the EEPROM 16. As the communication condition data, data corresponding to each of FST, CNV, ITC and TCT is stored in order from the head of the address.

For example, when data is transferred to the address H'3000 in order from the most significant bit during communication (M
“00” is stored in SB First), and a value other than “00” is stored when the least significant bit is sequentially transferred (LSB First). Further, in the address H'3001, "00" is stored when the communication is performed based on the positive logic, and a value other than "00" is stored when the communication is performed based on the negative logic. Furthermore, in the addresses H'3002 and H'3003, the response interval time or the command-response switching minimum waiting time is stored in units of etu.
1 etu is the time required to transmit or receive a 1-bit signal. The area other than the first 4 bytes of the EEPROM 16 is an area for storing so-called user data.

In the present embodiment, the IC card is read from the reader / writer to the IC.
By giving a Change Transmission parameter command (hereinafter referred to as “CTP command”) to the card 10, the above four types of data are written or rewritten in the EEPROM 16. FIG. 4 is a diagram showing the format of the CTP command. The CTP command is composed of 5 bytes of data. The first byte is a code (INS) indicating the type of command. The second byte to the fifth byte are data regarding FST, CNV, ICT and TCT in order.

As described above, since the CTP command is prepared, in this embodiment, after the IC card 10 is manufactured and before it is distributed to the card user, the I
It is possible to write arbitrary communication condition data in the EEPROM 16 according to the usage of the C card 10. Further, even after the IC card 10 is issued, if the communication standard of the system using the IC card is changed, the communication condition data is rewritten using the CTP command and the IC card 10 is reissued. Without this, it is possible to provide a card user with a card that conforms to the new communication standard.

Next, the operation of the IC card 10 will be described. FIG. 5 is a flow chart showing the operation of the IC card 10. When the IC card 10 and the reader / writer are connected and the IC card is reset (activated) by the reader / writer, the CPU 18 performs the activation process in the IC card 10 and then the ROM 12 to make an initial response. Run the Answer to Reset program stored in. As a result, the data for initial response is edited at a predetermined address in the RAM 14 (S502). Further, the head address of the edited data is substituted into the variable out_data_address, and the length of the data is substituted into the variable out_data_length (S504).

Next, the CPU 18 executes the communication control program stored in the ROM 12 (S506).
That is, the CPU 18 uses out_data_address and ou
The data in the memory area specified by t_data_length is transmitted to the reader / writer. After that, the CPU 18
The system waits for a command to be sent from the reader / writer.

When the command is transmitted, the CPU 18
Confirm that the received command has no error (S5
08). If there is an error in the command (S508: Y
In es), an error code or the like for notifying the reader / writer of the fact is written in a predetermined address of the RAM 14 (S518). Then, using the written error code, the response data is edited at a predetermined address of the RAM 14 (S514), and the start address and the data length thereof are out_data_address and out_, respectively.
It is stored in data_length (S516). After this, CP
The U18 returns to the processing of step 506 and transmits the response data edited in the RAM 14 to the reader / writer.

On the other hand, if it is determined in step 508 that there is no error in the command (S508: No), then it is determined whether the command is a CTP command (S510). As a result, when it is determined that the command is not the CTP command (S510: No), the process proceeds to step 512 and the process of the command is executed (S5).
12). That is, the CPU 18 reads the INS of the first byte of the command, selects the subprogram corresponding to the INS from the command & response processing program, and executes it.

On the other hand, when it is determined in step 510 that the transmitted command is the CTP command (S510: Yes), the CPU 18 executes the CTP command. FIG. 6 is a flowchart showing the processing contents when the CTP command is executed. When the CTP command is executed, first, the data arranged in the second byte of the CTP command is stored in the address H'of the EEPROM 16.
It is written in 3000 (S602). Address H'3
After writing the data to 000,
The data from the 3rd byte to the 5th byte of the CTP command are stored in addresses H'3001 to H'30
03 is sequentially written (S604 to S606).

Step 512 or step 520 of FIG.
In step 514, after the processing of each command is completed, steps 514 and 516 are executed in the same manner as when the error processing is executed in step 518, and a response corresponding to the execution of each command is transmitted to the reader / writer.

7 to 10 are flow charts showing the processing contents of the communication control program executed in step 506 of FIG. In these flow charts, step 71
From 0 to step 758, the processing contents relating to the response transmission to the reader / writer are shown. In addition, after step 760, the processing contents relating to command reception from the reader / writer are shown.

When the execution of the communication control program is started, the CPU 18 firstly addresses the addresses H'3000 to H'3.
The data of 003, that is, the communication condition data stored in the EEPROM 16 is sequentially read and is substituted into the variables FST, CNV, ICT and TCT of the communication control program (S702 to S708). That is, regular data is given to each parameter of the communication control program.

When the substitution of the communication condition data into the parameters is completed, next, the above step 512, 518 or 5 is executed.
In any one of 20, the series of processes for outputting the edited response data to the predetermined address of the RAM 14 byte by byte is performed. First, bit _counter
Is set to 8 (S710). bit _counter is
This is a variable for counting the number of times of the loop processing that follows.

Then, the initial value of the variable n designating the bit of the 1-byte data to be transmitted is determined based on the contents of the FST. Here, first in step 712,
It is determined whether the FST value is "0". FST
Is 0, it is determined that the communication condition set by the FST is MSB First (S71).
2: Yes), and 8 indicating the most significant bit of 1-byte data is substituted for n (S714). Conversely, FST is "0"
If not, the communication condition is determined to be LSB First (S712: No), and 1 indicating the least significant bit is substituted for n.

Next, a signal (so-called start bit) notifying that 1-byte data is to be transmitted is output to the reader / writer (S718). Specifically, a signal of logic level "Low" (when non-logic is adopted as the communication condition) is output for one bit (1 etu).

Next, the value of bit_counter is confirmed (S720). If bit_counter is not "0", it is determined that there is data to be output (S72).
0: No), 1 of the address indicated by out_data_address
The byte data is read (S722).

Next, the contents of the data substituted into the FST are confirmed again (S724), and the FST is MSB first.
, The value of n is decremented by 1 (S726),
When FST indicates LSB first, the value of n is incremented by 1 (S728). Next, the contents of the data assigned to CNV and the value (bn) of the nth bit of the 1-byte data to be output are confirmed (S73).
0, S732, S734). As a result, the positive logic communication condition is designated by CNV (CNV = 0) and bn = 0.
Or if a negative logic communication condition is designated by CNV (CNV ≠ 0) and bn ≠ 0, a signal of logical level “Low” is output for one bit (1 etu) (S736). ). In addition, conditions other than the above (CNV
= 0 and bn ≠ 0, or CNV ≠ 0 and bn = 0), a signal of logical level “High” is output for one bit (S738).

Next, the parity for the bit data output so far is calculated (S740), and
The value of bit_counter is decremented by 1. After this, the process returns to step 720 again, and steps 720 to 7
The processing up to 42 is continued until bit_counter becomes 0.

On the other hand, in step 720, bit_co
If unter is 0, it is determined that all bits of the 1-byte data have been output (S718: Yes),
Next, the parity transmission process is started. That is, C
The value of NV and the value of the parity data calculated in step 740 are confirmed (S744, S).
746, S748). As a result, when the positive logic communication condition is designated by CNV (CNV = 0) and the parity data is 0, or when the negative logic communication condition is designated by CNV (CNV ≠ 0) and the parity data is 0
If not, a signal of logic level "Low" is output for one bit (S750). In addition, conditions other than the above (CNV = 0 and parity data ≠ 0, or CNV
≠ 0 and parity data = 0), logical level "H"
One bit of the "high" signal is output (S752).

When the transmission of parity data is completed, ou
The value of t_data_length is subtracted by 1 (S754),
Even in the result of this subtraction, out_data_length
If the value of is not 0 (S756: No), it means that there is still data to be output.
Therefore, after the delay process (S758) for the response interval time designated by the ICT is performed, the process returns to step 710 again, and the process of transmitting the next 1-byte data is executed.

On the other hand, in step 756, out_da
If ta_length is 0 (S756: Yes), it is determined that all data to be transmitted has been transmitted,
Next, a process for receiving a command from the reader / writer is executed.

In the command receiving process, first, input_
data_address and input_data_length are initialized (S760). Where input_data_address and
input_data_length is the received command RAM
It is a variable into which information for specifying in which area of 14 the information is stored. That is, input _data_
The start address of the memory area where the command is stored is assigned to address. Further, 0 is temporarily assigned to input_data_length.

Next, steps 712 to 716 described above.
The same process is performed, and the value of n is 8 or 1 depending on whether the communication condition is MSB first or LSB first.
Is set to (S761, S762, S764). Furthermore, bit_counter and parity_data are set to the initial value 0 (S766, S768).

Next, the CPU 18 determines whether or not the start bit is detected in the signal input via the I / O contact (S770). As a result, if the start bit is not detected, the reader
It is determined whether or not the time from the transmission of 1-byte data from the writer exceeds the character waiting time (hereinafter referred to as "CWT") (S79).
8). If the time does not exceed CWT, the leader
It is determined that the writer will continue to send commands,
The process returns to step 770 again. Conversely, the time is C
If it exceeds WT, it is determined that the command transmission is completed, and the process of step 842 is executed. That is, a delay process of a time corresponding to the number of bits obtained by subtracting 10 from the value set in TCT is performed. With this delay processing, a series of processing of the communication control program ends.

On the other hand, when the start bit is detected in step 770, the process for receiving the 1-byte data transmitted from the reader / writer is started. Specifically, first, a delay process for 1.5 bits is performed (S772), and then the data input from the I / O contact is sampled. As a result of sampling, the logic level of the sampled signal is "Lo
w ”and CNV is 0 (S77
6: Low, S778: Yes), or when the logic level of the signal is “High” and CNV is not 0 (S776: High, S780: No), b
0 is substituted for n (S782). Also, in the case other than the above conditions (S776: Low, S778: No, and S
776: High, S780: Yes), 1 for bn
Is substituted (S784).

Next, it is judged whether FST is 0,
Subtract 1 from n according to the result (S786: Yes, S
788) or add 1 to n (S786: No,
S790). Furthermore, 1 is added to bit_counter (S7
92), and the parity data is calculated using the value of bn determined in step 782 or step 784 (S794). That is, the exclusive OR of the data stored in the parity_data and the data stored in the bn is calculated, and the result is assigned to the parity_data.

Upon completion of the above processing, step 796
In, the value of bit_counter is referred to. as a result,
If the value is not yet 8, the flow returns to step 772 to receive the next 1-bit data. on the other hand,
If the value is 8, it means that all 1-byte data has been fetched, so that the process for fetching parity data is executed next.

First, after a delay process of one bit is performed, the signal input through the I / O line is sampled (S810, S812). Then, based on the logic level of the sampled signal, prity_
If bit is 0 (S814: Low, S816: Yes, or S814: High, S818: No, S8
20) or 1 (S814: Low, S816:
No, or in the case of S814: High and S818: Yes, in S822).

Next, the value of parity_bit and step 79
The parity is confirmed by comparing the value of parity_data calculated in 4. As a result, if the values of both variables match, it is determined that the data has been received normally, and the process of step 828 is executed next. If the values do not match, receiving_f
After the data “error” is assigned to lag (S826), the process of step 828 is executed.

At step 828, 1-byte data is edited from the eight data b1 to b8. further,
The edited 1-byte data is input _data_address
Stored in the address specified by (S83
0). Finally, input_data_address and input_da
After the value of ta_length is incremented by 1, (S832, S
834), the process returns to step 770, and the receiving process of the next 1-byte data is performed.

As described above, in the IC card 10 of this embodiment, the ROM 12 stores the communication control program, and the EEPROM 16 stores the communication condition data which is a parameter of the communication control program and sets the communication condition. ing. When the IC card 10 communicates with the reader / writer, the CPU 18 makes the EEPROM 16
The communication control program stored in the ROM 12 is executed by referring to the communication condition data stored in.

Therefore, according to this embodiment, the EEP
By setting the communication condition data in the ROM 16 to be appropriate, an IC card that meets any communication condition can be provided. Moreover, in the present embodiment, since the same ROM is used without providing different types of ROMs and an IC card that conforms to various different communication standards is provided, mass-produced and inexpensive ROMs are used. Therefore, it is possible to provide an inexpensive IC card.

Further, in this embodiment, Change Transmiss
It is possible to write or rewrite the communication condition data in the EEPROM 16 at any time by using the ion parameter command. Therefore, the IC card according to the present embodiment does not need to be reissued by rewriting the communication condition data of the EEPROM 16 as appropriate, even if the communication standard is revised after the card is issued. It is possible to comply with communication standards.

In the present specification, "IC card"
Means a portable information recording medium including a CPU and a memory accessed by the CPU, the CPU operating according to a program stored in the memory. Therefore, the "IC card" is not limited to, for example, a so-called card shape having a planar and square shape, but may be a medium having a coin shape or the like and having a CPU and a memory.

[0051]

As described above in detail, according to the invention according to claim 1, it is possible to provide an inexpensive IC card which can be used for various different communication conditions while using the same dedicated memory. Is. Further, according to the invention of claim 2, it is possible to provide an IC card that appropriately corresponds to a new communication standard even when the communication standard is revised. Further, according to the invention of claim 3, the communication condition can be arbitrarily defined by the condition related to the communication stored in the non-volatile memory regardless of the content of the program related to the communication stored in the read-only memory. It is possible to provide an IC card communication method.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an IC card according to the present invention.

FIG. 2 is a diagram exemplifying addresses assigned to respective memories of the IC card according to the present invention.

FIG. 3 is a diagram showing a memory map of the EEPROM 16;

FIG. 4 is a diagram showing a format of a CTP command.

5 is a flowchart showing the operation of the IC card 10. FIG.

FIG. 6 is a flowchart showing processing contents when a CTP command is executed.

FIG. 7 is a flowchart showing a part of processing contents of a communication control program.

FIG. 8 is a flowchart showing a part of the processing contents of the communication control program, which is a continuation of the part shown in FIG. 7;

9 is a flowchart showing a part of the processing contents of the communication control program and showing the continuation of the part shown in FIG. 8;

10 is a flowchart showing a part of the processing contents of the communication control program and showing the continuation of the part shown in FIG. 9;

[Explanation of symbols]

 10 IC card 12 ROM 14 RAM 16 EEPROM 18 CPU

Claims (3)

[Claims] 1. An IC card comprising a CPU, a rewritable nonvolatile memory, and a read-only memory for storing a program executable by the CPU, the read-only memory communicating with the outside. A communication control program that prescribes the operation of the CPU at the time, the non-volatile memory has communication condition information that prescribes the condition of communication executed according to the communication control program, and the CPU is the communication device. An IC card, characterized in that the communication program is executed using condition information. 2. The IC card according to claim 1, wherein the communication condition information stored in the nonvolatile memory can be rewritten by an external command. 3. A communication method for an IC card comprising a CPU, a rewritable non-volatile memory, and a read-only memory that stores a program executable by the CPU, wherein the communication-related program stored in the non-volatile memory. A communication method for an IC card, characterized in that the communication with the outside is performed by executing the above-mentioned using the information regarding the communication conditions stored in the non-volatile memory.