JPH09281186A - Circuit for measuring delay time characteristic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify measuring of delay time characteristic of a critical path by activating the critical path by a single control signal and observing the direct input and output of signal with the same control signal. SOLUTION: The input of a circuit 20 including a signal transmission path of the largest delay time among an integrated circuit 1, namely, a critical path is connected to data outputs Q of FF10, FF12, FF13 synchronously operating with a clock signal CLK. The output of the circuit 20 is connected to a data input D of an FF11 synchronously operating with the signal CLK. A scan path function is provided in every FF10-13. Means 102, 103 for activating the circuit 20 including the critical path, a means 100 for feeding a direct input signal to the critical path and a means 101 for allowing the observation of an output of the critical path are provided. Since the same control signal SFT2 enables the observation of the direct input signal to the circuit 20 and the output signal, a delay time characteristic can be measured simply.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay time characteristic measuring circuit, and more particularly to a delay time characteristic measuring circuit of an integrated circuit.

[0002]

2. Description of the Related Art Conventionally, AC such as delay time characteristics of an integrated circuit is used.
As a method of measuring the electrical characteristics, there is a method of measuring the oscillation frequency of a ring oscillator formed by connecting inverter logic in odd stages to easily measure the AC characteristics (for example, the conventional technique disclosed in JP-A-62-63462). (See the description of).

FIG. 5 is a circuit diagram showing an example of a conventional delay time characteristic measuring circuit. The integrated circuit 1 sandwiched by the flip-flops 10, 11, 12, 13 in the integrated circuit 1
Among them, there is a circuit 20 including a signal propagation path having the longest delay time, that is, a critical path, and a ring oscillator 201 having inverters connected in odd stages is provided separately from the circuit 20.

The circuit 20 including the critical path receives the output Q of the flip-flops 11, 12, 13 as an input, and the output of the circuit 20 is connected to the input terminal D of the flip-flop 10. The critical path in this case is a signal path from the output Q of the flip-flop 10 to the input D of the flip-flop 11.

Next, the operation of the above conventional example will be described. The ring oscillator 201 is oscillated by applying a control signal to the input CNT, and the oscillation signal is output to the output RO. The delay time characteristic of the integrated circuit 1 is obtained by measuring the oscillation frequency of the oscillation signal output to the output RO. That is, the delay time for each inverter stage is obtained from the number of stages of the inverters constituting the ring oscillator 201 and the oscillation frequency, and this is the delay time characteristic of the integrated circuit 1.

[0006]

The prior art described above is
The problem is that the delay time characteristic of the critical path, which is the most problematic, cannot be measured.

This is because the delay time characteristics are significantly different between the inverter in the ring oscillator and the circuit in the critical path.

Therefore, the present invention has been made in view of the above circumstances, and an object thereof is a circuit capable of measuring a delay time of a critical path which is the most problematic in terms of delay time characteristics of an integrated circuit. To provide.

[0009]

To achieve the above object, the delay time characteristic measuring circuit according to the present invention is a means for selecting and inputting a fixed level to a predetermined memory element group by a control signal in a synchronous integrated circuit. A means for selecting and inputting a desired signal to the first storage element by a control signal, and a second storage element connected to the output of the combination circuit having the output of the first storage element as an input. , Is provided.

[0010]

Embodiments of the present invention will be described below. With reference to FIG. 1, an embodiment of the present invention includes means 102 for activating a circuit 20 including a critical path which is a path (path) that restricts the overall circuit operation speed among signal propagation paths of a logic circuit. 103, means 100 for directly applying an input signal to the critical path, and means 101 for observing the output of the critical path.

The critical path 20 can be activated by one control signal SFT2, and the same control signal SFT2 enables direct input of a signal to the critical path 20 and observation of the output of the critical path 20. The delay time characteristics of 20 can be easily measured.

Next, an embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1, a flip-flop 10, 12, which operates in synchronization with a clock signal CLK, is input to a circuit 20 including a signal propagation path having the largest delay time, that is, a critical path in the integrated circuit 1. A circuit 2 to which the data output Q of 13 is connected and which includes a critical path
The data input D of the flip-flop 11 that operates in synchronization with CLK is connected to the output of 0.

Flip-flops 10, 11, 12, 13
All have a scan path function. Here, the scan path function selects an input SI (scan-in) different from the normal data input D to the flip-flop, and whether the data stored in the flip-flop is the normal data D or the scan-in SI. Control signal input S for controlling
By providing an FT and connecting SI inputs and outputs Q of the flip-flops in a one-to-one connection, it is possible to confirm the stored data in the cascade-connected flip-flops by a simple procedure. Say that. The scan-path method is a flip-flop in which flip-flops in an LSI during test are connected like a shift register (scan path), a test signal is input from an external terminal, and an operation result of a combinational circuit unit is converted to a shift register. It is a method of reading through.

For the input SI of the flip-flop 10, the output of the flip-flop of the preceding stage connected to the scan path and the signal SI2 that can be input from the outside of the integrated circuit 1 can be selectively switched by the control signal SFT2 that can be input from the outside. The selection circuit 100 is connected to the input SI of the flip-flop 12, and the selection circuit 102 capable of selectively switching between the output of the previous flip-flop and the signal fixed to “1” is connected to the input SI of the flip-flop 13. A selection circuit 103 capable of selectively switching between the output of the preceding flip-flop and a signal fixed at "0" is connected.

At the input SFT of the flip-flop 11,
A selection circuit 101 capable of selectively switching between a control signal SFT for the scan path function and a signal fixed at "0" is connected. The selection circuits 101, 102, and 103 can be selectively switched by the same control signal SFT2 as 100.

Next, the operation of the embodiment of the present invention will be described in detail with reference to the drawings.

Normally, as the CLK signal of the integrated circuit 1, a clock signal having a constant period T1 as shown in FIGS. 2 and 3A is given, and the integrated circuit 1 receives the clock signal C.
It operates in synchronization with LK.

In this embodiment, the period T1 of the clock signal CLK is assumed to be 50 ns. In order to activate the critical path 20 of FIG. 1, that is, to propagate an arbitrary signal to the signal path from the output Q of the flip-flop 10 to the input D of the flip-flop 11, the flip-flop 1
It is necessary to fix the output Q of 2 to "1" level and the output Q of the flip-flop 13 to "0" level.

In this embodiment, the output Q of each flip-flop can be easily set by the selection circuit 102 and the selection circuit 103.
It can be fixed to "1" and "0", respectively.
For example, the selection control signal SFT of the selection circuits 102 and 103
When "0" is input to 2, the output of the preceding flip-flop connected to the scan path of each flip-flop is selected, and when "1" is input to SFT2, the selection circuit 1
It is assumed that 02 selects a "1" fixed signal and the selection circuit 103 selects a "0" fixed signal.

Then, the scan path control signal SFT of each flip-flop is used to fetch data from SI as the data input of each flip-flop.
That is, when the scan path mode is set, a normal scan path connection is realized by giving "0" to SFT2.
If "1" is given to SFT2, the flip-flops 12 and after the first clock after switching the scan path mode,
"1" and "0" are set in 13 respectively, and the outputs of the respective flip-flops are fixed to "1" and "0", respectively, and the critical path is activated.

With the critical path activated,
When a signal as shown in FIG. 2 and FIG. 3B is applied to the SI2 input of the selection circuit 100, the selection circuit 100 is connected to the flip-flop 10 in the scan path when the SFT2 is “0”. 2B is input to the flip-flop 10, and SI 2 is selected when SFT2 is “1”, the output Q of the flip-flop 10 is output to the output Q of FIG. , And the waveform as shown in FIG. 3C is output.

Here, assuming that the delay time of the critical path (delaying delay time) is Tpd1, a signal as shown in (D) of FIG. 2 is given to the input D of the flip-flop 11.

FIG. 2D shows that, with respect to the clock cycle T1 = 50 ns of the integrated circuit 1, Tpd1 is 40 ns and the flip-flop 10 to the flip-flop 1 are within the cycle T1.
The data propagates to 1 and can be considered as a good product as the integrated circuit 1.

In this case, this can be determined by checking whether "1" is set in the flip-flop 11 at time t. In order to fetch the signal of FIG. 2D into the flip-flop 11, the flip-flop 11 must be in the normal mode, that is, the state other than the scan path mode, but by the selection circuit 101 connected to the SFT input of the flip-flop 11, At this time, the flip-flop 11 is set to enter the normal mode.

That is, the selection circuit 101 is arranged so that the normal scan path control signal SFT is selected when SFT2 is "0" and the signal fixing the flip-flop 11 to the normal mode is selected when SFT2 is "1". Therefore, when activating the critical path,
At the same time, the flip-flop 11 enters the normal mode, and the signal of FIG.

In the example of FIG. 1, the flip-flop is in the normal mode when the SFT input is "0", and is in the scan path mode when the SFT input is "1".

The signal waveform diagram of FIG. 3E shows the integrated circuit 1
Of the delay time of the critical path is Tp
FIG. 6 is a diagram showing a case where d2 = 60 ns, which is longer than the operation cycle T1 of the integrated circuit 1. In this case, at time t, that is, within the period T1, the output signal of the flip-flop 10, that is, the signal of "1" level cannot be propagated to the input of the flip-flop 11, so "0" is set in the flip-flop 11. To be done. As a result, the delay characteristic of the integrated circuit 1 can be determined to be defective.

To confirm whether the data set in the flip-flop 11 is "1" or "0", S after the time t.
FT2 is set to “0”, and 10, 12, 13 in the integrated circuit 1 are set.
By enabling the scan path connection of each flip-flop and switching the flip-flop 11 to the scan path mode at the same time, the data of the flip-flop 11 is read and confirmed.

Next, a second embodiment of the present invention will be described.

The difference between this embodiment and the first embodiment is that
In FIG. 1, the circuit 20 is a circuit having a signal propagation path having an arbitrary delay characteristic other than the critical path which is the signal propagation path having the longest delay time in the integrated circuit 1. As a result, not only the critical path,
The delay time characteristic of an arbitrary signal propagation path can be measured.

Next, a third embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

The present embodiment differs from the first and second embodiments in that the output of the flip-flop 11 for taking in the output of the activated signal propagation path of the circuit 20 is connected to the external pad of the integrated circuit 1. External output buffer 1 connected to 111
10 is connected. As a result, the signal set in the flip-flop 11 at time t is "0" or "1".
It can be determined by observing the signal appearing on the external pad 111. That is, it is possible to make the determination in a shorter test time than that in the scan pass mode.

[0034]

As described above, according to the present invention,
This has an effect that the delay time characteristic of the critical path itself of the integrated circuit can be measured with a simple setting.

This is because, in the present invention, the critical path is activated only by switching one control signal,
This is because the direct input to the critical path is enabled and the selection circuit that takes the output of the critical path into the flip-flop is provided.

Further, according to the present invention, there is an effect that the delay time characteristic of the critical path can be measured without impairing the original function and delay time characteristic of the integrated circuit.

This is because, in the present invention, all the selection circuits provided for measuring the delay time characteristics of the critical path are connected to the input for the scan function of the flip-flop.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a diagram for explaining the embodiment of the present invention and is a waveform diagram showing a good judgment operation.

FIG. 3 is a diagram for explaining the embodiment of the present invention and is a waveform diagram showing a defect determination operation.

FIG. 4 is a circuit diagram showing another embodiment of the present invention.

FIG. 5 is a circuit diagram showing a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Integrated circuit 10-13 Flip-flop with scan function 20 Circuit including critical path (or circuit including arbitrary signal propagation path) 100-103 Selection circuit 110 External output buffer 111 External pad 201 Ring oscillator

Claims (7)

[Claims] 1. In a synchronous integrated circuit, means for selecting and inputting a fixed level to a predetermined memory element group by a control signal, and means for selecting and inputting a desired signal to a first memory element by a control signal. And a second memory element connected to the output of a combinational circuit having the output of the first memory element as an input, the delay time characteristic measuring circuit. 2. A delay time characteristic measuring circuit, wherein each memory element according to claim 1 is composed of a memory element having a scan path function. 3. A memory element with a scan path function according to claim 2, wherein the second memory element connected to the output of the combination circuit according to claim 1 is fixed to the scan control input by the control signal. A delay time characteristic measuring circuit having means for inputting a level. 4. The delay time characteristic measuring circuit according to claim 1, wherein all the control signals are the same signal. 5. A means for causing the output of the second storage element connected to the output of the combinational circuit to output the signal directly to the output terminal of the integrated circuit. The delay time characteristic measuring circuit according to any one of 4 to 4. 6. A circuit for inputting a predetermined signal to a critical path to activate the circuit including a critical path input between flip-flops, and a means for selectively applying an input signal directly to the critical path. A delay time characteristic measuring circuit comprising: means for observing the output of the critical path, wherein the delay time characteristic of the critical path can be measured. 7. The delay time characteristic measuring circuit according to claim 6, wherein the flip-flop has a scan path function, and signals for controlling the respective means are the same signal.