JPH0927624A - Thin film transistor, manufacture of thin film transistor and liquid crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a thin film transistor, which has little leakage current at a turn-off time of the transistor, by a method wherein the transistor is formed into one of a constitution, wherein the transistor is provided with sidewalls formed on the sidewalls of a gate electrode and impurity regions, which are provided in a semiconductor film, are formed on the sides of the sidewalls, are used as source/drain regions and have an LDD structure, and the like. SOLUTION: A thin film transistor has a semiconductor film 2 formed on an insulating substrate 1, a gate insulating film 3 formed on the film 2 and a gate electrode 4 formed on the film 3. Moreover, the transistor is formed into one of a constitution, wherein it has sidewalls 7 formed on the sidewalls of the electrode 4 and impurity regions 6, which are provided in the film 2, are formed on the sides of both sidewalls 7, are used as source/drain regions and have an LDD structure. For example, after lowconcentration impurities are implanted in the polycrystalline silicon film 2 using the first sidewalls 7 as masks, the electrode 4 and the sidewalls 7 are covered with a resist 8 and high-concentration impurities are implanted in the film 2 using the resist 8 as a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a thin film transistor (Thi
The present invention relates to an n film transistor, a manufacturing method thereof, and a liquid crystal display (LCD).

[0002]

2. Description of the Related Art In LCDs as liquid crystal devices, in recent years, a simple matrix system to an active matrix system has been actively developed. The active matrix system includes a TFT type in which a thin film transistor is attached to each pixel and a diode type in which a non-linear diode is attached to each pixel. Among them, the TFT type holds the voltage applied during the selection period until the next scanning by utilizing its switching characteristic and pixel capacitance, and it is possible to easily obtain high contrast and halftone with a large capacitance. it can.

However, this TFT type LCD is
There is a problem that leakage current is generated during the so-called TFT OFF period in which the applied voltage is held. Therefore, in order to reduce this leakage current, an LDD structure transistor is adopted. Although various methods of manufacturing a transistor having an LDD structure have been proposed, a technique of forming in self-alignment in order to simplify the process is disclosed in, for example, Japanese Patent Application Laid-Open No. 4-1043.
No. 4 (H01L21 / 336).

This conventional technique will be described with reference to FIGS. Step A (see FIG. 19): Insulating substrate (eg, quartz glass)
In order to form a polycrystalline silicon film 52 on 51 and use this polycrystalline silicon film 52 as an active layer of a thin film transistor, the polycrystalline silicon film 52 is processed into a predetermined shape by photolithography technique and dry etching technique by RIE method. To do.

A reduced pressure C is formed on the polycrystalline silicon film 52.
A silicon oxide film as the gate insulating film 53 is deposited by using the VD method. Step B (see FIG. 20): After depositing a polycrystalline silicon film on the gate insulating film 53 by a low pressure CVD method, impurities are implanted into the polycrystalline silicon film and heat treatment is performed to activate the impurities. .

Next, after depositing a silicon oxide film 54 on this polycrystalline silicon film by the atmospheric pressure CVD method, the polycrystalline silicon film and the silicon are formed by using the photolithography technology and the dry etching technology by the RIE method. The oxide film 54 is processed into a predetermined shape. The polycrystalline silicon film is used as the gate electrode 55. Next, a low concentration impurity is implanted into the polycrystalline silicon film 52 using the gate electrode 55 and the silicon oxide film 54 as a mask by a self-alignment technique to form a low concentration impurity region 56a.

Step C (see FIG. 21): After thinly depositing a silicon oxide film on the gate insulating film 53 and the silicon oxide film 54 by a low pressure CVD method, this is anisotropically etched back to form the gate. A side wall 57 is formed on the side wall of the electrode 55. And the sidewall 5
Using the mask 7 as a mask, a high concentration impurity is implanted into the polycrystalline silicon film 52 to form a high concentration impurity region 56b.

Thus, the LD as the source / drain
The impurity region 56 having the D structure is formed in a self-aligned manner.

[0009]

In the conventional example, L
Although the leakage current at the time of OFF can be reduced by adopting the DD structure, it is necessary to suppress this leakage current as much as possible in order to apply it to devices such as LCDs which will have higher performance in the future. In view of such a problem, the present invention provides a thin film transistor having a small leakage current when turned off.

Further, the present invention provides a liquid crystal display having excellent display characteristics by using a thin film transistor which has a small leakage current when turned off.

[0011]

A thin film transistor according to claim 1 is a semiconductor film formed on an insulating substrate, a gate insulating film formed on the semiconductor film, and a gate insulating film formed on the gate insulating film. And a side wall formed on the side wall of the gate electrode, and an impurity region having an LDD structure to be a source / drain formed on both sides of the side wall of the semiconductor film.

According to a second aspect of the present invention, a thin film transistor has a polycrystalline silicon film formed on an insulating substrate, a gate insulating film formed on the polycrystalline silicon film, and a gate insulating film formed on the gate insulating film. Gate electrode, an insulating side wall formed on the side wall of the gate electrode, and an impurity region of LDD structure serving as a source / drain formed on both sides of the side wall of the polycrystalline silicon film. It was done.

According to a third aspect of the present invention, there is provided a method of manufacturing a thin film transistor, which includes a step of forming a semiconductor film on an insulating substrate, a step of forming a gate electrode on the semiconductor film via a gate insulating film, and the gate. First on at least the sidewall of the electrode
Forming a sidewall of the first sidewall, a step of implanting a low concentration impurity into the semiconductor film using the first sidewall as a mask, and forming a second sidewall on at least a sidewall of the first sidewall. And the process of
Implanting a high concentration impurity into the semiconductor film using the second sidewall as a mask.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a thin film transistor, wherein a step of forming a polycrystalline silicon film on an insulating substrate and a step of forming a gate electrode on the polycrystalline silicon film via a gate insulating film. And a step of forming a first sidewall on at least a sidewall of the gate electrode,
Using the first sidewall as a mask, implanting a low concentration impurity into the polycrystalline silicon film, covering the gate electrode and the first sidewall with a resist, and using the resist as a mask And a step of implanting a high-concentration impurity into the crystalline silicon film.

According to a fifth aspect of the present invention, in the method of manufacturing a thin film transistor, a step of forming an amorphous silicon film on an insulating substrate, a step of heat-treating the amorphous silicon film to form a polycrystalline silicon film, A step of forming a gate electrode on the polycrystalline silicon film via a gate insulating film, a step of forming a first sidewall on at least a side wall of the gate electrode, and a step of using the first sidewall as a mask. A step of implanting a low concentration impurity into the polycrystalline silicon film, a step of covering the gate electrode and the first sidewall with a resist, and a step of using the resist as a mask,
And a step of implanting a high-concentration impurity into the polycrystalline silicon film.

In the method of manufacturing a thin film transistor according to claim 6, heat treatment for activating the implanted impurities is performed. A method for manufacturing a thin film transistor according to claim 7 is the thin film transistor according to claim 1 or 2, or the thin film transistor manufactured by the method according to any one of claims 3 to 6 as a pixel driving element. It is used.

According to an eighth aspect of the present invention, there is provided a method of manufacturing a thin film transistor, wherein the thin film transistor according to any one of the first and second aspects, or the thin film transistor manufactured by the method of manufacturing the thin film transistor according to any one of the third to sixth aspects is used for driving a pixel. And a peripheral drive circuit element.

[0018]

That is, in the semiconductor film (polycrystalline silicon film), side walls are provided not on both sides of the gate electrode but on the side wall of the gate electrode, and L is provided on both sides of this side wall.
By forming the DD structure, the leakage current when the transistor is off is reduced.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment embodying the present invention is shown in FIGS.
8 will be described. Step 1 (see FIG. 1): A SiO ₂ film 1a having a film thickness of 3000 to 5000 Å is formed on a substrate 1 made of quartz glass, alkali-free glass or the like by a normal pressure or low pressure CVD method at a forming temperature of 350 ° C.

The film thickness of the SiO ₂ film 1a is such that impurities in the substrate 1 are changed to SiO ₂ by heat treatment or beam irradiation in a later process.
_{2 It} must have a thickness that does not diffuse through the membrane to the upper layer,
The range of 1000-6000Å is appropriate, 2000-60
When it is set to 00Å, the diffusion preventing effect is good, and among them, the case of 3000 to 5000Å is most suitable. Further, a SiN film may be used instead of the SiO ₂ film 1a,
In this case, the film thickness is preferably in the range of 1000 to 5000 Å, and the effect of preventing diffusion is good when the film thickness is in the range of 2000 to 5000 Å, and among them, the case of 2000 to 3000 Å is most suitable.

Step 2 (see FIG. 2): the insulating thin film 1a
An amorphous silicon film 2a (film thickness 500Å) is formed on the above. When this amorphous silicon film 2a is used as an active layer of a TFT, if the active layer is too thick, the off-current of the polycrystalline silicon TFT increases, and if it is too thin, the on-current decreases. The thickness of the crystalline silicon film 2a is appropriately in the range of 400 to 800Å,
When set to Å, the characteristics are good, among which 500-60
The case of 0Å is most suitable.

There are the following methods for forming the amorphous silicon film 2a. Method using low pressure CVD: In order to form a silicon film by the low pressure CVD method, thermal decomposition of monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used. When monosilane is used, it becomes amorphous when the treatment temperature is 550 ° C. or lower, and becomes polycrystalline when the treatment temperature is 620 ° C. or higher. Then, at 550 to 620 ° C., the amount of amorphous containing fine crystals increases, and as the temperature decreases, the amount of amorphous becomes closer to amorphous and the amount of fine crystals decreases. Therefore, the amount of fine crystals in the amorphous silicon film 2a can be adjusted only by changing the temperature condition.

Method using plasma CVD method: To form an amorphous silicon film by plasma CVD method, thermal decomposition of monosilane or disilane in plasma is used.
In the actual process, the above method is adopted, and an amorphous silicon film containing no microcrystals is formed under the conditions of gas used: monosilane and temperature: 350 ° C. Step 3 (see FIG. 3): The surface of the amorphous silicon film 2a is scanned with a XeCl excimer laser beam having a wavelength λ = 308 nm to perform an annealing treatment, and the amorphous silicon film 2
A is melted and recrystallized to form a polycrystalline silicon thin film 2.

At this time, the laser conditions are as follows: annealing atmosphere: 1 × 10 ⁻⁴ Pa or less, substrate temperature: room temperature to 600 ° C.,
Irradiation energy density: 100 to 500 mJ / cm ² , scanning speed: 1 to 10 mm / sec (actually 0.1 to 1
It is possible to scan at a speed in the range of 00 mm / sec). Step 4 (see FIG. 4): In order to use the polycrystalline silicon film 2 as an active layer of a thin film transistor, the polycrystalline silicon film 2 is processed into a predetermined shape by a photolithography technique and a dry etching technique such as an RIE method.

Then, on the polycrystalline silicon film 2,
An LTO film (Low Temperature Oxide: silicon oxide film) 3 (thickness 1000 Å) as a gate insulating film is formed by using the low pressure CVD method. Step 5 (see FIG. 5): Amorphous silicon film (film thickness 2000Å) 4 is formed on the gate insulating film 3 by the low pressure CVD method.
a is deposited. The amorphous silicon film 4a is doped with impurities (arsenic or phosphorus for N type and boron for P type) at the time of formation, but it may be deposited in a non-doped state and then the impurities may be implanted.

Next, using a sputtering method, tungsten silicide (WSi ₂ ) is formed on the amorphous silicon film 4a.
A film 4b (thickness 1000Å) is formed. In the sputtering method, an alloy target of W silicide is used. Then, after depositing the silicon oxide film 5 on the W silicide film 4b by the atmospheric pressure CVD method, the photolithography technology and the dry etching technology by the RIE method are used.
The polycrystalline silicon film 4a, the W silicide film 4b and the silicon oxide film 5 are processed into a predetermined shape. The amorphous silicon film 4a is used as the gate electrode 4 having a polycide structure together with the W silicide film 4b.

The gate electrode 4 may be made of polycrystalline silicon alone. Step 6 (see FIG. 6): A silicon oxide film is deposited on the gate insulating film 3 and the silicon oxide film 5 by an atmospheric pressure CVD method, and the entire surface of the gate electrode 4 is anisotropically etched back. A sidewall 7 (thickness 1500 Å) is formed on the side of the silicon oxide film 5.

Then, by the self-alignment technique, with the sidewall 7 as a mask, the polycrystalline silicon film 2 is accelerating voltage: 80 KeV and the dose amount is 3 × 10 ¹³ cm ^-2 .
Phosphorus (P) ions are implanted as impurities to form low-concentration impurity regions 6a. Step 7 (see FIG. 7): The sidewalls 7 and the silicon oxide film 5 are covered with a resist 8 and again the self-alignment technique is used to form the polycrystalline silicon film 2 using the resist 8 as a mask.
By accelerating voltage: 80 KeV and a dose amount of 3 × 10 ¹⁵ cm ⁻² , phosphorus (P) ions are implanted as an impurity to form a high-concentration impurity region 6b.
A source / drain region 6 having a ly doped drain structure is formed.

Step 8 (see FIG. 8): In this state, RTA
(Rapid Thermal Annealing) method is used for rapid heating. The RTA conditions at this time are: heat source: xenon arc lamp, temperature: 800 to 900 ° C. (pyrometer), atmosphere: N ₂ , time: 1 to 2 seconds. Although heating by the RTA method uses high temperature, it can be completed in an extremely short time, so that there is no concern that the substrate 1 will be deformed. In particular, such lamp annealing is suitable for activating impurities because it raises the temperature of the amorphous portion.

At this time, a thin amorphous silicon film may be formed on the device surface before the RTA in order to easily absorb the heat of the RTA. Due to this rapid heating, the impurities in the source / drain regions 7 are activated and the amorphous silicon film 4a is polycrystallized, and further, the polycrystal silicon film 4a and the W silicide film 4b are formed.
The sheet resistance of the gate electrode 4 having the polycide structure is reduced to about 22Ω / □.

The sheet resistance of the activated source / drain regions 6 is 1.5 kΩ / □ for the N type and 1.2 kΩ / □ for the P type, and the high temperature heat treatment by the diffusion furnace used in the high temperature process is performed. Is equivalent to. By this activation, impurities are diffused and the source / drain regions 6
May spread slightly below the sidewall 7. Therefore, both sides of the sidewall in the present invention include a state in which impurities diffuse and spread to the lower side of the sidewall.

Through the above steps, the thin film transistor (T
FT: Thin Film Transistor (A) is formed. In this example, as described above, the unique L
Since a thin film transistor having a DD structure is formed, it is OFF compared to a conventional thin film transistor having an LDD structure.
The leakage current can be greatly reduced.

According to an experiment by the present inventor, in an N-channel transistor, gate width W / gate length L = 400/3.
5, drain voltage VD = -12V, gate voltage VG = -1
When set to 6V, the leakage current I _OFF of the thin film transistor of the conventional structure was 100 pA, whereas the leakage current I _OFF of the thin film transistor of the present invention is 10 pA.
It was reduced to 1/10.

Step 9 (see FIG. 9): After removing the resist 8,
Plasma oxide film (film thickness 2000Å) on the entire surface of the device
And a silicon oxide film (film thickness 2000 by the atmospheric pressure CVD method)
An interlayer insulating film 9 having a laminated structure with (4) is formed. Then, using an electric furnace, in a hydrogen (H ₂ ) atmosphere, at a temperature of 45
It is heated at 0 ° C. for 12 hours and further subjected to hydrogen plasma treatment. By performing such hydrogenation treatment, hydrogen atoms are bonded to crystal defect portions of the polycrystalline silicon film, the crystal structure is stabilized, and the electrolytic effect mobility is increased.

After that, photolithography technology and RIE
A contact hole 10 that contacts the source / drain region 6 is formed in the interlayer insulating film 9 by using a dry etching technique according to the method. Step 10 (see FIG. 10): A wiring layer having a laminated structure of Ti / Al—Si alloy / Ti is deposited by a magnetron sputtering method, and a source / drain electrode is formed by using a photolithography technique and a dry etching technique by an RIE method. Process as 11.

Step 11 (see FIG. 11): The silicon oxide film 1 as a protective film is formed on the entire surface of the device by the CVD method.
2 (may be a silicon nitride film) is thinly deposited. Step 12 (see FIG. 12): SOG (Sp
The in-on-glass film 13 is applied three times to flatten the irregularities on the device surface. Step 13 (see FIG. 13): Since the SOG film 13 has a poor resist releasability and easily absorbs water, a silicon oxide film 14 (silicon) is formed on the SOG film 13 as a protective film by the CVD method. A nitride film may be used) is thinly deposited.

Step 14 (see FIG. 14): Using the photolithography technique and the dry etching technique by the RIE method, the silicon oxide film 12 / SOG film 13 / silicon oxide film 14 is contacted to the source / drain electrode 11. A hole 15 is formed, and an ITO film 16 as a pixel electrode is sputter-deposited on the entire surface of the device. Step 15 (see FIG. 15): Finally, after forming a resist pattern on the ITO film 16 in order to process the ITO film 16 into an electrode shape, first, by the RIE method using hydrogen bromide gas (HBr). When the ITO film 16 is etched and the silicon oxide film 14 starts to be exposed, the gas is switched to chlorine gas (Cl ₂ ) and the etching is continued until the end.

Step 16 (see FIG. 16): LC
After forming the one-sided TFT substrate of D, the common electrode 1 is formed on the surface.
The transparent insulating substrate 18 on which 7 is formed is made to face each other, and liquid crystal is sealed between the substrates 1 and 18 to form a liquid crystal layer 19, thereby completing the pixel portion of the LCD. FIG. 17 is a block diagram of the active matrix type LCD in this embodiment.

Each scanning line (gate wiring) G1 is provided in the pixel portion 20.
・ ・ ・ Gn, Gn + 1 ・ ・ ・ Gm and each data line (drain wiring) D1 ・ ・
-Dn, Dn + 1 ... Dm are arranged. The gate lines and the drain lines are orthogonal to each other, and the pixels 21 are provided in the orthogonal portions. Each gate wiring is connected to the gate driver 22 so that a gate signal (scanning signal) is applied. Further, each drain wiring is connected to a drain driver (data driver) 23 so that a data signal (video signal) is applied. A peripheral drive circuit 24 is configured by these drivers 22 and 23.

An LCD in which at least one of the drivers 22 and 23 is formed on the same substrate as the pixel section 20 is generally a driver integrated type (driver built-in type).
It is called LCD. The gate drivers 22 may be provided at both ends of the pixel section 20. Further, the drain driver 23 may be provided on both sides of the pixel unit 20.

FIG. 18 shows the gate wiring Gn and the drain wiring Dn.
An equivalent circuit of the pixel 21 provided in a portion orthogonal to is shown. The pixel 21 includes a TFT (similar to the thin film transistor A) as a pixel driving element, a liquid crystal cell LC, and an auxiliary procedure C.
Composed of S. The gate of the TFT is connected to the gate wiring Gn, and the drain of the TFT is connected to the drain wiring Dn. The display electrode (pixel electrode) of the liquid crystal cell LC and the auxiliary capacitance (storage capacitance or additional capacitance) CS are connected to the source of the TFT.

The liquid crystal cell LC and the auxiliary capacitance CS form a signal storage element. The voltage Vcom is applied to the common electrode (electrode opposite to the display electrode) of the liquid crystal cell LC. On the other hand, in the auxiliary capacitor CS, a constant voltage VR is applied to the electrode on the side opposite to the side connected to the source of the TFT. The common electrode of the liquid crystal cell LC is literally a common electrode for all the pixels 21. Further, a capacitance is formed between the display electrode and the common electrode of the liquid crystal cell LC. In addition, in the auxiliary capacitance CS,
The electrode on the side opposite to the side connected to the source of the TFT may be connected to the adjacent gate wiring Gn + 1.

In the pixel 21 thus constructed,
When the gate wiring Gn is set to a positive voltage and a positive voltage is applied to the gate of the TFT, the TFT turns on. Then, the capacitance of the liquid crystal cell LC and the auxiliary capacitance CS are charged by the data signal applied to the drain wiring Dn. On the contrary, when the gate wiring Gn is set to a negative voltage and a negative voltage is applied to the gate of the TFT, the TFT is turned off, and the voltage applied to the drain wiring Dn at that time is the electrostatic capacity and the auxiliary capacity of the liquid crystal cell LC. Held by CS. In this manner, by supplying a data signal to be written to the pixel 21 to the drain wiring and controlling the voltage of the gate wiring, the pixel 21 can hold an arbitrary data signal. The liquid crystal cell L according to the data signal held by the pixel 21.
The transmittance of C changes and an image is displayed.

Here, important characteristics of the pixel 21 are a writing characteristic and a holding characteristic. The writing characteristics are required to sufficiently write a desired video signal voltage to the signal storage element (the liquid crystal cell LC and the auxiliary capacitance CS) within a unit time determined by the specifications of the pixel section 20. The point is whether you can do it. What is required for the holding characteristic is whether or not the video signal voltage once written in the signal storage element can be held for a required time.

The auxiliary capacitance CS is provided in order to increase the electrostatic capacitance of the signal storage element to improve the writing characteristic and the holding characteristic. That is, the liquid crystal cell LC
However, there is a limit to the increase in capacitance due to its structure. Therefore, the auxiliary capacitance CS compensates for the shortage of the electrostatic capacitance of the liquid crystal cell LC. The above embodiment may be modified as follows, and in that case, the same operation and effect can be obtained.

1) In step 2, the amorphous silicon film is formed by a low pressure CVD method using, for example, monosilane gas,
Deposit at a temperature of 580 ° C. As a result, the amorphous silicon film 2a becomes a film containing microcrystals. By polycrystallizing the amorphous silicon film containing microcrystals by the solid phase growth method, the crystal grain size decreases and the mobility slightly decreases, but the crystal growth can be completed in a short time.

2) In step 2, the amorphous silicon film 2
a is atmospheric pressure C regardless of the low pressure CVD method or the plasma CVD method.
VD method, photo-excited CVD method, vapor deposition method, EB (Electron Bea
m) It is formed by any one of a group consisting of a vapor deposition method, an MBE (Molecular Beam Epitaxy) method, and a sputtering method. 3) The threshold voltage (Vth) of the polycrystalline silicon TFT is controlled by doping impurities in the portion corresponding to the channel region of the polycrystalline silicon film 2. In the polycrystalline silicon TFT formed by the solid phase growth method, the threshold voltage tends to shift in the depletion direction in the N-channel transistor and the threshold voltage tends to shift in the enhancement direction in the P-channel transistor. Further, when the hydrogenation treatment is performed, the tendency becomes more remarkable. To suppress the shift of the threshold voltage, the channel region may be doped with impurities.

4) The following steps are carried out instead of the above step 3. Step 3a: By performing a heat treatment at a temperature of about 600 ° C. for about 20 hours in a nitrogen (N ₂ ) atmosphere with an electric furnace,
The amorphous silicon film 2a is solid phase grown to form a polycrystalline silicon film 2. 5) The polycrystalline silicon film 2 formed in the step 3a has many defects such as dislocations in the crystals that form the film, and there is a possibility that an amorphous portion remains between the crystals, which causes a leak current. There are many fears.

Therefore, after the step 3a, the substrate 1 is rapidly heated by the RTA method or the laser annealing method to improve the film quality of the polycrystalline silicon film 2. In the embodiments 4) and 5), when the laser beam is not used, the above S
The iO ₂ film 1a is not particularly necessary. 6) The electric furnace takes a longer time than laser irradiation, but since a large number of substrates can be processed at one time, the steps 4) and 5) have substantially high throughput. Therefore, the subsequent heat treatment for activating the impurity region, for example,
A laser beam annealing method may be used instead of the RTA method. The RTA method has an advantage that it can be completed in a short time, and the laser annealing method has an advantage that the sheet resistance can be lowered because the temperature of the impurity region can be raised high.

7) In step 5, P other than the sputtering method is used.
The W silicide film 4b is formed by the VD method (vacuum vapor deposition method, ion plating method, ion beam deposition method, cluster ion beam method, etc.). 8) MoSi ₂ , T as an alternative to W silicide
iSi _2, TaSi _2, refractory metal silicide such as CoSi _2, other, W, Mo, Co, Cr , Ti, may be used a high-melting metal such as Ta.

9) Not only the planar type, but also the polycrystalline silicon TFT of any structure such as an inverted planar type, a staggered type and an inverted staggered type. 10) Applicable not only to polycrystalline silicon TFTs but also to insulated gate semiconductor devices in general. In addition, photoelectric conversion elements such as solar cells and optical sensors, bipolar transistors, static induction transistors (SIT: Static Induction Transistor).
It is applied to all semiconductor devices using a polycrystalline silicon film such as or).

11) Instead of the resist 8, a sidewall made of an insulating material such as a silicon oxide film or a silicon nitride film is used. The forming method is similar to that of the sidewall 7.

[0053]

The present invention has the following excellent effects. 1) It is possible to provide a high-performance thin film transistor with a small leakage current when turned off. 2) A liquid crystal display having excellent display characteristics can be provided by using a thin film transistor that has a small leakage current when turned off.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining a manufacturing process of an embodiment embodying the present invention.

FIG. 6 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining a manufacturing process of an embodiment embodying the present invention.

FIG. 8 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view for explaining a manufacturing process of an embodiment embodying the present invention.

FIG. 10 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 11 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 12 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 13 is a cross-sectional view for explaining a manufacturing process of an embodiment embodying the present invention.

FIG. 14 is a cross-sectional view for explaining the manufacturing process for one embodiment of the present invention.

FIG. 15 is a cross-sectional view for explaining the manufacturing process for one embodiment of the present invention.

FIG. 16 is a cross-sectional view for explaining the manufacturing process for one embodiment of the present invention.

FIG. 17 is a block diagram of an active matrix type LCD.

FIG. 18 is an equivalent circuit diagram of a pixel.

FIG. 19 is a cross-sectional view for explaining the manufacturing process of the conventional example.

FIG. 20 is a cross-sectional view for explaining the manufacturing process of the conventional example.

FIG. 21 is a cross-sectional view for explaining the manufacturing process of the conventional example.

[Explanation of symbols]

 1 Insulating Substrate 2a Amorphous Silicon Film 2 Polycrystalline Silicon Film 3 Gate Insulating Film 4 Gate Electrode 6a Low Concentration Impurity Region 6b High Concentration Impurity Region 6 Source / Drain Region 7 Sidewall (First Sidewall) 8 Resist (First) 2 side walls)

Claims (8)

[Claims] 1. A semiconductor film formed on an insulating substrate,
A gate insulating film formed on the semiconductor film, a gate electrode formed on the gate insulating film, a sidewall formed on a sidewall of the gate electrode, and both sides of the sidewall of the semiconductor film. And an impurity region having an LDD (Lightly Doped Drain) structure to be a source / drain formed in the above. 2. A polycrystalline silicon film formed on an insulating substrate, a gate insulating film formed on the polycrystalline silicon film, a gate electrode formed on the gate insulating film, and A thin film transistor comprising: an insulating sidewall formed on a sidewall of a gate electrode; and an impurity region having an LDD structure, which is a source / drain formed on both sides of the sidewall of the polycrystalline silicon film. . 3. A step of forming a semiconductor film on an insulating substrate, a step of forming a gate electrode on the semiconductor film via a gate insulating film, and a first sidewall on at least a side wall of the gate electrode. A step of implanting a low concentration impurity into the semiconductor film using the first sidewall as a mask, and a step of forming a second sidewall on at least a sidewall of the first sidewall. And a step of implanting a high-concentration impurity into the semiconductor film using the second sidewall as a mask. 4. A step of forming a polycrystalline silicon film on an insulating substrate, a step of forming a gate electrode on the polycrystalline silicon film via a gate insulating film, and a step of forming a gate electrode on at least a sidewall of the gate electrode. Forming a first sidewall, implanting a low concentration impurity into the polycrystalline silicon film using the first sidewall as a mask, and covering the gate electrode and the first sidewall with a resist And a step of implanting a high-concentration impurity into the polycrystalline silicon film using the resist as a mask, the method of manufacturing a thin film transistor. 5. A step of forming an amorphous silicon film on an insulating substrate, a step of heat-treating the amorphous silicon film to form a polycrystalline silicon film, and a gate on the polycrystalline silicon film. Forming a gate electrode via an insulating film; forming a first sidewall on at least a side wall of the gate electrode; and using the first sidewall as a mask to form a low concentration film on the polycrystalline silicon film. A step of implanting an impurity, a step of covering the gate electrode and the first sidewall with a resist, and a step of implanting a high concentration impurity into the polycrystalline silicon film using the resist as a mask. Method for manufacturing thin film transistor. 6. The method of manufacturing a thin film transistor according to claim 3, wherein a heat treatment for activating the implanted impurities is performed. 7. A liquid crystal using the thin film transistor according to claim 1 or 2 or the thin film transistor manufactured by the method of manufacturing a thin film transistor according to claim 3 as a pixel driving element. display. 8. The thin film transistor according to claim 1 or 2, or the thin film transistor manufactured by the method for manufacturing a thin film transistor according to any one of claims 3 to 6, is used as a pixel driving element and a peripheral driving circuit element. A liquid crystal display characterized by that.