JPH0927512A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0927512A
JPH0927512A JP17343995A JP17343995A JPH0927512A JP H0927512 A JPH0927512 A JP H0927512A JP 17343995 A JP17343995 A JP 17343995A JP 17343995 A JP17343995 A JP 17343995A JP H0927512 A JPH0927512 A JP H0927512A
Authority
JP
Japan
Prior art keywords
electrodes
wire
signal line
electrode
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17343995A
Other languages
Japanese (ja)
Inventor
Ryuichiro Mori
隆一郎 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17343995A priority Critical patent/JPH0927512A/en
Publication of JPH0927512A publication Critical patent/JPH0927512A/en
Pending legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent the dimensional increase of a semiconductor element due to the increase of the number of each electrode for a signal line, a power supply line and a ground line by making wires connected to each electrode a different height to each other with respect to the upper surface of a semiconductor element and making a wire from an electrode for a signal line a middle in the height of wires from the other two electrodes. SOLUTION: Each electrode 2a to 2c and each internal lead 3a to 3c are respectively interconnected by a wire 4a for a power supply line, a wire 4b for a signal line and a wire 4c for a ground line. An internal lead 3a for a power supply, an internal lead 3b for a signal line and an internal lead 3c for a ground line are disposed in that order in nearly parallel to the peripheral edge of a semiconductor element on the outside of the semiconductor element. Also, the wires 4a to 4c are disposed so that the height positions are different to each other. That is, the wire 4b for a signal line is made a middle in height, the wire 4a for a power supply line is made to come to an upper position than the wire 4b for a signal line and the wire 4c for a ground line is made to come to a lower position than the wire 4b for a signal line.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は、特に高速な信号処理
を行う半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which performs high speed signal processing.

【０００２】[0002]

【従来の技術】図１０は、従来の半導体装置を示す平面
図、図１１はその側面図である。図中、１は半導体素
子、２ａ〜２ｃは電極であり、２ａは電源線用電極、２
ｂは信号線用電極、２ｃはグランド線用電極である。３
ａ〜３ｂは内部リードであり、３ａは電源線用内部リー
ド、３ｂは信号線用内部リード、３ｃはグランド線用内
部リードである。４ａ〜４ｃは電極２と内部リード３を
結ぶワイヤで、４ａは電源線用電極２ａと電源線用内部
リード３ａとを結ぶワイヤ、４ｂは信号線用電極２ｂと
信号線用内部リード３ｂとを結ぶワイヤ、４ｃはグラン
ド線用電極２ｃとグランド線用内部リード３ｃとを結ぶ
ワイヤである。2. Description of the Related Art FIG. 10 is a plan view showing a conventional semiconductor device, and FIG. 11 is a side view thereof. In the figure, 1 is a semiconductor element, 2a to 2c are electrodes, 2a is a power line electrode, 2
Reference numeral b is a signal line electrode, and 2c is a ground line electrode. 3
Reference numerals a to 3b are internal leads, 3a is an internal lead for a power line, 3b is an internal lead for a signal line, and 3c is an internal lead for a ground line. Reference numerals 4a to 4c are wires connecting the electrodes 2 and the internal leads 3, 4a is a wire connecting the power supply line electrodes 2a and the power supply line internal leads 3a, and 4b is a signal line electrode 2b and the signal line internal leads 3b. Connecting wires 4c are wires connecting the ground wire electrode 2c and the ground wire inner lead 3c.

【０００３】ところで、一般に高速な信号を処理する半
導体装置においては、信号線のインピーダンスの増加を
抑えるため、個々の信号線を電源線とグランド線で挟ん
で配置すると効果的であることが知られている。図１０
において、半導体素子１の外周部にその外周縁部に沿っ
て１列に電極２ａ〜２ｃが配列されており、各信号線用
電極２ｂに対して、電源線用電極２ａとグランド線用電
極２ｃは、それと隣り合わせになるように配置してあ
る。また、各電極２ａ〜２ｃとそれぞれ対向するよう
に、電源線用内部リード３ａ、信号線用内部リード３ｂ
及びグランド線用内部リード３ｃが配列されている。ま
た、各電極２ａ〜２ｃと各内部リード３ａ〜３ｃは、各
ワイヤ４ａ〜４ｃでそれぞれ結ばれている。また図１０
の平面図に示すように、信号線用電極２ｂと信号線用内
部リード３ｂを結ぶワイヤ４ｂは、電源線用電極２ａと
電源線用内部リード３ａを結ぶワイヤ４ａと、グランド
線用電極２ｃとグランド線用内部リード３ｃを結ぶワイ
ヤ４ｃとの間に、挟まれた状態に配列されている。Generally, in a semiconductor device that processes a high-speed signal, it is known to be effective to dispose each signal line between a power line and a ground line in order to suppress an increase in impedance of the signal line. ing. FIG.
In the outer peripheral portion of the semiconductor element 1, the electrodes 2a to 2c are arranged in a row along the outer peripheral edge portion thereof. For each signal line electrode 2b, the power supply line electrode 2a and the ground line electrode 2c are provided. Is placed next to it. Further, the power supply line internal lead 3a and the signal line internal lead 3b are arranged so as to face the respective electrodes 2a to 2c.
And the internal leads 3c for ground lines are arranged. The electrodes 2a to 2c and the internal leads 3a to 3c are connected by the wires 4a to 4c, respectively. FIG.
As shown in the plan view of FIG. 3, the wire 4b connecting the signal line electrode 2b and the signal line internal lead 3b includes a wire 4a connecting the power line electrode 2a and the power line internal lead 3a, and a ground line electrode 2c. It is arranged so as to be sandwiched between the wire 4c and the ground wire inner lead 3c.

【０００４】[0004]

【発明が解決しようとする課題】以上のように、例えば
信号線用電極２ｂが１００個あるときは、それに対して
電源用電極２ａを１００個とグランド線用電極２ｃを１
００個を設けることになるが、この場合、従来の半導体
装置では、これらの各電極２ａ〜２ｃを半導体素子１の
外周部にその縁部に沿って１列に配列することになる。
そのため、電極数が増加するのに伴い、素子の寸法は増
大し、１枚のウエハ基板から生産できる素子数が低下し
てしまうという問題があった。As described above, for example, when there are 100 signal line electrodes 2b, 100 power supply electrodes 2a and 1 ground line electrode 2c are provided for the signal line electrodes 2b.
In this case, in the conventional semiconductor device, these electrodes 2a to 2c are arranged in the outer peripheral portion of the semiconductor element 1 in a line along the edge thereof.
Therefore, there has been a problem that as the number of electrodes increases, the size of the element increases, and the number of elements that can be produced from one wafer substrate decreases.

【０００５】この発明は、上記のような問題点を解決す
るためになされたもので、信号線用電極、電源線用電極
及びグランド線用電極の個数の増大による半導体素子の
寸法の増加を防ぐことができ、さらに、信号線用電極、
電源線用電極及びグランド線用電極の個数が増大しても
１枚のウエハ基板から生産できる半導体素子の数を低下
させることがない半導体装置を提供することを目的とす
る。The present invention has been made to solve the above problems, and prevents an increase in the size of a semiconductor element due to an increase in the number of signal line electrodes, power supply line electrodes and ground line electrodes. In addition, the electrode for the signal line,
An object of the present invention is to provide a semiconductor device in which the number of semiconductor elements that can be produced from one wafer substrate does not decrease even if the number of power line electrodes and ground line electrodes increases.

【０００６】[0006]

【課題を解決するための手段】この発明に係る半導体装
置は、半導体素子の外周に外周縁部に対して直交又はほ
ぼ直交する方向に配列された電源線用電極と信号線用電
極とグランド線用電極との３つの電極から成る一組の電
極が、半導体素子の外周に沿って複数組配置されてお
り、前記一組の電極の中の各電極に接続される各ワイヤ
は、半導体素子上面に対して互いに高さ位置が異なるよ
うに配置され、かつ前記信号線用電極からのワイヤは、
他の２つの電極からのワイヤの高さ位置の中間の高さ位
置に配置されている、ことを特徴としている。A semiconductor device according to the present invention includes a power supply line electrode, a signal line electrode, and a ground line arranged on the outer periphery of a semiconductor element in a direction orthogonal or substantially orthogonal to an outer peripheral edge portion. A plurality of sets of electrodes composed of three electrodes for the electrodes are arranged along the outer circumference of the semiconductor element, and each wire connected to each electrode of the one set of electrodes is the upper surface of the semiconductor element. Are arranged so that their height positions are different from each other, and the wire from the signal line electrode is,
It is characterized in that it is arranged at a height position intermediate between the height positions of the wires from the other two electrodes.

【０００７】また本発明による半導体装置では、前記一
組の電極の中の各電極、すなわち、電源線用電極、信号
線用電極及びグランド線用電極とそれぞれワイヤで接続
される電源線用内部リード、信号線用内部リード及びグ
ランド線用内部リードは、前記一組の電極の中の各電極
の配列方向とほぼ平行な方向に、配列されている、こと
を特徴としている。Further, in the semiconductor device according to the present invention, each of the electrodes in the set of electrodes, that is, the power line electrode, the signal line electrode, and the ground line electrode is connected to the power line internal lead by a wire. The signal line inner lead and the ground line inner lead are arranged in a direction substantially parallel to the arrangement direction of each electrode in the set of electrodes.

【０００８】[0008]

【作用】この発明に係る半導体装置では、電源線用電極
と信号線用電極とグランド線用電極との３つの電極から
成る一組の電極の中の各電極を半導体素子の外周に外周
縁部に対して直交又はほぼ直交する方向に配列するよう
にしているので、半導体素子の最外周部の電極数は従来
の半導体装置におけると比べて約３分の１となり、半導
体素子の寸法の増大を迎えることができる。また、信号
線用ワイヤの高さ位置を電源線用ワイヤとグランド線用
ワイヤの高さ位置の真ん中に配置して、信号線用ワイヤ
を電源線用ワイヤとグランド線用ワイヤとにより上下か
ら挟むように配置しているので、インピーダンスの増加
を抑えることができる。In the semiconductor device according to the present invention, each electrode in a set of three electrodes including a power line electrode, a signal line electrode, and a ground line electrode is provided on the outer periphery of the semiconductor element. The number of electrodes in the outermost peripheral portion of the semiconductor element is about one-third of that in the conventional semiconductor device, and the size of the semiconductor element is increased. You can meet. Further, the height position of the signal line wire is arranged at the center of the height position of the power line wire and the ground line wire, and the signal line wire is sandwiched between the power line wire and the ground wire line from above and below. Since they are arranged in this manner, the increase in impedance can be suppressed.

【０００９】また本発明による半導体装置では、前記一
組の電極の中の各電極とそれぞれワイヤで接続される電
源線用内部リード、信号線用内部リード及びグランド線
用内部リードを、前記一組の電極の中の各電極の配列方
向とほぼ平行な方向に配列するようにしたので、半導体
装置全体を小型化することができるようになる。Also, in the semiconductor device according to the present invention, the set of electrodes includes a power line internal lead, a signal line internal lead, and a ground line internal lead, which are connected to the electrodes by wires. Since the electrodes are arranged in a direction substantially parallel to the arrangement direction of the electrodes, the entire semiconductor device can be downsized.

【００１０】[0010]

【実施例】【Example】

実施例１．以下、この発明の一実施例を図について説明
する。図１は、本発明の実施例１による半導体装置とそ
のワイヤボンド方法を示す平面図、図２はその側面図、
図３はその斜視図、図４はその断面図である。図中、１
は半導体素子、２ａ〜２ｃは電極であり、２ａは電源線
用電極、２ｂは信号線用電極、２ｃはグランド線用電極
である。また３ａ〜３ｃは内部リードであり、３ａは電
源線用内部リード、３ｂは信号線用内部リード、３ｃは
グランド線用内部リードである。また４ａ〜４ｃは、各
電極２ａ〜２ｃと各内部リード３ａ〜３ｃをそれぞれ結
ぶワイヤで、４ａは電源線用ワイヤ、４ｂは信号線用ワ
イヤ、４ｃはグランド線用ワイヤである。また図３〜４
において、５はダイパッド、６はモールド樹脂である。Embodiment 1 FIG. An embodiment of the present invention will be described below with reference to the drawings. 1 is a plan view showing a semiconductor device and its wire bonding method according to a first embodiment of the present invention, and FIG. 2 is a side view thereof.
3 is a perspective view thereof, and FIG. 4 is a sectional view thereof. In the figure, 1
Are semiconductor elements, 2a to 2c are electrodes, 2a is a power line electrode, 2b is a signal line electrode, and 2c is a ground line electrode. Further, 3a to 3c are internal leads, 3a is an internal lead for a power supply line, 3b is an internal lead for a signal line, and 3c is an internal lead for a ground line. Further, 4a to 4c are wires connecting the respective electrodes 2a to 2c and the respective inner leads 3a to 3c, 4a is a power supply wire, 4b is a signal wire, and 4c is a ground wire. Also, FIGS.
In the above, 5 is a die pad, and 6 is a mold resin.

【００１１】この実施例１では、図１〜４に示すよう
に、電源線用電極２ａ、信号線用電極２ｂ、グランド線
用電極２ｃは、それぞれ１個ずつの計３個が一組の電極
として、半導体素子１の外周部に、その外周縁部に対し
てほぼ直交する方向（半導体素子の内部に向かってほぼ
縦方向）に配列されている。またこの場合、信号線電極
２ｂは、電源線用電極２ａとグランド線用電極２ｃとの
間に位置するように配列されている。また、内部リード
３は従来例（図１０）と同様に、半導体素子１の外側
に、半導体素子１の外周縁部とほぼ平行な方向に、電源
線用内部リード３ａ、信号線用内部リード３ｂ及びグラ
ンド線用内部リード３ｃの順に、配列されている。In the first embodiment, as shown in FIGS. 1 to 4, each of the power supply line electrode 2a, the signal line electrode 2b, and the ground line electrode 2c is a set of three electrodes, one electrode each. Are arranged on the outer peripheral portion of the semiconductor element 1 in a direction substantially orthogonal to the outer peripheral edge portion thereof (almost a vertical direction toward the inside of the semiconductor element). In this case, the signal line electrode 2b is arranged so as to be located between the power supply line electrode 2a and the ground line electrode 2c. Further, as in the conventional example (FIG. 10), the internal leads 3 are provided on the outside of the semiconductor element 1 in the direction substantially parallel to the outer peripheral edge portion of the semiconductor element 1 so that the internal leads 3a for power lines and the internal leads 3b for signal lines are provided. And the internal leads 3c for the ground line are arranged in this order.

【００１２】また実施例１では、図２に示すように、ワ
イヤ４ａ〜４ｃは互いにその高さ位置が互いに異なるよ
うに配置されている。すなわち、信号線用ワイヤ４ｂが
真ん中の高さに来るようにし、電源線用ワイヤ４ａがそ
の信号線用ワイヤ４ｂの上に来るように、またグランド
線用ワイヤ４ｃがその信号線用ワイヤ４ｂの下に来るよ
うに、配置されている。Further, in the first embodiment, as shown in FIG. 2, the wires 4a to 4c are arranged so that their height positions are different from each other. That is, the signal wire 4b is placed at the middle height, the power wire 4a is placed on the signal wire 4b, and the ground wire 4c is placed on the signal wire 4b. They are arranged so that they come down.

【００１３】以上のように、この実施例１では、各電極
２ａ〜２ｃの３個を一組の電極として、この一組の中の
３つの電極を、半導体素子１の外周縁部に対してほぼ直
交する方向に向けて、配列している。したがって、半導
体素子１の最外周部の電極数は従来に比べて約３分の１
となる。よって、同じ電極数でも、従来例に比べて半導
体素子の寸法を大幅に小型化させることができる。As described above, in the first embodiment, the three electrodes 2a to 2c are set as one set of electrodes, and the three electrodes in the set are set with respect to the outer peripheral edge portion of the semiconductor element 1. They are arranged in a direction substantially orthogonal to each other. Therefore, the number of electrodes at the outermost periphery of the semiconductor element 1 is about one-third that of the conventional one.
Becomes Therefore, even with the same number of electrodes, the size of the semiconductor element can be significantly reduced as compared with the conventional example.

【００１４】すなわち、図５（ａ）に示すように、従来
よりチップサイズを規定するのはチップ内部の回路の占
有面積だとされていた。しかし、ウエハプロセス技術が
進み配線が１層から２層、３層へと三次元的に形成され
るようになると、内部の回路の占有面積は余り増えなく
なる。すると、内部の回路の占有面積よりも、周辺の電
極の寸法や配列がチップ寸法（ｘ，ｙ）を決定する大き
な要因になってくる。よって、この実施例１のように、
各電極の配列を図５（ｂ）に示すように変えることによ
り、チップ寸法（ｘ’，Ｙ’）を小さくすることができ
る（なお、この場合、小さくなるのは、半導体チップ寸
法だけで、パッケージ寸法は従来と変わらない）。した
がって、ウエハ１枚から採れるチップ数（ウエハ１枚当
たりの理論チップ数）を増加させることができる。That is, as shown in FIG. 5A, conventionally, it has been said that it is the area occupied by the circuit inside the chip that defines the chip size. However, as the wafer process technology advances and the wiring is three-dimensionally formed from one layer to two layers, three layers, the occupied area of the internal circuit does not increase much. Then, the size and arrangement of the peripheral electrodes become a major factor in determining the chip size (x, y) rather than the area occupied by the internal circuit. Therefore, as in the first embodiment,
By changing the arrangement of each electrode as shown in FIG. 5B, the chip size (x ′, Y ′) can be reduced (in this case, only the semiconductor chip size is reduced. Package dimensions are the same as before). Therefore, the number of chips taken from one wafer (theoretical number of chips per wafer) can be increased.

【００１５】またこの実施例１では、各ワイヤ４ａ〜４
ｃの３つをそれぞれ一組として、その一組の中の各ワイ
ヤ４ａ〜４ｃは、互いに高さ位置が異なるように配置し
ている。そして、さらに、信号線用ワイヤ４ｂを、その
高さ位置が他の電源線用ワイヤ４ａとグランド線用ワイ
ヤ４ｃの高さ位置の中間に来るように、ワイヤボンドし
ているので、従来例に比べて信号線のインピーダンスの
増加を抑えることができる。Further, in the first embodiment, each of the wires 4a-4
The three wires c are set as one set, and the wires 4a to 4c in the set are arranged so that their height positions are different from each other. Further, since the signal wire 4b is wire-bonded so that the height position thereof is in the middle of the height positions of the other power wire 4a and the ground wire 4c, the conventional example is used. In comparison, it is possible to suppress an increase in the impedance of the signal line.

【００１６】実施例２．上記の実施例１では、信号線用
電極２ｂを中間にして、電源用電極２ａを半導体素子１
の内側に、グランド線用電極２ｃを半導体素子１の外周
側に配置しているが、実施例２では、この実施例１と逆
に、信号線用電極２ｂを中間にして、グランド線用電極
２ｃを半導体素子１の内側に、電源用電極２ａを半導体
素子１の外周側に配置している。この実施例２によって
も、実施例１と同様の作用効果が奏されることになる。Embodiment 2 FIG. In the above-described first embodiment, the power source electrode 2a is connected to the semiconductor element 1 with the signal line electrode 2b in the middle.
Although the ground line electrode 2c is disposed inside the semiconductor device 1 on the outer peripheral side of the semiconductor element 1, in the second embodiment, contrary to the first embodiment, the signal line electrode 2b is disposed in the middle, and the ground line electrode is formed. 2 c is arranged inside the semiconductor element 1, and the power supply electrode 2 a is arranged on the outer peripheral side of the semiconductor element 1. According to the second embodiment, the same operational effect as the first embodiment can be obtained.

【００１７】実施例３．次に、図６は、本発明の実施例
３を示す平面図、図７はその側面図、図８はその斜視
図、図９はその断面図である。これらの図中の符号は、
上記実施例１におけると同様である。この実施例３で
は、図６〜９に示すように、一組の電極の中の各電極２
ａ〜２ｃに対応する各内部リード３ａ〜３ｃも、この各
電極２ａ〜２ｃの配列とほぼ同じ方向に、半導体素子１
の内部に向かって縦方向に、配列されている。すなわ
ち、一組の電極の中の各電極２ａ〜２ｃにそれぞれ対応
する３つの内部リード３ａ〜３ｃの中、信号線用内部リ
ード３ｂは中央に配置され、それより半導体素子１に近
い方にグランド用内部リード３ｃが、またそれより半導
体素子１から離れた方に電源用内部リード３ａが配置さ
れている。また、前記の各電極２ａ〜２ｃと各内部リー
ド３ａ〜３ｃとを結ぶ各ワイヤ４ａ〜４ｃは、図７〜９
に示すように、信号線用ワイヤ４ｂを真ん中の高さにし
て、それより高い方に電源線用ワイヤ４ａが、またそれ
より低い方にグランド線用ワイヤ４ｃが配置されてい
る。なお、図８〜９において、７はモールド樹脂、８は
半田ボール、９は基板である。Embodiment 3 FIG. Next, FIG. 6 is a plan view showing a third embodiment of the present invention, FIG. 7 is a side view thereof, FIG. 8 is a perspective view thereof, and FIG. 9 is a sectional view thereof. The symbols in these figures are
This is the same as in the first embodiment. In this third embodiment, as shown in FIGS.
The internal leads 3a to 3c corresponding to a to 2c are also arranged in the same direction as the arrangement of the electrodes 2a to 2c in the semiconductor element 1
Are arranged in the vertical direction toward the inside. That is, among the three internal leads 3a to 3c corresponding to the respective electrodes 2a to 2c in the set of electrodes, the signal line internal lead 3b is arranged at the center, and the one closer to the semiconductor element 1 is grounded. The internal lead 3c for power supply and the internal lead 3a for power supply are arranged further away from the semiconductor element 1. Further, the wires 4a to 4c connecting the electrodes 2a to 2c and the internal leads 3a to 3c are respectively shown in FIGS.
As shown in FIG. 5, the signal wire 4b is set to the middle height, the power wire 4a is arranged higher than the signal wire 4b, and the ground wire 4c is arranged lower than the power wire 4a. 8 to 9, 7 is a mold resin, 8 is a solder ball, and 9 is a substrate.

【００１８】以上のように構成されているので、この実
施例３によれば、前記実施例１と同様の作用効果が奏さ
れることはもちろん、それに加えて、前記一組の電極の
中の各電極２ａ〜２ｃにそれぞれ対応する内部リード３
ａ〜３ｃを、前記各電極２ａ〜２ｃの配列方向とほぼ平
行な方向（半導体素子１の外周縁部とほぼ直交する方
向）に配列するようにしたので、半導体装置全体の寸法
を従来よりも大幅に小さくすることが可能になる。Since the third embodiment is constructed as described above, the same effects and advantages as those of the first embodiment can be obtained, and in addition to that, in addition to that, in the set of electrodes, Internal leads 3 corresponding to the respective electrodes 2a to 2c
Since a to 3c are arranged in a direction substantially parallel to the arrangement direction of the electrodes 2a to 2c (direction substantially orthogonal to the outer peripheral edge portion of the semiconductor element 1), the size of the entire semiconductor device is larger than that of the conventional one. It is possible to make it significantly smaller.

【００１９】[0019]

【発明の効果】この発明に係る半導体装置では、電源線
用電極と信号線用電極とグランド線用電極との３つの電
極から成る一組の電極の中の各電極を半導体素子の外周
に外周縁部に対して直交又はほぼ直交する方向に配列す
るようにしているので、半導体素子の最外周部の電極数
は従来の半導体装置におけると比べて約３分の１とな
り、半導体素子の寸法の増大を迎えることができる。ま
た、信号線用ワイヤの高さ位置を電源線用ワイヤとグラ
ンド線用ワイヤの高さ位置の真ん中に配置して、信号線
用ワイヤを電源線用ワイヤとグランド線用ワイヤとによ
り上下から挟むように配置しているので、インピーダン
スの増加を抑えることができる。In the semiconductor device according to the present invention, each electrode in a set of three electrodes, that is, a power line electrode, a signal line electrode, and a ground line electrode, is provided outside the semiconductor element. Since the electrodes are arranged in a direction orthogonal or almost orthogonal to the peripheral portion, the number of electrodes in the outermost peripheral portion of the semiconductor element is about one-third of that in the conventional semiconductor device, which is smaller than the size of the semiconductor element. Can reach an increase. Further, the height position of the signal line wire is arranged at the center of the height position of the power line wire and the ground line wire, and the signal line wire is sandwiched between the power line wire and the ground wire line from above and below. Since they are arranged in this manner, the increase in impedance can be suppressed.

【００２０】また本発明による半導体装置では、前記一
組の電極の中の各電極とそれぞれワイヤで接続される電
源線用内部リード、信号線用内部リード及びグランド線
用内部リードを、前記一組の電極の中の各電極の配列方
向とほぼ平行な方向に配列するようにしたので、半導体
装置全体を小型化することができるようになる。Further, in the semiconductor device according to the present invention, the set of electrodes includes a power line inner lead, a signal line inner lead, and a ground line inner lead which are respectively connected to the electrodes by wires. Since the electrodes are arranged in a direction substantially parallel to the arrangement direction of the electrodes, the entire semiconductor device can be downsized.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の実施例１による半導体装置を示す平
面図である。FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.

【図２】 実施例１による半導体装置を示す側面図であ
る。FIG. 2 is a side view showing the semiconductor device according to the first embodiment.

【図３】 実施例１による半導体装置を示す斜視図であ
る。FIG. 3 is a perspective view showing a semiconductor device according to a first embodiment.

【図４】 実施例１による半導体装置を示す断面図であ
る。FIG. 4 is a sectional view showing a semiconductor device according to a first embodiment.

【図５】 実施例１の作用効果を説明するための図であ
る。FIG. 5 is a diagram for explaining the function and effect of the first embodiment.

【図６】 本発明の実施例２による半導体装置を示す平
面図である。FIG. 6 is a plan view showing a semiconductor device according to a second embodiment of the present invention.

【図７】 実施例２による半導体装置を示す側面図であ
る。FIG. 7 is a side view showing a semiconductor device according to a second embodiment.

【図８】 実施例２による半導体装置を示す斜視図であ
る。FIG. 8 is a perspective view showing a semiconductor device according to a second embodiment.

【図９】 実施例２による半導体装置を示す断面図であ
る。FIG. 9 is a cross-sectional view showing a semiconductor device according to a second embodiment.

【図１０】 従来の半導体装置を示す平面図である。FIG. 10 is a plan view showing a conventional semiconductor device.

【図１１】 従来の半導体装置を示す側面図である。FIG. 11 is a side view showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

２ａ 電源線用電極．２ｂ 信号線用電極．２ｃ グラ
ンド線用電極．３ａ 電源線用内部リード． ３ｂ 信
号線用内部リード．３ｃ グランド線用内部リード．
４ａ 電源線用ワイヤ．４ｂ 信号線用ワイヤ． ４ｃ
グランド線用ワイヤ． ５ ダイパッド．６ モール
ド樹脂． ８ 半田ボール． ９ 基板2a Power line electrode. 2b Signal line electrode. 2c Ground wire electrode. 3a Internal lead for power line. 3b Internal lead for signal line. 3c Internal lead for ground wire.
4a Wire for power line. 4b Wire for signal line. 4c
Wire for ground wire. 5 Die pad. 6 Mold resin. 8 Solder balls. 9 substrates

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 半導体素子の外周に外周縁部に対して直
交又はほぼ直交する方向に配列された電源線用電極と信
号線用電極とグランド線用電極との３つの電極から成る
一組の電極が、半導体素子の外周に沿って複数組配置さ
れており、前記一組の電極の中の各電極に接続される各
ワイヤは、半導体素子上面に対して互いに高さ位置が異
なるように配置され、かつ前記信号線用電極からのワイ
ヤは、他の２つの電極からのワイヤの高さ位置の中間の
高さ位置に配置されている、半導体装置。1. A set of three electrodes, a power supply line electrode, a signal line electrode, and a ground line electrode, which are arranged on the outer periphery of a semiconductor element in a direction orthogonal or substantially orthogonal to the outer peripheral edge portion. A plurality of sets of electrodes are arranged along the outer periphery of the semiconductor element, and the wires connected to the electrodes in the set of electrodes are arranged so that their height positions are different from each other with respect to the upper surface of the semiconductor element. And the wire from the signal line electrode is arranged at a height position intermediate between the height positions of the wires from the other two electrodes. 【請求項２】 請求項１の半導体装置において、前記一
組の電極の中の各電極とそれぞれワイヤで接続される電
源線用内部リード、信号線用内部リード及びグランド線
用内部リードは、前記一組の電極の中の各電極の配列方
向とほぼ平行な方向に、配列されている、半導体装置。2. The semiconductor device according to claim 1, wherein the power line inner lead, the signal line inner lead, and the ground line inner lead, which are respectively connected to the electrodes in the set of electrodes by wires, A semiconductor device arranged in a direction substantially parallel to an arrangement direction of each electrode in a set of electrodes.
JP17343995A 1995-07-10 1995-07-10 Semiconductor device Pending JPH0927512A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17343995A JPH0927512A (en) 1995-07-10 1995-07-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17343995A JPH0927512A (en) 1995-07-10 1995-07-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0927512A true JPH0927512A (en) 1997-01-28

Family

ID=15960498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17343995A Pending JPH0927512A (en) 1995-07-10 1995-07-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0927512A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09115945A (en) * 1995-10-18 1997-05-02 Nec Corp Semiconductor device
JP2007501537A (en) * 2003-06-09 2007-01-25 フリースケール セミコンダクター インコーポレイテッド Semiconductor package with optimized wire bond positioning
EP1818984A2 (en) * 2001-09-28 2007-08-15 Freescale Semiconductors, Inc. Semiconductor chip with multiple rows of bond pads
JP2007535821A (en) * 2004-04-29 2007-12-06 キングスバリー，ジェフ Single row bonding pad configuration of integrated circuit chip
JP2010010492A (en) * 2008-06-27 2010-01-14 Sony Corp Semiconductor device and semiconductor integrated circuit
EP2220679A1 (en) * 2007-12-06 2010-08-25 Broadcom Corporation Embedded package security tamper mesh
WO2010105152A3 (en) * 2009-03-13 2011-10-27 Tessera, Inc. Microelectronic assembly wherein a wirebond is impedance controlled by using an additional wirebond connected to a reference potential
WO2010105157A3 (en) * 2009-03-13 2012-02-23 Tessera, Inc. Microelectronic assembly wherein a wirebond is impedance controlled by using a conductive layer connected to a reference potential
JP2012230986A (en) * 2011-04-26 2012-11-22 Renesas Electronics Corp Semiconductor device
US8581377B2 (en) 2010-09-16 2013-11-12 Tessera, Inc. TSOP with impedance control
US8853708B2 (en) 2010-09-16 2014-10-07 Tessera, Inc. Stacked multi-die packages with impedance control
US8981579B2 (en) 2010-09-16 2015-03-17 Tessera, Inc. Impedance controlled packages with metal sheet or 2-layer rdl
US9136197B2 (en) 2010-09-16 2015-09-15 Tessera, Inc. Impedence controlled packages with metal sheet or 2-layer RDL

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09115945A (en) * 1995-10-18 1997-05-02 Nec Corp Semiconductor device
EP1818984A2 (en) * 2001-09-28 2007-08-15 Freescale Semiconductors, Inc. Semiconductor chip with multiple rows of bond pads
EP1818984A3 (en) * 2001-09-28 2007-10-03 Freescale Semiconductors, Inc. Semiconductor chip with multiple rows of bond pads
JP2007501537A (en) * 2003-06-09 2007-01-25 フリースケール セミコンダクター インコーポレイテッド Semiconductor package with optimized wire bond positioning
JP2007535821A (en) * 2004-04-29 2007-12-06 キングスバリー，ジェフ Single row bonding pad configuration of integrated circuit chip
EP2220679A4 (en) * 2007-12-06 2014-02-26 Broadcom Corp Embedded package security tamper mesh
EP2220679A1 (en) * 2007-12-06 2010-08-25 Broadcom Corporation Embedded package security tamper mesh
US8890298B2 (en) 2007-12-06 2014-11-18 Broadcom Corporation Embedded package security tamper mesh
JP2010010492A (en) * 2008-06-27 2010-01-14 Sony Corp Semiconductor device and semiconductor integrated circuit
US8018035B2 (en) 2008-06-27 2011-09-13 Sony Corporation Semiconductor device and semiconductor integrated circuit
WO2010105152A3 (en) * 2009-03-13 2011-10-27 Tessera, Inc. Microelectronic assembly wherein a wirebond is impedance controlled by using an additional wirebond connected to a reference potential
US8269357B2 (en) 2009-03-13 2012-09-18 Tessera, Inc. Microelectronic assembly with impedance controlled wirebond and conductive reference element
US8575766B2 (en) 2009-03-13 2013-11-05 Tessera, Inc. Microelectronic assembly with impedance controlled wirebond and conductive reference element
WO2010105157A3 (en) * 2009-03-13 2012-02-23 Tessera, Inc. Microelectronic assembly wherein a wirebond is impedance controlled by using a conductive layer connected to a reference potential
US8253259B2 (en) 2009-03-13 2012-08-28 Tessera, Inc. Microelectronic assembly with impedance controlled wirebond and reference wirebond
US8994195B2 (en) 2009-03-13 2015-03-31 Tessera, Inc. Microelectronic assembly with impedance controlled wirebond and conductive reference element
US9030031B2 (en) 2009-03-13 2015-05-12 Tessera, Inc. Microelectronic assembly with impedance controlled wirebond and reference wirebond
US8581377B2 (en) 2010-09-16 2013-11-12 Tessera, Inc. TSOP with impedance control
US8802502B2 (en) 2010-09-16 2014-08-12 Tessera, Inc. TSOP with impedance control
US8853708B2 (en) 2010-09-16 2014-10-07 Tessera, Inc. Stacked multi-die packages with impedance control
US8981579B2 (en) 2010-09-16 2015-03-17 Tessera, Inc. Impedance controlled packages with metal sheet or 2-layer rdl
US9136197B2 (en) 2010-09-16 2015-09-15 Tessera, Inc. Impedence controlled packages with metal sheet or 2-layer RDL
JP2012230986A (en) * 2011-04-26 2012-11-22 Renesas Electronics Corp Semiconductor device

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