JPH09266557A - Video wall processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of cables for transmission and to reduce the degradation of picture quality at the time of extension by lowering a data rate by compressing the image data of digital video signals by using an encoder. SOLUTION: Memories 13a-13d respectively segment and output the digital video signals at positions corresponding to divided screens according to a control signal from a control unit 18, and DCT parts 14a-14d perform the 8×8 DCT of these digital video signals. IDCT parts 15a-15d perform IDCT by adding ineffective data, namely, '0' data showing that there are no coefficients in high frequency components or showing that the coefficients are cut off corresponding to the scale of extension. Besides, the memories 13a-13d, DCT parts 14a-14d and IDCT parts 15a-15d are controlled by the control signal from the control unit 18 and encoders 16a-16d perform the image data compression of MPEG2 to output signals from the IDCT parts 15a-15d.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvements in video wall processors.

[0002]

2. Description of the Related Art In recent years, in constructing a large screen, a system has been constructed in which a plurality of monitors are arranged to form one screen. Such a system is called a video wall system.

FIG. 6 is a diagram showing a state in which a screen of an image is doubled as an example of a conventional video wall system. As shown in FIG. 6, the screen 1 of the input video image is divided into four equal parts 1a to 1d, and the respective divided screens are enlarged vertically and horizontally to be doubled and arranged in four first to fourth monitors 2a to 2d. Project to. For example, an image on the screen 1 of a monitor image having a horizontal width l1 and a vertical width l2 becomes an image on a screen 2 of a video image in which two monitors of the same size are arranged vertically and horizontally, four in total.

FIG. 7 is a diagram for explaining a circuit configuration of a conventional video wall system. This video wall system comprises a monitor group 2 connected to a video wall processor 3. The monitor group 2 includes, for example, first to fourth monitors 2a to 2d, and cables 4a to 4 respectively.
The D / A units 8a to 8d in the video wall, which will be described later, are connected to the D / A units.

In this case, the bidet wall processor 3 is
Analog image signal 1 corresponding to screen 1 of the input video
An analog-to-digital converter (hereinafter referred to as A
/ D section) 5, the expansion section 6 to which the output signal is supplied
a to 6d, the interpolation unit 7 to which the output signals thereof are respectively supplied
a to 7d, and D / A sections 8a to 8d to which the output signals thereof are respectively supplied. The video signals output from the D / A units 8a to 8d are supplied to the first to fourth monitors 2a to 2d, respectively.

An analog video signal 1e is generated by the A / D section 5 in FIG.
Is converted into a digital video signal. By controlling the memories in the expansion units 6a to 6d by the control signals output from the control unit 9, the signals corresponding to the divided screens displayed on the first to fourth monitors 2a to 2d are digitally displayed. It is extracted from the video signal 1e. In order to enlarge the screen corresponding to the extracted signal, the interpolating unit 7a ...
Interpolation between pixels at the time of enlargement is performed at 7d.

FIG. 8 is a diagram for explaining an example of the interpolation method. As shown in FIG. 8A, the data of a pixel (hereinafter, referred to as a first pixel) at a certain point before enlarging the screen of the image by a factor of 2 is A, and the pixel next to the pixel is a pixel (hereinafter, referred to as a second pixel). (Note) data is B, and the pixel next to it is the third pixel. FIG.
As shown in (b), when the image is doubled, the position of the second pixel is shifted to the position of the third pixel relative to the position of the first pixel. Further, the data of (A + B) / 2, which is the average value of the data A and B, is inserted as the data of the new second pixel. Interpolation between pixels is performed in this way. The digital video signals are converted into analog video signals by the D / A units 8a to 8d, and each monitor 2 is converted into a video signal.
a to 2d, respectively.

[0008]

However, the above configuration has the following problems. Cables 4a to 4d for video signals between the video wall processor 3 and the monitor group 2 are required in the same number as the monitors 2a to 2d. Therefore, there is a problem that the number of cables increases. Further, there is a problem that image quality is deteriorated because linear interpolation is performed for pixel interpolation during enlargement. An object of the present invention is to provide a video wall processor that has a small number of signal output cables and has little deterioration in image quality during expansion.

[0009]

In order to solve the above problems and achieve the object, the following means were taken in the video wall processor of the present invention. According to the video wall processor of the present invention described in claim 1, a digital video signal corresponding to one screen is input, the one screen is divided into a plurality of divided screens, and a plurality of divided screens respectively corresponding to the divided screens are input. A plurality of video signal generation circuits for respectively generating the respective first digital video signals, and a plurality of second video signals for expanding the respective input first digital video signals.
A plurality of enlarging circuits for outputting as digital video signals, a plurality of encoders for compressing the input second digital video signals as image data, and a plurality of input image data compressed for each second digital video signals And a digital transmission circuit for forming and outputting at least one stream.

In the above video wall processor of the present invention, since the data rate of the digital video signal is reduced by the encoder, the transmission is facilitated and the number of cables for transmission is reduced.

According to a second aspect of the present invention, the expansion circuit includes:
A plurality of discrete cosine transform circuits which perform discrete cosine transform of the respective first digital video signals output from the inputted video signal generating circuit and output respective discrete cosine transform coefficients, and the respective discrete cosine transforms inputted At the same time as adding invalid data to the coefficient, inverse discrete cosine transform,
It is composed of a plurality of inverse discrete cosine transform circuits for generating a second digital video signal corresponding to a screen larger than each of the divided screens and supplying the second digital video signal to the encoder.

In the above video wall processor of the present invention, since invalid data is added to the first digital video signal and inverse discrete cosine transform is performed, it is easy to enlarge an image with little distortion.

According to a third aspect of the present invention, the digital transmission circuit inserts into the stream a signal indicating time management information for performing image data expansion or synchronous reproduction of the image data-compressed second digital video signals. It includes a circuit to do.

In the above video wall processor of the present invention, since the data rate of the digital video signal is lowered, it becomes easy to transmit, and the number of cables for transmission is reduced. In addition, it is easy to synchronize the video displayed on the monitor.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an embodiment of the present invention. The same parts as those in FIGS. 6 and 7 are designated by the same reference numerals.

It comprises a video wall processor 10 and a monitor group 11. They are, for example, one cable 12
Connected by First, the video wall processor 1
0 will be described. The analog video signal 1e is supplied to the memories 13a to 13d, which are video signal generation circuits, via the A / D unit 5 in the video wall processor 10. The output signals of the memories 13a to 13d are discrete cosine transform circuits (hereinafter referred to as DCT units) that are expansion circuits.
14a to 14d and an inverse discrete cosine transform circuit (hereinafter, ID
15a to 15d and the encoder 16
The signals a to 16d are sequentially supplied to the multiplexer 17, which is a digital transmission circuit. The multiplexer 17 outputs a data string (hereinafter referred to as a stream) to the cable 12 connected to the monitor group 11. The control signal from the control unit 18 is sent to the memory 13a.
˜13d, DCT units 14a to 14d, IDCT unit 15a
~ 15d respectively.

The first to fourth monitor sections 11 of the monitor group 11
a to 11d are demultiplexers 19a to 19d to which the cable 12 is connected, input buffers 20a to 20d, decoders 21a to 21d, output buffers 22a to 22d,
D / A 23a to 23d, and their output terminals and input terminals are connected in order. D / A 23a-2
The output signal of 3d is supplied to the first to fourth monitors 2a to 2d.

The operation of the video wall processor 10 will be described. The analog video signal 1e is converted into a digital video signal by the A / D section 5. Each of the memories 13a to 13d cuts out a digital video signal at a position corresponding to the divided screen according to a control signal from the control unit 18. For example, the divided screens 1a to 1 of the video in FIG.
As shown by d, four divisions are performed and a digital video signal corresponding to each divided screen is output. DCT units 14a to 14d
Performs 8 × 8 DCT of the digital video signal. I
The DCT units 15a to 15d add invalid data indicating that the high frequency component has no coefficient or the coefficient is truncated, that is, "0" data, according to the magnifying power, and IDCT is performed. Further, according to the control signal from the control unit 18, the memories 13a to 13d,
The DCT units 14a to 14d and the IDCT units 15a to 15d are controlled. Further, the encoders 16a to 16d have the I
MPE is applied to the output signals from the DCT units 15a to 15d.
G2 (Moving Picture Image C)
Image Experts Group 2) image data compression (hereinafter referred to as encoding) is performed.

Each data from the IDCT units 15a to 15d is sent to the multiplexer 17 for each group of pictures (hereinafter, referred to as GOP) by a packetized elementary stream packet (hereinafter, referred to as a variable length packet). It will be described as a PES packet). The PES packet constitutes a packetized elementary stream (hereinafter referred to as PES). Then, it is converted into a fixed-length transport packet of 188 bytes and is output to the cable 12 as a data string (hereinafter referred to as a stream).

FIG. 2 is a diagram for explaining an example of correspondence between an example of a video screen and data of its PES packet, and FIG. 3 is a diagram showing an example of the structure of these two types of packets. As shown in FIGS. 2A and 2B, for video data, for example, 1 GOP video data of the image on the screen 2a corresponds to the data 24b and 24c of the PES packet 24. Similarly, the video data of 1 GOP of each of the images of the other three screens 2b to 2d corresponds to the data of the three PES packets 25 to 27.

As shown in FIG. 3A, in the PES packet, control data for a control signal is added to the head of the PES packet. Next, a PES packet 24 of video data with a PES header, a PES packet of audio data with a PES header, and a PE of control data
S packet, PES packet 25 containing video data,
The stream is a PES packet including audio data, and so on.

As shown in FIGS. 2 (c) and 3 (b), these data are sequentially distributed to 188-byte packets including transport headers 28a to 28e to form transport packets. That is, the first transport packet 28A is the transport header 28
a, a PES header 24a, and a part 24b of the data of the PES packet. Second transport packet 2
8B includes a transport header 28b, a part 24c of the data of the PES packet, and a stuff code 29 added as needed.

Next, the transport header 28c and PE
Transport packet 2 consisting of PES packet of audio data with S header and stuff code 29
8C, a transport header 28d, a PES packet of control data, and a transport packet 28D including a stuff code 29 follow. Further, a part 25a, 25b of the PES packet 25 including the transport packet 28e and the video data corresponding to the video screen 1b.
And a transport packet 28E consisting of Hereinafter, similarly, the PES packets 26 and 27 including the video data corresponding to the video screens 1c and 1d are converted into transport packets to form a stream.

When the multiplexer 17 in FIG. 1 constructs a packet, the decoding time stamp (hereinafter D
A TS and a presentation time stamp (hereinafter referred to as PTS) are inserted in a predetermined part of the header of the PES packet. The DTS and PTS are signals indicating time management information for synchronously decoding and reproducing and outputting individual streams on the receiving side, as intended by the transmitting side. DTS is basically image data decompression of encoded data (hereinafter,
The data indicating the timing to start (decoding), and the PTS is data indicating the timing to output the decoded and displayable digital video signal. By at least one of DTS and PTS,
It is possible to display synchronized images. P of PES packet
The configurations of the TS and DTS will be described later together with the configuration of the PES packet.

The PTSs of the PES corresponding to the respective images of the split screens 2a to 2d in FIG. 2 have the same data so that these four images are displayed simultaneously. The DTS is determined according to the time required for decoding so that the PTS of the same data can be simultaneously displayed. That is, at the time of decoding, data is sent from the input buffer to the decoders 21a to 21d at the timing instructed by the DTS to be decoded, and is sent from the output buffers 22a to 22d to the D / A 23a to 23d at the timing instructed by the PTS. .
Eventually, the respective images are simultaneously displayed on the screens 2a to 2d.

Next, the operation of the monitor group 11 in FIG. 1 will be described. For example, each of the demultiplexers 19a to 19d of each of the monitor units 11a to 11d has a screen 2 shown in FIG.
The transport packets corresponding to a to 2d are demultiplexed, that is, selected. Further, the PES packet is restored from the selected transport packet.
Further, the video data of each screen 2a to 2d in FIG. 2 is restored and supplied to each of the decoders 21a to 21d, and the data of DTS and PTS, which will be described later, is restored, and each input buffer 20a to 20d and each output. It supplies necessary timing signals to the buffers 22a to 22d. Each input buffer 20a
˜20d are the demultiplexers 19a to 19d, respectively.
The data from d is temporarily stored, and the video data in the respective stored data is supplied to the decoders 21a to 21d at a timing according to the data of the DTS. The video data from each of the input buffers 20a to 20d is decoded by the decoders 21a to 21d according to MPEG2,
It becomes a digital video signal. Each decoder 21a-21d
The digital video signals from the output buffer 22
a to 22d are temporarily stored, and the stored digital video signals are converted into analog video signals by the D / A units 23a to 23d at timings corresponding to the PTS data. Monitor 2 for each analog video signal
It is supplied to a-2d and displayed simultaneously.

Next, the interpolation method will be described. FIG. 4 is a diagram illustrating an interpolation method. As shown in FIGS. 4 (a) and 4 (b), a digital video signal 3 of 8 × 8 pixels is used at the time of doubling.
64 pieces of data 31 after applying 8 × 8 DCT to 0, and 192 pieces of “0” data 32 in the high frequency component
Is added to make a total of 256 data. 1 of that data
A 6 × 16 IDCT is performed. In this way, 8x
The video data of 8 is a 16 × 16 digital video signal 3
Expanded to 3. That is, non-linear pixel interpolation is performed. In the case of 1 time for comparison, as shown in FIG. 4A, 8 times corresponding to the digital video signal 30 of 8 × 8 pixels is used.
8 × 8 IDCT is performed on the coefficient 31 of the × 8 DCT to obtain 8
The x8 digital video signal 30a is obtained.

FIG. 5 is a diagram for explaining the data structure of a PES packet forming the PES of an example of the program stream in the case of MPEG2. For example, a PES packet always includes a PES header, video data,
It has audio data, control data, and the like. P
The ES header is, for example, a packet start code prefix (Packetstart Co
de Prefix), Stream ID for identification (Stream ID
), A PES packet length (PES Packet)
Length), PES Header Flags indicating the presence or absence of other information, and P indicating the length of other information.
ES header length (PES Header Length), and PES header fields (PES Head Length) indicating the length of other information
er Fiels), PES which is the data of the further information
It has a packet data block (PES Packet Data Block). PES Header Flags
Is a PES that indicates whether or not scrambled
Scrambling control (PES scrambling control,
SC), PES priority indicating priority (PES pr
iority, PR), a data alignment indicator (DA) indicating the order of valid data such as video data between PES packets, a copyright (copyright, CR) of a flag related to copying, and original data. PTS DTS flag (PTS DT) indicating the presence or absence of at least one of original or copy, PTS and DTS
S flags, PD), elementary stream clock reference flags (ESCR Flags, ESCR), elementary stream late flags (ES rate flag,
ES), digital storage media trick mode flag (DSM Tr
ick mode flag TM), an additional copy info flag (AC), and a PESCRC flag (PES CRC fla) indicating the presence or absence of an error code.
g, CRC), and other PES extension flags (PES extention flags, EXT) indicating the presence or absence of information. The PES header field is, for example, PTS /
DTS, DSM Trick Mode Field, which is data related to special playback, and Additional Copy Info field (Additional Copy In).
foField), PES extension flag (PES Ext
ention Flags), Stuffing By (Stuffing By
tes).

PTS and DTS are each "001".
Following "0" and "0011", the data 34a of the 32nd to 30th bits, the marker bit, and the 29th bit of
15th bit data 34b, marker bit, 14th bit
Bits to first bit data 34c and marker bits. Further, there may be a PTS and DTS flag including more detailed data than the PTS / DTS 34.
The PTS and DTS flags are 36 after "0011".
PTS field 34d, which is bit data, "00"
"01" is followed by a DTS field 34e which is 36-bit data.

In the PTS, the display timing is instructed by using the 90 kHz reference clock. Also,
The DTS data in the PES header is determined so as not to cause data overflow or underflow during decoding. The DTS uses a 90 kHz reference clock to instruct when to start decoding. That is,
Using this MPEG2 transport packet, it is possible to multiplex the video signals output from the video wall processor to multiple monitors, and output the image reproduction on the monitors in synchronization with all monitors. Becomes

The DSM trick mode field is, for example, fast forward indicating fast forward.
), Slow Motion (Slow Motion)
), Phrase frame (Freeze Frame) indicating stop,
The four states of Fast Reverse indicating rewind are shown. In case of first forward,
000 ”is the trick mode control (trick mo
de control) data, followed by field ID (fiel
d id), Intra slice refresh (intraslice r
efesh), Frequent seat translation (frequency
truncation). For slow motion,
After the data of the trick mode control which is "001", the field rep control (field rep co
ntrol). In case of freeze frame, "01
It has a field ID following the trick mode control data of 0 ". In the case of the first reverse, the trick mode control data of" 111 "is followed by a field ID, intra slice refresh, and free. Has a frequency truncation.
The ES extension flag includes, for example, a PES private data flag and a pack header field fl.
ag), program packet sequence counter flag (program packet sequence counter flag), STD buffer flag (STD Buffer Flag), PES extension field flag (PES extention field fl)
ag). The extension data field is
It has a marker bit and a PES Extension Field Length.

In the above embodiment, the encoder reduces the data rate of the digital video signal, which facilitates transmission and reduces the number of cables for transmission. Since "0" data is added to the DCT coefficient and IDCT is performed, it is easy to enlarge an image with little distortion. Further, since the DTS and PTS are used, it is easy to synchronize the display monitor and the like.

[0033]

As described above, according to the present invention, it is possible to provide a video wall processor in which the number of cables for signal output is small and the deterioration of image quality during expansion is small.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a video wall processor according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a video wall processor according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a video wall processor according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a video wall processor according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a video wall processor according to an embodiment of the present invention.

FIG. 6 illustrates a video wall processor according to the present invention and a conventional example.

FIG. 7 is a diagram illustrating an example of a conventional video wall processor.

FIG. 8 illustrates an example of a conventional video wall processor.

[Description of Codes] 1, 2a to 2d ... Monitor (screen), 1a to 1d ... Split screen, 1e ... Analog video signal, 2, 11 ... Monitor group, 4a-4d, 12 ... Cable, 5 ... A / D section 3, 10 ... Video wall processor, 11a to 11d ... Monitor unit, 13a to 13d ... Memory, 14a to 14d ... DCT unit, 15a to 15d ... IDCT unit, 16a to 16d ... Encoder, 17 ... Multiplexer, 19a to 19d ... Demultiplexer, 20a to 20d ... Input buffer, 21a to 21d ... Decoder, 22a to 22d ... Output buffer, 23a to 23d ... D / A section, 30, 30a ... Digital video signal of 8 × 8 pixels, 31 ... 8 × 8 32 ... "0" data, 33 ... 16x16 digital video signal, 34 ... PTS and DTS at least On the other hand, 34a~34e ... PTS or,, DTS bit data.

Claims (3)

[Claims] 1. A digital video signal corresponding to one screen is input, the one screen is divided into a plurality of divided screens, and a plurality of first digital video signals respectively corresponding to the respective divided screens are respectively obtained. A plurality of video signal generating circuits for generating, a plurality of magnifying circuits for magnifying each of the input first digital video signals and outputting as a plurality of second digital video signals, and each of the second input A plurality of encoders for compressing image data of the digital video signal, and a digital transmission circuit configured to output the second digital video signals of the input image data compressed into at least one stream. Characteristic video wall processor. 2. The plurality of discrete cosine transform circuits, wherein the enlargement circuit discrete cosine transforms the respective first digital video signals output from the input video signal generating circuit and outputs respective discrete cosine transform coefficients. And at the same time adding invalid data to each of the input discrete cosine transform coefficients and performing inverse discrete cosine transform to generate a second digital video signal corresponding to a screen larger than each of the divided screens. The video wall processor according to claim 1, comprising a plurality of inverse discrete cosine transform circuits supplied to the. 3. The digital transmission circuit includes a circuit for inserting into the stream a signal indicating time management information for performing image data expansion or synchronous reproduction of the image data compressed second digital video signals. A video wall processor according to claim 1 or claim 2 characterized in that.