JPH09260647A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a step, which is used as a mark for alignment use in a lithography process. SOLUTION: A semiconductor device is one formed into a structure, wherein an element formation region surrounded with an element isolation region 22 is formed on the surface of a semiconductor substrate 21 and at the same time, a gate oxide film 23 is formed on the surface of the substrate 21, a gate electrode 25 is formed on the film 23, a silicon nitride film 27 is formed on the region 22, which is a matching mark region, and moreover, an insulating film 28 is deposited on the film 27. A gate electrode lead-out part 251 of the element formation region is formed in this film 28, contact holes 291 to 293 are formed in the film 28, in such a way as to correspond to diffused layers 241 and 242 and at the same time, contact holes 301, 302,... are formed in the part of the film 27. A W-film is deposited to embed the W-film in the holes 291 to 293, and the holes 291 and 293 are formed into contact metal holes 321 to 323, but as the W-film is not grown on the film 27, the holes 301, 302,... are left as they are and a step suitable for detecting a mark is left.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufactured based on a lithography process using a reduction projection exposure apparatus, and particularly used as a miniaturized large-scale MOS semiconductor circuit, and a manufacturing method thereof.

[0002]

2. Description of the Related Art When manufacturing a semiconductor device or a semiconductor integrated circuit, basically, a film deposition process by oxidation, deposition, sputtering, etc. on a semiconductor substrate such as silicon, and a necessary portion of the deposited film are carried out. Repetition is performed with the pattern formation for removing the other portions remaining.

As is generally known, a photolithography method (photolithography method: hereinafter simply referred to as lithography) is used for forming such a pattern in the present manufacturing process of semiconductor elements. In the lithography method used for forming this pattern, a glass mask called a reticle is used in which a pattern to be actually formed is magnified about 5 times, for example, and is formed of chrome. That is, a pattern image obtained by passing ultraviolet rays through this glass mask is reduced using a lens mechanism, a pattern image is formed on a semiconductor substrate, and a photosensitive material (resist) applied on the semiconductor substrate is exposed.
A resist mask pattern is formed by developing this. That is, the deposited film deposited and formed on the semiconductor substrate is processed by using this resist mask pattern as a mask material and processed into a fine pattern shape.

Therefore, a plurality of identical patterns can be easily formed on the semiconductor substrate (wafer) by using a means for forming such a mask pattern and etching the deposited film on the semiconductor substrate. Such a technique enables mass production of semiconductor devices and semiconductor integrated circuits.

Such a lithographic process is one of the most important processes in the manufacturing process of a semiconductor device, and an active element such as a transistor and a passive element such as a resistor and a capacitor are formed on a semiconductor substrate to form one element. In order to form a semiconductor circuit device, it is repeated a plurality of times to a few tens of times to form an impurity diffusion layer, a gate electrode, and a wiring pattern.

In each of these processes, it is necessary to match the positional relationship between the pattern formed in each of the processes and the pattern formed in the lower layer, and on the reticle, alignment is performed in the subsequent lithography process. A pattern for forming a specific pattern (alignment mark) to be used is prepared. The alignment mark is designed so that a step pattern conforming to the specifications of the stepper is formed in the lower layer pattern forming process.

In the actual lithography process using this alignment mark, the alignment mark is irradiated with visible light or laser light, and the difference in the intensity of the reflected light due to the step difference,
Alternatively, the position of the alignment mark is detected by detecting the interference light generated thereby.

FIG. 6A illustrates an example of a conventional and commonly used alignment mark, for example, a MOS.
In the integrated circuit, the LOCOS is formed on the surface of the semiconductor substrate 11.
An element formation region is set so as to be surrounded by an element isolation region 12 formed by oxidation or the like, an impurity diffusion layer is formed in this element formation region, and an insulating layer 13 is deposited thereon. Then, a plurality of contact holes for connecting to the underlying impurity diffusion layer and the gate electrode portion are formed in the insulating layer 13, and openings 141, 142, ... For alignment are formed. The openings 141, 142, ... Are formed in, for example, a rectangular shape or a square shape, and are regularly arranged as shown in FIG. 7B. The respective areas of the openings 141, 142 ,. It is lower than the other parts, and a step is formed.

A first wiring layer, for example, is formed on the surface of the insulating layer 13 in which the contact holes are opened. As shown in FIG. 6C, the surface of the insulating layer 13 is made of aluminum or the like. A metal film 15 for one wiring layer is deposited. At the time of lithography, a mask having a predetermined pattern is aligned after such a metal film 15 is deposited, but even after the metal film 15 is formed, steps are formed corresponding to the openings 141, 142 ,. Since it remains, it is possible to detect the position by reflected light, and this is used for mask alignment.

On the other hand, with the miniaturization of semiconductor elements, the size of the contact hole formed in the insulating layer 13 is also reduced. However, the impurity diffusion layer, the gate electrode and the wiring metal film
The thickness of the interlayer insulating layer (insulating layer 13) that is set between the insulating layer 15 and the insulating layer 15 is to reduce the parasitic capacitance required for circuit performance, and to reduce the parasitic capacitance required for circuit electrodes, such as a gate electrode formed below the metal film 15. Due to the film thickness, it cannot be made thinner than the size is reduced by miniaturization.

From these results, the contact hole (opening 14
Aspect ratio (ratio of size to depth) of 1, 142, ...)
Becomes larger as miniaturization progresses, and the metal film 15 cannot be sufficiently deposited in the contact hole by the sputtering method that has been conventionally used for depositing the metal film 15. Therefore,
As shown in FIG. 7, a disconnection portion 16 is generated in the contact hole to cause a connection failure. This is because the sputtering method causes metal atoms to fly from the upper part of the contact hole and deposits the metal film 15 in the contact hole.

Further, in the manufacturing stage, it is not impossible to sputter so that the disconnection portion 16 which causes such a connection failure is not formed, but even in such a case, the contact side surface near the bottom surface of the contact hole is formed. When the thickness of the metal film 15 on the insulating layer 13 is 100%, the metal film sputtered on the portion is about 5% or less. Therefore, in a state where this semiconductor device is put into practical use, the density of the current flowing through the side surface portion near the bottom surface of the contact hole becomes excessive, which may eventually lead to disconnection.

In order to deal with such a problem, a special contact hole filling technique has been developed. After the contact hole is opened, a metal film such as tungsten (W) is formed by a vapor deposition method (CVD method). Grow, FIG. 8 (A)
As shown by, the opening 141 is formed by using the metal film 15 as a contact hole.
, 142, ... Can be the buried metal 151 uniformly deposited in the inside.

The contact hole filling technique is as follows:
First, T on the bottom and side surfaces of the contact hole, and on the insulating film 13.
A blanket for forming a refractory metal film such as i and growing a metal film such as tungsten on the entire surface of the metal film.
t) method is known. Secondly, a selective method is known in which a metal film such as tungsten is selectively grown only from the bottom of the contact hole.

In the blanket method, a metal film for filling is literally grown in addition to the contact hole, and it is necessary to remove the surplus metal on the insulating film 13 after forming this metal film. Further, in the selective method, the metal film is basically grown only in the contact hole, but in the actual semiconductor device structure as shown in FIG. The hole 145 and the contact hole 146 on the gate electrode 18 have different depths. Therefore, if the deep contact hole 145 is completely filled, the buried metal overflows on the insulating film 13 and the surplus metal film 19 is formed on the shallow contact hole 146. In this state, adjacent contact holes,
This causes a short circuit between wiring layers formed thereafter. Therefore, it is necessary to remove the surplus metal film 19 on the insulating film 13 even in the selective method.

As a technique for removing the surplus metal on the insulating film, after coating the entire surface of the substrate with a resist, the resist and the metal used for filling (tungsten etc.) have almost the same etching rate, that is, both etching. Anisotropic etching (Reactive Ion Etch) with a selectivity close to “1”
ching: RIE) or isotropic etching (Chemical
The first known method is to perform Dry Etching (CDE). Further, there is known a chemical mechanical polishing (CMP) method in which polishing is performed while flowing an abrasive material that causes a chemical reaction with at least the surplus metal film to remove only the surplus metal or both the surplus metal and the insulating film. Has been.

If these means for removing excess metal are used,
Excessive metal on the insulating film 13 which is an interlayer insulating layer can be removed to the extent that a short circuit problem does not occur, and by using these excess metal removing techniques together with the contact hole filling film forming technique. As shown in FIG. 8A, the step difference between the metal film 151 embedded in the contact hole and the insulating film 13 can be 100 nm or less.

In this way, if the metal is evenly buried in the contact hole and the step between the buried metal and the insulating film is 100 nm or less, disconnection failure occurs even in the miniaturized semiconductor device at the contact portion. Can be greatly improved. However, when adopting such a structure, there arises a problem in alignment in the lithography process.

That is, in the alignment in the current lithography process, a method of detecting the position by utilizing the step of the opening is adopted. Therefore, in order to obtain the reflected light intensity or the interference light capable of performing the position detection for this alignment, a step of at least 50 to 100 nm is required without another film on the step, and When another film is placed on the step, a larger step is required. Therefore, the step of the alignment mark becomes 100 nm or less, and 40
In the metal wiring processing step in which the lithography step is performed with the metal layer for metal wiring having a thickness of 0 to 1000 nm deposited, the alignment mark formed in the contact hole opening step cannot be detected.

[0020]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and in the case where a metal embedding technique is used for a contact hole formed together with an opening serving as an alignment mark. Also in the above, it is an object of the present invention to provide a semiconductor device and a manufacturing method thereof in which an alignment mark which can be effectively used for alignment is formed in a subsequent lithography process.

[0021]

In a semiconductor device according to the present invention, for example, a MOS formed on a semiconductor substrate is used.
A metal film formed by a selective gas layer growth method is embedded in the contact hole connecting the impurity diffusion layer of the semiconductor device and each of the gate electrodes and the metal wiring layer,
The bottom of another contact hole formed on the same semiconductor substrate at the same time as the contact hole, which forms a pattern for detecting a step and performing alignment in the lithography process, or from the bottom of this contact hole to its side surface. In part, the buried metal is exposed to the ungrown material.

As described above, when the material in which the embedded metal is not grown is exposed from the bottom of the contact hole used for alignment in the lithography process to a part of its side surface, the metal is not formed in the contact hole. When the film is grown to be buried, a predetermined metal is buried in the contact hole corresponding to the impurity diffusion layer and the gate electrode portion to form a contact, but the material in which the buried metal is not grown is exposed. The buried metal does not grow in the contact hole, and the state of the opening remains. Therefore, when pattern matching is performed using reflected light or interference light in the lithography process, a step due to the contact hole for alignment is clearly detected, and fine semiconductor elements can be effectively processed.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1A shows a cross-sectional structure of an example applied to a MOS semiconductor circuit, in which a buried element isolation (Shallow T
The element formation region is set so as to be surrounded by the element isolation region 22 having a rench isolation (STI) structure. Then, a gate insulating film 23 made of an oxide film is formed on the surface of the semiconductor substrate 21.

Impurity diffusion layers 241 and 242 corresponding to a source and a drain are formed in the element forming region, and a gate electrode formed of polycrystalline silicon is located between the impurity diffusion layers 241 and 242.
25 is formed, and the gate electrode 25 is formed on the element isolation layer 22.
The gate electrode lead-out portion 251 is formed so as to extend to that portion. In this case, the refractory metal silicide (TiSi _{2 in} this example) layer 2 is formed on the surfaces of the gate electrode 25, the gate electrode lead-out portion 251, and the impurity diffusion layers 214 and 242, respectively.
6,261 and 311 and 312 are attached and salicide (Se
lf-aligne Silicide: Salicide) structure.

This semiconductor device can be divided into three regions A, B and C with the element forming region sandwiched therebetween.
Is an alignment mark area, area B is an active element (MOS type semiconductor element) area, and area C is an element isolation area.
In the alignment mark region A, a silicon nitride film (SiN film) 27 is formed on the surface of the element isolation layer 22, and an insulating film serving as an interlayer insulating layer corresponding to the entire surface of the semiconductor substrate 21. 28 are deposited.

For the insulating film 28, impurity diffusion layers 241 and 242 corresponding to the source and the drain, respectively.
, And contact holes 291 to 293 are formed corresponding to the gate electrode lead-out portion 251, respectively. At the same time as the step of forming the contact holes 291 to 293, the lithography is performed corresponding to the position of the silicon nitride film 27. The contact holes 301, 302, ... Used for alignment used in the process are formed to have a pattern as shown in FIG. Here, the contact holes 291 and 292 are formed in the diffusion layer 24.
TiSi ₂ formed corresponding to 1 and 242 respectively
Until the terminal layers 311 and 312 consisting of
Further, the contact hole 293 is formed until the refractory metal silicide layer 261 is exposed, and the contact holes 301, 302, ... Are opened until the silicon nitride film 27 is exposed.

In this way, the contact holes 291 to 293 and 30
.. are formed in the contact holes 321 to 293 by the growth of a metal such as W (tungsten) by the selective method.
Embed 3. In this case, the silicon nitride film 27 has W
Contact holes 291-29 as they are not grown.
W is grown only on 3 to grow contact metals 321 to 323, and the contact holes 301, 302, ... Are left as open holes and can be used as alignment marks.
Here, the contact holes 291 to 293 are generated by the growth of W.
Excessive metal overflows on the opening surface of, but this excess metal is appropriately removed.

Therefore, the contact holes 301, 302, ... For the alignment marks are formed along with the contact holes 291-293, and at the same time, the contact holes 301 intended to be used as the alignment marks even if the W growing step is carried out. , 302
, ..., the level difference due to the opening is clearly left, and the position can be sufficiently detected in the subsequent lithography process. Here, the film thickness of the insulating film 28 to be the interlayer insulating film is
Since the thickness is about 500 to 1500 nm, steps corresponding to this thickness are formed in the contact holes 301, 302 ,. Since the step difference for the lithography process may be at least 150 nm or more, this contact hole
301, 302, ... Can be effectively used as alignment marks.

Here, the silicon nitride film 27 is composed of the gate electrode 25 and the gate lead-out portion 251 which constitute the MOS transistor.
Since it can be shared with the side wall insulating layer 33, it is not necessary to add a new step of depositing a silicon nitride film only for remaining the alignment mark.

FIG. 2 sequentially shows a manufacturing process of such a semiconductor device. First, as shown in FIG. 2A, a semiconductor substrate 21 is subjected to an element isolation region by a conventionally known STI process. 22 is formed, and the element formation region is set so as to be surrounded by the region 22. After that, an impurity for controlling a threshold value or the like is introduced into this element forming region.

Then, a gate oxide film 23 is formed on the entire surface of the semiconductor substrate 21 by thermal oxidation, polycrystalline silicon into which impurities are appropriately introduced is deposited, and a protective oxide film 35 and a protective oxide film 35 at the time of processing the gate electrode are deposited thereon. After depositing 351
The gate electrode 25 and the gate lead-out electrode 251 are formed by selective etching, and if necessary, impurity introduction regions 361 and 362 are formed by introducing impurities into the impurity diffusion region forming portions corresponding to the source and drain forming portions. Then, a silicon nitride film 37 is deposited on the entire surface of the semiconductor substrate 21 to a film thickness of 50 to 200 nm. Note that the impurity may be introduced into the polycrystalline silicon at the same time as or after the polycrystalline silicon is deposited.

Next, as shown in FIG. 6B, the silicon nitride film 27 in the portion corresponding to the alignment mark area A is left, and the gate electrode 25 and the gate electrode lead-out portion are formed.
A resist pattern is formed so that the sidewall insulating layer 33 is left on the sidewall of 251 and the silicon nitride film 37 is etched. The remaining silicon nitride film 27 prevents the growth of W during the filling of the contact hole described later, and at the same time, the sidewall insulating layer 33 is formed on the sidewalls of the gate electrode 25 and the gate electrode lead-out portion 251 by this etching. It is formed.

Subsequently, as shown in FIG. 6C, impurities are again introduced into the impurity diffusion layer region forming portion as needed, and the impurity diffusion layers 241 corresponding to the source and the drain are formed.
And 242 are formed, and the oxide film 231 on the gate electrode 25, the gate electrode lead-out portion 251, and the impurity diffusion layers 241, 242 is removed by a conventionally known method. Further, the protective oxide films 35 and 351 on the gate electrode 25 and the gate electrode lead-out portion 251 are removed.

After that, a Ti / TiN film, which is a refractory metal, is sputtered, and TiSi ₂ conversion annealing is performed to obtain T
The iSi ₂ layers 26 and 261 are formed only on the gate electrode 25 and the gate electrode lead-out portion 251, and the impurity diffusion layers 241 and 242 to form a salicide structure.

At this time, since TiSi ₂ reaction does not occur on the element isolation region 22 and the silicon nitride film 27, an unreacted Ti / TiN film remains in this portion. This unreacted Ti / TiN film is removed by a mixed solution of, for example, sulfuric acid and hydrogen peroxide solution so that TiSi ₂ is not etched, and has a salicide structure.

Next, an insulating film 28 for forming an interlayer insulating layer is formed by depositing a CVD oxide film, boron / phosphorus glass, etc., and the contact holes 291 to 293 are formed by RIE using a lithography method. 301, 302
, ... are opened. In the RIE used for opening the contact hole, the etching selection ratio between the oxide film and the silicon nitride film is sufficiently large so that the remaining silicon nitride film 27 in the alignment mark area A is sufficiently left. It must be done under the set conditions.

After that, when a W film is formed by the selective CVD method, W grows on TiSi ₂ but does not grow on the silicon nitride film 27, so that the contact hole is formed.
The contact metals 321 to 323 are buried and formed only in the 291 to 293. Then, the semiconductor device as shown in FIG. 1 is completed by the CMP process of removing the surplus metal overflowing from the openings of the contact holes 291 to 293 together with the surface of the insulating film 28.

In the embodiment shown here, the removal of the excess metal and the flattening of the surface of the insulating film 28 are explained by one CMP process, but after the insulating film 28 is deposited, The surface is flattened by CMP and then RI
Contact holes 291 to 293 and 301, 302 using E,
.., W film formation, etching using a resist etch-back technique, or removal of excess metal by CMP may be performed.

Further, in this embodiment, the STI structure is used for forming the element isolation region 22, but it is also possible to use the element isolation structure by the selective oxidation (LOCOS) method. Further, a polycide structure composed of WSi ₂ and polycrystalline silicon may be used for the gate electrode, and TiSi ₂ may be attached only to the impurity diffusion region. Salicide structure or impurity diffusion layer Ti
When the Si ₂ attachment structure is not used, the Ti / TiN film is sputtered after the contact hole is opened, silicidation annealing is performed, and the interlayer insulating film / mark portion contact bottom (Si
It is also possible to adopt a manufacturing method in which the unreacted Ti / TiN film on the side wall of the contact hole is removed to form TiSi ₂ only on the bottom of the contact hole corresponding to the impurity diffusion region. .

FIG. 3 is a sectional view for explaining the second embodiment, in which the polycrystalline silicon film 40 and the tungsten silicide (WSi) are formed on the element isolation region 22 in the alignment mark forming region A.
₂ ) Gate electrode 42 of WSi polycide structure with layer 41 overlaid
The silicon nitride film 43 is laminated on the gate electrode 42. In this case, silicon nitride films 44 and 441 are laminated on the tungsten silicide layer 41 on the gate electrode 25 and the gate electrode lead-out portion 251, respectively.

Then, as in the previous embodiment, the contact holes 291 to 29 are formed after forming the insulating film 28 serving as an interlayer insulating layer.
3 and 301, 302, ... In this case, the contact hole 293 corresponding to the gate electrode lead-out portion 251 is opened until it penetrates the silicon nitride film 441 and reaches TiSi ₂ . Therefore, the contact holes 301, 302, ...
While the silicon nitride film 43 is exposed at the bottom of the contact holes 291 to 293 in the regions B and C, the W film is exposed.

Therefore, W is not grown in the contact holes 301, 302, ... In the alignment mark forming area A by the film formation of W, but W is grown in the bottoms of the contact holes 291-293, and the contact holes 291-293 are formed. Contact metal 321
~ 323 is embedded.

With this structure, the contact holes 301, 302, etc. for position alignment having a depth corresponding to the film thickness of the insulating film 28 are formed as in the previous embodiment. It is possible to sufficiently detect the position for alignment in the lithography process.

In this embodiment, the contactless holes 291 and 292 on the impurity diffusion layer are opened in a self-aligned manner with respect to the gate electrode and the element isolation region. aligned Contac
Since the t) structure is used, not only the bottom portion of the contact holes 301, 302, ... In the mark formation region A but also a part of the side surface portion of the silicon nitride film 43 connected to the bottom silicon nitride film 43. The membrane is exposed.

FIG. 4 illustrates a manufacturing process of the semiconductor device shown in the second embodiment. First, as shown in FIG. 4A, the semiconductor substrate 21 is subjected to S as in the first embodiment.
The element isolation region 22 is formed by the TI process. And
MO which is an element formation region surrounded by the element isolation region 22.
Impurities are introduced into the S-type semiconductor element region in order to control its threshold value, a gate oxide film 23 is formed, and then a polycrystalline silicon film 40 is deposited. Then, after appropriately introducing impurities, a WSi ₂ film 41 is deposited on the polycrystalline silicon film 40, and further silicon nitride films 44, 441 and 43 are deposited to form a gate electrode.

In this structure, after the gate oxide film 23 is formed on the semiconductor substrate 21, a layer of polycrystalline silicon is deposited,
Further, after the WSi ₂ film is formed, a silicon nitride film is formed so as to be laminated, and a gate electrode portion, a gate electrode lead portion, and a lithographic process that leaves a region corresponding to the region A are manufactured by RIE. As a result, a gate electrode is formed in the alignment mark region A in which the silicon nitride film 43 is laminated so that W does not grow when the contact hole is filled.

Subsequently, as shown in FIG. 6B, impurities are introduced into the impurity diffusion layer region forming portion to form impurity diffusion layers 241 and 242 corresponding to the source and drain, and then the semiconductor substrate 21. A silicon nitride film is deposited thereon to a film thickness of 50 to 200 nm, and etching is performed by RIE to form the sidewall insulating layer 33. At this time, the gate electrode
Although the silicon nitride films 44 and 441 deposited before processing the gate electrode and the like exist on the 25th portion and the like, if the sidewall insulating layer 33 is left by selecting an appropriate RIE time, the gate electrode Silicon nitride films 44 and 441 are also formed on the gate electrodes 40 and 41 corresponding to the region A on the electrodes 25 and 41 and the electrode lead-out portion 251.
Can be left.

Thereafter, as shown in FIG. 5A, impurities are again introduced into the impurity diffusion regions 241 and 242 if necessary, and then the impurity diffusion regions 241 and 242 are removed.
The oxide film 231 in the portion corresponding to 242 is removed, and Ti / Ti
TiSi ₂ conversion annealing is performed together with N film sputtering,
The unreacted Ti / TiN film on the element isolation region 22, the silicon nitride films 43, 44, 441, and the side wall 32 is removed, and TiSi ₂ is attached to the impurity diffusion layers 241, 242 to form a terminal layer. 311 and 312 are formed.

Next, a silicon nitride film 45 is deposited on the entire surface to a thickness of 10 to 100 nm, and then an insulating film 28 to be an interlayer insulating layer is formed by depositing a CVD oxide film and boron / phosphorus glass. . Then, a contact hole 293 is formed in the insulating film 28 by lithography / RIE only corresponding to the gate electrode lead-out portion 251. The RIE used at this time is not limited to the insulating film 28 but the gate electrode lead-out portion.
It is performed under the condition that the silicon nitride film 441 laminated on 251 is also etched.

Then, as shown in FIG. 7B, contact holes 291 and contact holes 291 and 321 are formed in the diffusion layers 341 and 342 in the terminal layers 311 and 312 and the gate electrode 25, respectively.
292 is formed, and at the same time, contact holes 301 1, 302, ... For alignment are formed in the portion corresponding to the polycrystalline silicon film 40. Contact holes 291, 292 and 301, 302, ...
Is performed by RIE / lithography, under the condition that the etching selection ratio between the oxide film and the silicon nitride film is sufficiently large so that only the oxide film is etched,
Further, RIE is continuously performed under the condition that the etching selection ratio between the silicon nitride film and the oxide film is sufficiently large and only the silicon nitride film is etched, and the borderless gate SAC as shown in the figure is opened.

By opening by such two kinds of RIE, the contact holes 291 on the diffusion regions 241 and 242 are formed.
, 292 overlaps the gate electrode 25 portion and the element isolation region 22, the impurity diffusion layer 241 is formed on the gate electrode 25 portion.
The contact holes on the contact holes 291 and 292 are opened by preventing the contact holes on the contact holes 242 and 242 from being opened and the element isolation region 22 from being etched, so that miniaturization can be effectively promoted.

In this way, the polycrystalline silicon in the region A is
In the portion corresponding to 40, the silicon nitride film 43 deposited before the processing of the gate electrode or the like exists, and therefore, the contact holes 301, 302, ... Even if the nitride film 43 is present and then W is formed by the selective CVD method,
W is not grown inside the contact holes 301, 302, .... Contact holes 291-293, 30 divided into two parts like this
After the holes 1, 302, ... Are formed, a W film is formed by the selective CVD method, excess metal is removed, as in the previous embodiment,
By flattening the insulating film 28, the semiconductor device shown in FIG. 3 is completed.

In the second embodiment, too,
Similar to the first embodiment, CMP is performed after the interlayer insulating film is deposited.
It is also possible to carry out the flattening by a method such as a method and then to open a contact hole and remove the surplus metal by a resist etch back or CMP method. Also, the element isolation region
The LOCOS method may be used to form 22 and the terminal layer 31
It is also possible to form the TiSi ₂ film only on the bottom portions of the contact holes 291 to 293 after forming the contact holes 291 to 293 without using the TiSi ₂ attachment structure for 1 and 312.

[0054]

As described above, according to the semiconductor device of the present invention, an insulating film serving as an interlayer insulating layer, together with a contact hole corresponding to a gate electrode or a diffusion layer, is used for alignment in a lithography process. Open the contact hole of
Even when the contact hole filling technique is used, metal is not filled in the contact hole for alignment, and therefore this contact hole can be used for alignment in the subsequent lithography process. Can be a position mark having. Therefore, the problem of poor connection in the contact hole portion due to the miniaturization of the semiconductor device can be solved, and the alignment in the lithography process can be performed easily and highly accurately.

[Brief description of drawings]

FIG. 1A is a sectional configuration diagram illustrating a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a plan view showing a state of arrangement of contact holes.

2A to 2C are views sequentially illustrating a manufacturing process of the semiconductor device.

FIG. 3 is a sectional configuration diagram illustrating a semiconductor device according to a second embodiment of the present invention.

4A and 4B are views for explaining a manufacturing process of the semiconductor device.

5A and 5B are views for explaining the manufacturing process of the semiconductor device, which follows FIG. 4B.

6A is a sectional view illustrating an alignment mark used in a conventional lithography process, FIG. 6B is a plan view thereof, and FIG. 6C shows a state when a metal is embedded in the alignment mark portion. Sectional drawing to demonstrate.

FIG. 7 is a cross-sectional view showing a metal wiring defect in a contact hole due to miniaturization of an element.

8A and 8B are cross-sectional views each illustrating a contact hole portion in a conventional semiconductor device.

[Explanation of symbols]

21 ... Semiconductor substrate, 22 ... Element isolation region, 23 ... Gate oxide film, 241, 242 ... Impurity diffusion layer, 25 ... Gate electrode, 251
... Gate electrode lead-out portion, 26, 261, ... TiSi ₂ film, 27 ... Silicon nitride film, 28 ... Insulating film (interlayer insulating film), 291 to 293
, 301, 302, ... Contact holes, 311, 312 ... TiS
i ₂ layer, 321 to 323 ... Contact metal, 32 ... Side wall insulating layer.

Claims (13)

[Claims] 1. A semiconductor substrate, an impurity diffusion region and a gate electrode formed in an element isolation region set on the surface of the semiconductor substrate, and a position separated from the impurity diffusion region and the region in which the gate electrode portion is formed. A growth restraining layer formed on the semiconductor substrate, the growth inhibiting layer being made of a material in which a buried metal does not grow, an insulating film layer formed so as to cover the semiconductor substrate surface, the diffusion region and a gate electrode lead portion. And a plurality of contact holes formed in the insulating film layer corresponding to the position of the growth suppressing layer, and a metal that is grown in these contact holes and is set as a lead terminal. The metal is not grown in the contact hole formed corresponding to the growth suppressing layer, and the contact hole is used for alignment in the lithography process. A semiconductor device characterized in that a step used is formed. 2. The semiconductor device according to claim 1, wherein the growth inhibiting layer comprises a silicon nitride film. 3. The semiconductor device according to claim 1, wherein the growth inhibiting layer is composed of a silicon nitride film, and the metal is tungsten. 4. The step difference remaining on the buried metal of the contact hole in which the metal is buried is set to 100 nm or less corresponding to the diffusion region and the lead-out portion of the gate electrode. Semiconductor device. 5. The step formed by the contact hole formed corresponding to the growth inhibiting layer portion has at least 1 step.
The semiconductor device according to claim 1, wherein the thickness is set to 50 nm or more. 6. The gate electrode portion is made of polycrystalline silicon, and a TiSi ₂ film is formed on the gate electrode portion and the impurity diffusion region, and is formed corresponding to the gate electrode portion and the impurity diffusion region. The semiconductor device according to claim 1, wherein the TiSi ₂ is exposed on the bottom surface of the formed contact hole. 7. A first step of forming an element formation region surrounded by an element isolation region on a surface portion of a semiconductor substrate and forming an impurity diffusion layer in the element formation region, and a gate oxide film on the surface of the semiconductor substrate. And a third step of forming a gate electrode on the gate oxide film, and a third step of depositing a non-grown substance of a buried metal on the semiconductor substrate having the gate electrode formed thereon. A fourth step of etching the formed layer of the non-grown material of the buried metal to form a growth inhibiting layer corresponding to the element isolation region outside the element formation region; and forming an insulating film on the entire surface of the semiconductor substrate. A fifth step of depositing; a step of forming a plurality of contact holes corresponding to the impurity diffusion layer portion and the gate electrode portion in the deposited insulating film and corresponding to the growth inhibiting layer position; And a seventh step of growing a metal in the contact hole. In the seventh step, the metal is grown in the contact holes corresponding to the impurity diffusion layer portion and the gate electrode portion, respectively. A method of manufacturing a semiconductor device, wherein the step is left without being grown in the contact hole corresponding to the growth inhibiting layer while being embedded. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the material in which the embedded metal forming the growth inhibiting layer is not grown is silicon nitride. 9. The non-growth material of the embedded metal forming the growth inhibiting layer is made of silicon nitride, and in the seventh step, tungsten is grown in the contact hole excluding the growth inhibiting layer. The method for manufacturing a semiconductor device according to claim 7, 10. The selective CV in the seventh step.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the metal is grown by the D method. 11. An element region setting step of forming an element formation region surrounded by an element isolation region on a surface portion of a semiconductor substrate, an oxide film formation step of forming a gate oxide film on the semiconductor substrate surface, and the gate. An etching step of sequentially stacking a polycrystalline silicon layer, a tungsten silicide layer, and a silicon nitride layer on the oxide film to form a growth inhibiting layer corresponding to the gate electrode portion and the element isolation region; Corresponding to a diffusion region forming step of introducing impurities into the semiconductor substrate at a corresponding position, an insulator layer forming step of forming an insulator layer on the entire surface of the semiconductor substrate, and a position of the gate electrode portion of the insulator layer. A first contact hole opening step of opening a contact hole penetrating the silicon nitride layer to reach the tungsten silicide layer, and the impurity diffusion of the insulator layer. A second contact hole forming step of forming contact holes at a position corresponding to the region and a position corresponding to the growth suppressing layer, respectively; and a plurality of holes formed by the first and second contact hole forming steps. A metal growth step of growing tungsten metal from the bottom of the contact hole, wherein the silicon nitride layer is exposed at the bottom of the contact hole formed at a position corresponding to the growth inhibiting layer, and tungsten is A method of manufacturing a semiconductor device, characterized in that it is grown only in a contact hole corresponding to the gate electrode portion and the impurity diffusion region. 12. The step of forming a contact hole at a position corresponding to the impurity diffusion region, the etching under the condition that the etching selection ratio between the insulating film and the silicon nitride is large, and the etching between the silicon nitride and the insulating film. The method of manufacturing a semiconductor device according to claim 11, wherein the etching under the condition of a large selection ratio is continuously performed. 13. The method of manufacturing a semiconductor device according to claim 11, wherein in the step of forming a contact hole at a position corresponding to the growth suppressing layer, etching is performed under the condition that only the insulating film is etched.